Performance test system and method for memory access system, electronic device, and storage medium

Abstract

The embodiment of the application provides a performance test system and method of a memory access system, an electronic device and a storage medium, the system comprises a configuration module, a test starting module and a universal verification methodology (UVM) memory access performance test platform; wherein the configuration module is configured to form a data file according to user test requirements; the test starting module is configured to obtain the data file, generate a test case set according to the data file, and call the UVM memory access performance test platform to construct a verification environment according to a test case in the test case set and perform performance test on the memory access system; and the UVM memory access performance test platform is configured to construct a verification environment according to a test case in the test case set, perform performance test on the memory access system, and output a UVM test log.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a performance test system and method for a memory access system, an electronic device, and a storage medium. BACKGROUND

[0002] With the rapid development of the digital integrated circuit industry and the continuous progress of the very large scale integrated circuit technology, the complexity of SOC (System on Chip) design is increasing, and chip verification, as an important part of chip reliability guarantee in the chip development stage, has become the focus of more and more enterprises. In the current rapid iteration of products, the development rate has become an important factor affecting product competitiveness. The time of chip verification accounts for about 70% of the entire chip development cycle, and the memory access system is an important part of a chip, playing an important role in reading and writing data, code, etc. If the performance test efficiency of the memory access system is improved, the efficiency of chip verification can be greatly improved.

[0003] However, in the current performance test of the memory access system, the user needs to re-write the entire verification system according to different scenarios, resulting in low automation and verification efficiency, and high development cost required for verification. SUMMARY

[0004] Embodiments of the present application provide a performance test system and method for a memory access system, an electronic device, and a storage medium, which can separate the configuration of the scene requirement from the test environment, without the need for the user to re-write the performance test system of the memory access system multiple times according to different scenarios, thereby improving the automation and verification efficiency, and reducing the verification cost.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, embodiments of the present application provide a performance test system for a memory access system, characterized in that it comprises a configuration module, a test starting module, and a UVM (Universal Verification Methodology) memory performance test platform.

[0007] The configuration module is configured to configure data files according to user test requirements, wherein the data files comprise at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0008] The test starting module is configured to acquire the data file and generate a test case set according to the data file; and invoke the UVM memory access performance test platform to construct a verification environment according to a test case in the test case set and perform performance test on the memory access system, the test case set including at least one test case, and one test case including memory access system performance configuration determined based on a set of performance mode configuration information and data mode determined based on a set of test data mode configuration information.

[0009] The UVM memory access performance test platform is configured to construct a verification environment according to a test case in the test case set and perform performance test on the memory access system, and output a UVM test log, the UVM test log including memory access system performance configuration and corresponding memory access performance result.

[0010] In a second aspect, an embodiment of the present application provides a performance test method of a memory access system, including:

[0011] According to user test requirement configuration, a data file is formed, and the data file includes at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0012] The data file is acquired, and a test case set is generated according to the data file; and the UVM memory access performance test platform is invoked to construct a verification environment according to a test case in the test case set and perform performance test on the memory access system; wherein the test case set includes at least one test case, and one test case includes memory access system performance configuration determined based on a set of performance mode configuration information and data mode determined based on a set of test data mode configuration information; and the UVM memory access performance test platform is configured to construct a verification environment according to a test case in the test case set and perform performance test on the memory access system, and output a UVM test log, the UVM test log including memory access system performance configuration information and corresponding memory access performance result.

[0013] In a third aspect, an embodiment of the present application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the following method when executing the program:

[0014] According to user test requirement configuration, a data file is formed, and the data file includes at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0015] acquire the data file, and generate a test case set according to the data file; and invoke the UVM memory access performance test platform to construct a verification environment and perform performance test on the memory access system according to a test case in the test case set; wherein the test case set comprises at least one test case, and one test case comprises memory access system performance configuration determined based on a set of performance mode configuration information and data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is configured to construct a verification environment and perform performance test on the memory access system according to a test case in the test case set, and output a UVM test log, wherein the UVM test log comprises memory access system performance configuration information and corresponding memory access performance result.

[0016] In a fourth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the following method:

[0017] According to the user test requirement configuration, a data file is formed, wherein the data file comprises at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0018] acquire the data file, and generate a test case set according to the data file; and invoke the UVM memory access performance test platform to construct a verification environment and perform performance test on the memory access system according to a test case in the test case set; wherein the test case set comprises at least one test case, and one test case comprises memory access system performance configuration determined based on a set of performance mode configuration information and data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is configured to construct a verification environment and perform performance test on the memory access system according to a test case in the test case set, and output a UVM test log, wherein the UVM test log comprises memory access system performance configuration information and corresponding memory access performance result.

[0019] The embodiments of the present application provide a performance test system and method of a memory access system, an electronic device, and a storage medium. According to user test requirement configuration, a data file is formed, and the data file is converted into a test case set, and the UVM memory access performance test platform is invoked to construct a verification environment and perform performance test on the memory access system according to a test case in the test case set, so that the user can directly configure according to different scenarios without re-writing the performance test system of the memory access system according to different scenarios, the automation level and portability of the platform can be improved, the potential verification risk caused by user errors can be reduced, the automation degree and verification efficiency can be improved, and the verification cost can be reduced.

[0020] The above description is only a summary of the technical solutions of the present application, in order to enable the technical means of the present application to be implemented according to the content of the description, and in order to enable the above and other purposes, characteristics and advantages of the present application to be more apparent and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0022] Figure 1 A structural schematic diagram of a performance test system of a memory access system provided by an embodiment of the present application is shown in the figure.

[0023] Figure 2 A structural schematic diagram of another performance test system of a memory access system provided by an embodiment of the present application is shown in the figure.

[0024] Figure 3 A test path schematic diagram of a performance test system of a memory access system provided by an embodiment of the present application is shown in the figure.

[0025] Figure 4 A flow schematic diagram of a performance test method of a memory access system provided by an embodiment of the present application is shown in the figure.

[0026] Figure 5 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0027] In order to make the purposes, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be described clearly and completely in the following with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0028] The technical solutions provided by the embodiments of the present application will be described in detail below with reference to the drawings.

[0029] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second" and the like, only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features.

[0030] In embodiments of the present application, the meaning of "multiple" is two or more, and the meaning of "at least one" is one or more, unless specifically limited otherwise.

[0031] The verification method of the mainstream storage system currently in common use needs to perform the following steps: 1. Build a verification platform. 2. Write test cases to determine the actual excitation to be sent. 3. Perform simulation, control the packet sender to send packets to the memory system. 4. Use the monitor to detect the data in each interface or memory (memory), verify that the data of the write transmission is correctly written, and the data of the read transmission can obtain correct results. However, in the current memory system performance test, according to the different scenes, the entire verification system needs to be re-written each time, the development cost of verification is high, the verification efficiency is low, the degree of automation is low, and the entire verification environment needs to be written by the user. This will lead to high costs of writing, learning and porting the verification environment, and not only is it time-consuming and laborious to use and debug, but also there may be human oversight, resulting in unexpected omissions, and the overall cost of the verification cycle is relatively high.

[0032] Based on this, the embodiments of the present application provide a performance test system of a memory system, as shown in Figure 1 The performance test system includes a configuration module 101, a test starting module 102 and a universal verification methodology (UVM) memory performance test platform 103. Wherein,

[0033] The configuration module 101 is configured to configure a data file according to the user test requirements, wherein the data file includes at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0034] The test starting module 102 is configured to obtain the data file and generate a test case set according to the data file; and call the UVM memory performance test platform to construct a verification environment according to the test cases in the test case set and perform performance test on the memory system, the test case set includes at least one test case, and one test case includes memory system performance configuration determined based on a set of performance mode configuration information and test data of a data mode determined based on a set of test data mode configuration information.

[0035] The UVM memory performance test platform 103 is configured to construct a verification environment according to the test cases in the test case set and perform performance test on the memory system, and output a UVM test log, the UVM test log includes memory system performance configuration and corresponding memory performance results.

[0036] It should be understood that, after receiving the test case delivered by the test starting module, the UVM memory access performance test platform 103 can construct a verification environment according to the test case, configure the performance of the memory access system, and perform performance testing, and then output the memory access system performance configuration and the memory access performance result corresponding to the test case. Generally, the memory access performance result can include bandwidth information and delay information of the effective data transmitted by the memory access system.

[0037] The embodiments of the present application provide a memory access system performance test system and method, an electronic device, and a storage medium. A data file is configured according to user test requirements, the data file is converted into a test case set, and a UVM memory access performance test platform is called to construct a verification environment and perform performance testing on the memory access system according to the test case in the test case set, so that the user can directly configure according to different scenarios without re-writing the performance test system of the memory access system according to different scenarios, the automation level and portability of the platform can be improved, and potential verification risks caused by user errors can be reduced, thereby improving the automation degree and verification efficiency and reducing verification costs.

[0038] Figure 2 Another structural schematic diagram of a memory access system performance test system provided by the embodiments of the present application is provided. Optionally, as shown in Figure 2 The performance test system can further include a data acquisition and processing module 104.

[0039] The data acquisition and processing module 104 is configured to analyze the UVM test log to determine whether the memory access system has a problem, determine the memory access performance result, and output the optimal memory access performance result and the corresponding memory access system performance configuration.

[0040] In the embodiments of the present application, the UVM test log is analyzed to determine whether the memory access system has a problem, determine the memory access performance result, and output the optimal memory access performance result and the corresponding memory access system performance configuration, which can improve the automation level and portability of the platform, reduce potential verification risks caused by user errors, thereby improve the automation degree and verification efficiency, and reduce verification costs.

[0041] Further, in the embodiments of the present application, the UVM memory access performance test platform 103 can include a memory access system, a packet sender submodule, and a monitor submodule.

[0042] The memory access system can refer to a memory access system in the prior art, such as a memory access system in the existing UVM memory access performance test platform.

[0043] The packet sender sub-module is configured to convert the test cases in the test case set generated by the test starting module 102 into ABMA protocol data packets, and configure the performance of the memory access system through the ABMA interface of the memory access system to build a verification environment, and perform performance testing on the memory access system.

[0044] The monitor sub-module is configured to monitor the ABMA protocol data packets through the ABMA interface, and monitor the test running results of the memory access system through the JEDEG interface of the memory access system, to output the UVM test log.

[0045] Optionally, the packet sender sub-module can further include:

[0046] The first packet sender is configured to convert the performance configuration of the memory access system in the test case into ABMA protocol data packets to configure the performance of the memory access system. Specifically, the first packet sender can configure at least one of the following performance parameters in the memory access system: port priority, data packet timeout duration, register bit width configuration, register access address, selection range of the register access address, and the like.

[0047] The plurality of second packet senders are configured to convert the data patterns in the test case into ABMA protocol data packets and deliver the ABMA protocol data packets to the memory access system to perform traversal testing or orthogonal testing.

[0048] Optionally, the monitor sub-module is specifically configured to:

[0049] Monitor the AMBA interface and the JEDEG interface of the memory access system under different requirements through the protocol configuration, the bit width configuration, and the frequency configuration, to obtain the time and the data volume of the data packets passing through each interface of the memory access system;

[0050] Determine the bandwidth and the average delay of the effective data according to the time and the data volume of the data packets passing through each interface of the memory access system;

[0051] Output the bandwidth and the average delay of the effective data corresponding to each performance configuration of the memory access system into the UVM test log.

[0052] For the convenience of understanding the technical solutions of the embodiments of the present application, the following will be described in combination with Figure 3 . Figure 3 is a schematic diagram of a test path of a performance testing system of a memory access system provided by the embodiments of the present application. As shown in Figure 3 , the UVM memory performance testing platform 300 can include a memory access system 310, a first packet sender 320, a second packet sender 330, and a monitor 340. The memory access system 310 can include a memory controller 11, a memory 12, and a configuration register 13.

[0053] AsFigure 3 The method can include:

[0054] S301, configuring a data file.

[0055] In the embodiments of the present disclosure, a test user of the memory access system can configure a data file according to a test requirement of the user. The data file includes at least one set of test data pattern configuration information and at least one set of performance pattern configuration information.

[0056] It should be understood that in the embodiments of the present disclosure, the test user of the memory access system only needs to configure the data file according to the test requirement. The test user can configure the test data pattern (Data Pattern) configuration information and the performance pattern configuration information of the memory access system in the data file according to the test requirement. One data file can be configured with one or more sets of test data pattern configuration information and one or more sets of performance pattern configuration information of the memory access system. Among them, the memory access requirement of the memory access system can be abstracted into a data pattern to simulate an actual application scenario, and one data pattern corresponds to one application scenario, which is represented by a set of test data pattern configuration information. The performance configuration of the memory access system can be represented by a performance pattern, and a set of performance pattern configuration information is used to represent one performance pattern.

[0057] It should be understood that in the embodiments of the present disclosure, the application scenarios can be divided into two categories: general application scenarios and extreme application scenarios. The general application scenario is generally some application scenarios with a relatively high frequency. The extreme application scenario is generally significantly different from the general scenario in one or more indicators, for example: a high-priority register port continuously sends data within a preset time and the amount of data sent is greater than a preset data amount threshold; the time length of the high-priority register port continuously sending data is greater than a preset time length threshold; the address span between the memory access addresses of at least two adjacent data packets is greater than a preset address span threshold; the frequency of switching data between register ports is greater than a preset switching frequency threshold, and the like. It should be understood that in actual application scenarios, the extreme application scenario is not limited to the above-mentioned content, and other application scenarios can also exist, which are not limited by the embodiments of the present disclosure.

[0058] It should be understood that the test data pattern configuration information in the data file and the performance pattern configuration information of the memory access system can be in a one-to-one relationship, a one-to-many relationship, or a many-to-many relationship, which is not limited by the embodiments of the present disclosure. For example, the test data pattern configuration information D1 can correspond to the performance pattern configuration information P1, the test data pattern configuration information D2 can correspond to the performance pattern configuration information P2 and P3, the test data pattern configuration information D3 and D4 can correspond to the performance pattern configuration information P3 and P4, and the like.

[0059] In addition, other parameters can also be configured in the data file. For example, a memory access address corresponding to the memory access system performance configuration can also be configured, and the like. Embodiments of the present application do not limit this.

[0060] To facilitate understanding of the configuration of the data file, the configuration of the register of the memory access system is taken as an example for description. Assuming that the memory access system to be tested adopts a 32-bit register, the user only needs to configure a 32-bit register in the attribute configuration of the register corresponding to the data file, so that the memory access system can be configured as a 32-bit register memory access system in subsequent configuration operations. In addition, it should be understood that the data file can adopt various data formats, and embodiments of the present application do not limit this. For example, the data file can be in txt format or ods format, and the like.

[0061] The above performance configuration attribute can be configured by the test user in the data file according to the related configuration of the configured register. For example, the performance configuration attribute can be a port priority or a data packet timeout length, a register bit width configuration, and the like, and of course can also be other performance configuration attributes, which will not be described herein. The memory access address corresponding to the above performance configuration attribute includes a register address and an optional range.

[0062] S302, starting the test script.

[0063] In embodiments of the present application, the test script can obtain the data file, and generate a test case set according to the data file; and call the UVM memory access performance test platform 300 to construct a verification environment according to the test case in the test case set and perform performance testing on the memory access system 310. It should be understood that in embodiments of the present application, the test script can use the following script languages to realize its functions: Python language, Perl language, Ruby language, and the like.

[0064] It should be understood that in step S302, the test script needs to pass the register configuration information and the data mode to the UVM memory access performance test platform 300, so as to construct a verification environment and perform performance testing in the UVM memory access performance test platform 300.

[0065] In embodiments of the present application, the test script first needs to obtain the data file, and parse the data file to obtain the at least one group of test data mode configuration information and the at least one group of performance mode configuration information, and then construct a test case set according to the at least one group of test data mode configuration information and the at least one group of performance mode configuration information. The test case set includes at least one test case, and each test case in the test case set includes a memory access system performance configuration determined based on a group of performance mode configuration information and a data mode determined based on a group of test data mode configuration information.

[0066] It should be understood that in the embodiments of the present application, the test case set includes a set of test cases required in the performance test, can include test cases constructed by a set of test data pattern configuration information and a set of performance pattern configuration information, can include test cases constructed by a set of test data pattern configuration information and multiple sets of performance pattern configuration information, can include test cases constructed by multiple sets of test data pattern configuration information and a set of performance pattern configuration information, and can also include test cases constructed by multiple sets of test data pattern configuration information and multiple sets of performance pattern configuration information. It should be understood that in the conventional test case, one test case can only execute one set of pattern configuration information under one set of register configuration. In the embodiments of the present application, a test case set including at least one set of pattern configuration and at least one set of register configuration can be automatically generated by a script. When the number of test cases in the test case set is greater than 1, the test case set can also be referred to as a regression test stimulus set, and the performance test can also be referred to as a regression simulation test, and the UVM test log can also be referred to as a regression log.

[0067] It should be understood that one performance test can be performed on the memory access system by using one test case. If the test case set includes multiple test cases, multiple performance tests can be performed by using multiple test cases. The UVM memory performance test platform can output one UVM test log each time a performance test is performed, or output all UVM test logs after all performance tests are completed.

[0068] Of course, it should be understood that at least one test case in the test case set includes at least one conventional test case corresponding to a conventional application scenario and at least one extreme test case corresponding to an extreme application scenario. Alternatively, the extreme application scenario can include an application scenario corresponding to at least one of the following data patterns:

[0069] The high-priority register port continuously sends data within a preset time and the amount of data sent is greater than a preset data amount threshold;

[0070] The high-priority register port continuously sends data for a duration greater than a preset duration threshold;

[0071] The address span between the memory access addresses accessed by at least two adjacent data packets is greater than a preset address span threshold;

[0072] The frequency of switching to send data between register ports is greater than a preset switching frequency threshold.

[0073] After the test script passes the test case to the UVM memory performance test platform 300, the UVM memory performance test platform 300 activates the first packet generator and the second packet generator according to the received test case (test case).Figure 3 In the embodiment, the plurality of second packet senders simulate the SoC master memory access behavior, and the first packet sender configures various related configurations of the memory access system, such as the priority of the port, the timeout duration of the data packet, and the like. Figure 3 In the embodiment, in order to distinguish various paths, the path in which the packet sender interacts with the memory access system is represented by a thick solid line with double arrows, the related path of the test starting module and the data acquisition and processing module is represented by a solid line with single arrows, and other paths that do not occupy simulation time are represented by dashed lines with arrows.

[0074] The first packet sender configures the memory access system according to the memory access system performance configuration in the test case. The first packet sender converts the data packet carrying the memory access system performance configuration in the test case into an Advanced Microcontroller Bus Architecture (AMBA) protocol data packet, and sends the data packet to the memory access system 310 to configure through a configuration register in the memory access system 310.

[0075] The second packet sender performs performance testing on the memory access system according to the data pattern in the test case. The second packet sender converts the data packet carrying the data pattern in the test case into an AMBA protocol data packet, and sends the data packet to the memory access system 310 to perform performance testing, which can include traversal testing, orthogonal testing, and the like.

[0076] When the test script passes the test case to the UVM memory access performance test platform 300 for performance testing, the monitor 340 in the UVM memory access performance test platform 300 monitors the performance testing process to output a UVM test log. In the embodiment, the UVM test log can include memory access system performance configuration information and corresponding memory access performance results.

[0077] The memory access system performance configuration information, such as various configuration parameters of registers in the memory access system, and the like. The memory access performance results can include the bandwidth and average delay of effective data of the memory access system. In actual applications, the memory access performance results often need to consider the average bandwidth and average delay of the memory access system. These two indicators reflect the average time and average rate required for data to be transmitted from the protocol interface end of the memory controller of the memory access system, such as the AMBA protocol interface end, to the memory interface end, such as the JEDEC (Joint Electron Device Engineering Council) interface end, to write or read the memory, which can be an important embodiment of the performance of the memory access system.

[0078] In addition, the monitor 340 can monitor the AMBA interface and JEDEG interface of the memory access system under different requirements through protocol configuration, bit width configuration and frequency configuration to obtain the time and data volume of the data packet passing through each interface of the memory access system, determine the bandwidth and average delay of the effective data according to the time and data volume of the data packet passing through each interface of the memory access system, and output the bandwidth and average delay of the effective data corresponding to each memory access system performance configuration to the UVM test log. Of course, it should be understood that the monitor can also monitor whether the memory access system itself has a bug or risk.

[0079] S303, data acquisition processing.

[0080] In the embodiment of the application, the UVM test log can be parsed by the data acquisition script to determine whether the memory access system has a problem, determine the memory access performance result, and output the optimal memory access performance result and the corresponding memory access system performance configuration.

[0081] When determining whether the memory access system has a problem, it is mainly determined whether the memory access system has a bug or risk.

[0082] When determining the memory access performance result, it is necessary to determine whether the delay and bandwidth under various conditions meet the user requirements. In particular, it is necessary to determine whether the delay and bandwidth of the test case corresponding to the extreme application scenario meet the user requirements.

[0083] In addition, the data acquisition script can also output the memory access performance configuration that can theoretically make the delay and bandwidth performance optimal and the bandwidth and delay corresponding to the optimal memory access performance configuration by comparing various memory access performance configurations and the corresponding bandwidth and delay.

[0084] It should be understood that if the bandwidth and delay corresponding to the optimal memory access performance configuration meet the user requirements, the bandwidth and delay corresponding to the optimal memory access performance configuration can be output to the chip design back-end or other related departments; if they do not meet the user requirements, optimization needs to be performed synchronously, and the above process is repeated after optimization.

[0085] The following will be illustrated by combining a specific example.

[0086] In a certain Soc memory access system, there are 8 masters that need to access the memory, each master corresponds to an IP address, and each master has a group of corresponding AMBA protocol interfaces in the memory access system. The user's requirements are: to confirm the correctness of the Soc memory access system, to confirm that the memory access system can meet the requirements of average delay and average bandwidth under all configuration conditions, and to output a group of configurations with theoretically optimal average delay and average bandwidth performance.

[0087] The performance test system of the memory access system provided in the embodiment of the present application is used for testing, and the working process includes the following steps:

[0088] Step 1: According to the information of the eight masters, the memory access requirements are determined and are abstracted into test data mode configuration information.

[0089] Step 2: Considering the extreme case that the data of the port with a lower priority is in the cache area, the port with a higher priority continuously sends a large amount of data, and the extreme case is abstracted into limit data mode configuration information.

[0090] Step 3: According to the actual register design, sixteen memory access performance related performance configuration attributes are extracted, that is, the priorities of the eight port, the time length of the data packet timeout of the eight port, and the register address and optional range of each configuration attribute are set according to the register address specification document of the memory access system.

[0091] Step 4: The test start script is called, and the data files generated in the previous three steps are specified.

[0092] Step 5: The test start script automatically generates a regression test stimulus set (that is, a test case set), and controls the UVM memory access performance test platform to automatically perform regression simulation (that is, performance test); after all the simulation is completed, the UVM test log is output.

[0093] Step 6: The data acquisition script acquires the information in the UVM test log, outputs the overall regression result: whether the memory access system has a bug, whether the memory access performance of each data mode meets the requirements, and in the case of meeting the requirements, outputs the theoretically best memory access performance data and controller configuration.

[0094] Step 7: According to the log output by the data acquisition script, the corresponding result is obtained, and it is confirmed whether the memory access system meets the requirements.

[0095] Of course, it should be understood that the foregoing steps 1-7 are only illustrative, and in actual applications, some of the steps can be added, deleted or combined, or the order of the steps can be adjusted, and the embodiment of the present application does not limit this.

[0096] Figure 4 is a performance test method flowchart of the memory access system of the embodiment of the present application. As shown in Figure 4 , the performance test method can include:

[0097] S401: Forming a data file according to user test requirement configuration.

[0098] The data file includes at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0099] S402, acquiring the data file, and generating a test case set according to the data file; and calling the UVM memory access performance test platform to construct a verification environment and perform performance test on the memory access system according to the test cases in the test case set.

[0100] The test case set includes at least one test case, and each test case includes memory access system performance configuration determined based on a set of performance mode configuration information and data mode determined based on a set of test data mode configuration information. The UVM memory access performance test platform is configured to construct a verification environment and perform performance test on the memory access system according to the test cases in the test case set, and output a UVM test log including memory access system performance configuration information and corresponding memory access performance results.

[0101] Optionally, as shown in Figure 4 the test method can further include:

[0102] S403, analyzing the UVM test log to determine whether there is a problem with the memory access system, and determine the memory access performance results, and output the optimal memory access performance results and corresponding memory access system performance configuration.

[0103] Figure 4 The specific implementation of each step in the embodiment shown in Figure 1 , Figure 2 The specific implementation of the corresponding modules in the embodiment shown in, or the specific implementation of the corresponding steps S301, S302 and S303 in the embodiment shown in, will not be described herein. Figure 3

[0104] Figure 5 An electronic device structure schematic diagram is provided for an embodiment of the present specification, referring to Figure 5 The electronic device includes a processor, an internal bus, a network interface, a memory and a non-volatile memory, and of course can also include other hardware required by the business. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs, and forms a performance test device or performance test system of the memory access system at the logical level. Of course, in addition to the software implementation, the present specification does not exclude other implementation manners, such as logic devices or software and hardware combined manner, etc., that is, the execution subject of the following processing flow is not limited to each logical unit, but can also be hardware or logic device.

[0105] ​The network interface, the processor and the memory can be connected with each other through a bus system. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 5 Only one bidirectional arrow is used to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0106] The memory is used to store programs. Specifically, the program can include program code, which includes computer operation instructions. The memory can include read-only memory and random access memory, and provide instructions and data to the processor. The memory can include high-speed random access memory (RAM), and can also include non-volatile memory, such as at least one disk memory.

[0107] The processor is configured to execute the program stored in the memory, and specifically execute the following steps:

[0108] According to the user test requirement configuration, a data file is formed, wherein the data file includes at least one set of test data mode configuration information and at least one set of performance mode configuration information;

[0109] The data file is obtained, and a test case set is generated according to the data file; and the UVM memory access performance test platform is called to construct a verification environment according to the test cases in the test case set and perform performance test on the memory access system; wherein the test case set includes at least one test case, and one test case includes memory access system performance configuration determined based on a set of performance mode configuration information and data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is configured to construct a verification environment according to the test cases in the test case set and perform performance test on the memory access system, and output a UVM test log, wherein the UVM test log includes memory access system performance configuration information and corresponding memory access performance results.

[0110] Optionally, the processor can further execute the following steps:

[0111] The UVM test log is parsed to determine whether the memory access system has a problem, and to determine a memory access performance result, and output an optimal memory access performance result and a corresponding memory system performance configuration.

[0112] The performance test method disclosed in the embodiments shown in the above Figure 3 、 The performance test method disclosed in the embodiments shown in the above 4 may be applied to a processor or implemented by a processor. The processor can be an integrated circuit chip having a signal processing capability. In the implementation process, each step of the above method can be completed by integrated logic circuits in hardware or instructions in software form in the processor. The processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; or a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiments of the present specification can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present specification can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0113] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the performance test method shown in the above Figure 3 、 Figure 4 .

[0114] It has to be understood that the terms "including", "containing" or any other similar terms are intended to be open-ended terms that specify the presence of the stated features, integers, steps, components, elements, or the like, but do not preclude the presence or addition of one or more other features, integers, steps, components, elements, or the like.

[0115] As will be appreciated by one skilled in the art, embodiments of the present application can be embodied as a method, system, or computer program product. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer readable program code.

[0116] As used herein, the terms "one embodiment", "an embodiment" or "one or more embodiments” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0117] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description. It will be appreciated, however, by those skilled in the art that the application can be practiced without such specific details. In other instances, well-known structures have not been described in detail in order not to obscure the understanding of this description. Finally, it should be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading the above description and the examples that follow. Therefore, although the application has been described with reference to particular embodiments thereof, it is to be understood that these embodiments are not intended to limit the application. To the contrary, it is intended to cover all alternatives, modifications and equivalents falling within the spirit and scope of the application as defined by the appended claims.

Claims

1. A performance testing system for a memory access system, characterized in that, include: Configuration module, test startup module, and UVM memory access performance testing platform (a general verification methodology); in The configuration module is used to configure and form a data file according to the user's testing requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information; The test startup module is used to acquire the data file and generate a set of test cases based on the data file; and to call the UVM memory access performance test platform to build a verification environment based on the test cases in the set of test cases and perform performance testing on the memory access system. The set of test cases includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information. The UVM memory access performance testing platform is used to build a verification environment based on the test cases in the test case set and perform performance testing on the memory access system, and output UVM test logs, which include: memory access system performance configuration and corresponding memory access performance results. The UVM memory access performance testing platform includes: a memory access system; a packet sender submodule, used to convert test cases in the test case set into AMBA protocol data packets, configure the memory access system's performance through the AMBA interface to build a verification environment, and perform performance testing on the memory access system; and a monitor submodule, used to monitor the AMBA protocol data packets through the AMBA interface, monitor the test execution results of the memory access system through the JEDEG interface of the memory access system, and output the UVM test log.

2. The performance testing system according to claim 1, characterized in that, The performance testing system also includes: The data acquisition and processing module is used to parse the UVM test logs to determine whether there are problems with the memory access system, determine the memory access performance results, and output the optimal memory access performance results and the corresponding memory access system performance configuration.

3. The performance testing system according to claim 1 or 2, characterized in that, The memory access performance results include bandwidth and latency information of the effective data transmitted by the memory access system.

4. The performance testing system according to claim 1, characterized in that, The packet sender submodule includes: The first packet sender is used to convert the memory access system performance configuration in the test case into AMBA protocol data packets to configure the performance of the memory access system. Multiple second packet senders are used to convert the data patterns in the test cases into AMBA protocol data packets and pass them to the memory access system for traversal testing or orthogonal testing.

5. The performance testing system according to claim 4, characterized in that, The first packet sender is specifically used to configure at least one of the following performance parameters of the memory access system: Port priority, packet timeout duration, register width configuration, register address.

6. The performance testing system according to claim 1, characterized in that, The monitor submodule is specifically used for: By monitoring the AMBA and JEDEG interfaces of the memory access system under different requirements through protocol configuration, bit width configuration, and frequency configuration, the time and amount of data packets passing through each interface of the memory access system can be obtained. The bandwidth and average latency of valid data are determined based on the time and amount of data packets passing through each interface of the memory access system. The bandwidth and average latency of the valid data corresponding to the performance configuration of each memory access system are output to the UVM test log.

7. The performance testing system according to claim 1, characterized in that, The at least one test case includes a test case corresponding to an extreme application scenario, and the extreme application scenario includes at least one of the following data patterns: The high-priority register port continuously sends data within a preset time and the amount of data sent exceeds a preset data amount threshold. The duration of continuous data transmission from the high-priority register port exceeds a preset duration threshold. The address span between the memory access addresses accessed by at least two adjacent data packets is greater than a preset address span threshold; The frequency of switching data transmission between register ports exceeds the preset switching frequency threshold.

8. A performance testing method for a memory access system, characterized in that, include: A data file is configured according to the user's testing requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information; The system acquires the data file and generates a test case set based on the data file; it then invokes the UVM memory access performance testing platform to build a verification environment based on the test cases in the test case set and performs performance testing on the memory access system; wherein the test case set includes at least one test case, and each test case includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; the UVM memory access performance testing platform is used to build a verification environment based on the test cases in the test case set, perform performance testing on the memory access system, and output UVM test logs. The UVM test log includes: memory access system performance configuration information and corresponding memory access performance results; the UVM memory access performance test platform includes: a memory access system; a packet sender submodule, used to convert test cases in the test case set into AMBA protocol data packets, and to configure the memory access system's performance through the AMBA interface of the memory access system to build a verification environment, and to perform performance testing on the memory access system; a monitor submodule, used to monitor the AMBA protocol data packets through the AMBA interface, and to monitor the test execution results of the memory access system through the JEDEG interface of the memory access system, so as to output the UVM test log.

9. The method according to claim 8, characterized in that, Also includes: The UVM test logs are parsed to determine if there are any problems with the memory access system, to determine the memory access performance results, and to output the optimal memory access performance results and the corresponding memory access system performance configuration.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the performance testing method as described in any one of claims 8-9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the performance testing method as described in any one of claims 8-9.

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