Signal transmission system and signal transmission method

Abstract

The invention discloses a signal transmission system and a signal transmission method. A signal transmission system includes: a signal transmission circuit for receiving an input signal to generate an output signal; and a signal timing adjustment circuit for adjusting the output timing of the output signal according to the signal mode of the input signal.

Description

Technical Field

[0001] The present invention relates to a signal transmission system and a signal transmission method, and in particular to a signal transmission system and a signal transmission method capable of improving reception success rate, reception stability and anti-noise capability. Background Art

[0002] DRAM (Dynamic random-access memory) is a popular electronic device in modern times. It usually includes a data transmission circuit to receive data and correctly transmit the data to DRAM. However, the data is often delayed during transmission due to the transmission path. The impact of these delays is particularly obvious when the DRAM has a higher operating speed or the data has a specific data format, which in turn affects the signal quality of the signal received by the DRAM end and reduces the success rate of DRAM receiving data. Summary of the invention

[0003] An object of the present invention is to provide a signal transmission system, which can allow the signal received by the receiving end to have better signal quality, lower noise, and better data reception success rate.

[0004] Another object of the present invention is to provide a signal transmission method, which can allow the signal received by the receiving end to have better signal quality, lower noise, and better data reception success rate.

[0005] An embodiment of the present invention discloses a signal transmission system, comprising: a signal transmission circuit for receiving an input signal to generate an output signal; and a signal timing adjustment circuit for adjusting the output timing of the output signal according to the signal mode of the input signal.

[0006] Another embodiment of the present invention discloses a signal transmission method, comprising: using a signal transmission circuit to receive an input signal to generate an output signal; and using a signal timing adjustment circuit to adjust the output timing of the output signal according to a signal mode of the input signal.

[0007] According to the aforementioned embodiments, the output timing of the output signal can be adjusted according to the signal mode, so that the signal received by the receiving end has better signal quality, lower noise, and better data reception success rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of a signal transmission system according to one embodiment of the present invention is depicted.

[0009] Figure 2 A circuit diagram of a signal transmission circuit according to one embodiment of the present invention is depicted.

[0010] Figure 3 Depicted is a diagram according to one embodiment of the present invention, Figure 2 The operation schematic diagram of the signal transmission circuit shown.

[0011] Figure 4 , Figure 5 and Figure 6 Circuit diagrams of signal timing adjustment circuits according to various embodiments of the present invention are depicted.

[0012] Figure 7 A schematic diagram depicting an eye diagram at a receiving end when signal transmission is not compensated and an eye diagram at a receiving end after signal transmission is compensated.

[0013] Figure 8 A flow chart of a signal transmission method according to an embodiment of the present invention is depicted. DETAILED DESCRIPTION

[0014] The content of the present invention will be described below with multiple embodiments. Please also note that the elements in each embodiment can be implemented by hardware (such as a device or circuit) or software (such as at least one program written in a microprocessor). In addition, the "first", "second" and similar descriptions in the following description are only used to define different elements, parameters, data, signals or steps. They are not used to limit their order. For example, the first device and the second device can be devices with the same structure but different.

[0015] Figure 1 1 is a block diagram of a signal transmission system 100 according to an embodiment of the present invention. Figure 1 As shown, the signal transmission system 100 includes a signal transmission circuit 101 and a signal timing adjustment circuit 103. The signal transmission circuit 101 is used to receive an input signal IS to generate an output signal OS. The signal timing adjustment circuit 103 is used to adjust the output timing of the output signal OS according to the signal pattern of the input signal IS. In more detail, in one embodiment, the signal pattern represents the bit distribution state of the input signal IS, such as 00001111 or 01010101. The output timing represents the high and low logic levels of the output signal OS and the timing of the positive edge and the negative edge. In one embodiment, the ratio relationship of the high and low logic levels of the output signal OS and the timing relationship of the positive edge and the negative edge are the same before and after being adjusted by the signal timing adjustment circuit 103. In other words, the action of the signal timing adjustment circuit 103 to adjust the output timing of the output signal OS does not affect the waveform of the output signal OS. In one embodiment, the signal transmission system 100 is a DRAM data transmission system, so both the input signal IS and the output signal OS include data to be transmitted to the DRAM.

[0016] In one embodiment, if the signal pattern has at least two consecutive first bits and a second bit following the first bit, the signal timing adjustment circuit causes the output signal to be output in advance, and the first bit and the second bit have different logic values. In one embodiment, the first bit is 0 and the second bit is 1, for example, the signal pattern has a bit distribution of 001. In one embodiment, the first bit is 1 and the second bit is 0, for example, the signal pattern has a bit distribution of 110. The advantage of this method is that when a signal has consecutive bits with the same logic value and then performs a logic value conversion, it takes time to convert the logic value. In this case, the delay caused by the transmission path of the signal transmission circuit 101 or the transmission path before it will be quite obvious, so that the signal quality received by the receiving end (such as the DRAM end) will become poor due to the delay, thereby affecting the accurate reception rate of the data. Therefore, if the output signal OS with such a signal pattern is output in advance, the aforementioned delay problem can be compensated.

[0017] Figure 2 1 is a circuit diagram of a signal transmission circuit 101 according to an embodiment of the present invention. Figure 2 As shown, the triggers DL_11, DL_12 and the multiplexer MUX_11 constitute two first shift registers, which generate a first signal mux_a according to multiple positive edges of a control signal mck_dq. The triggers DL_21, DL_22 and the multiplexer MUX_12 constitute two second shift registers, which generate a second signal mux_b according to multiple negative edges of the control signal mck_dq. The multiplexer MUX_O is used to selectively output the first signal mux_a or the second signal mux_b according to the control signal mck_dq to generate an output signal OS. Figure 2 In the embodiment, Figure 1 The input signal IS contains data dato_p, dato_n.

[0018] Figure 3 Depicted is a diagram according to one embodiment of the present invention, Figure 2 The operation diagram of the signal transmission circuit is shown in FIG. Figure 2 as well as Figure 3 As shown, the control signal mck_dq is used to control the first multiplexer MUX_O to select which of the first signal mux_a and the second signal mux_b to output. When the control signal mck_dq has a high logic level, the first multiplexer MUX_O outputs the second signal mux_b as the output signal OS. On the contrary, when the control signal mck_dq has a low logic level, the first multiplexer MUX_O outputs the first signal mux_a as the output signal OS.

[0019] Figure 4 , Figure 5 as well as Figure 6 The circuit diagram of the signal timing adjustment circuit according to different embodiments of the present invention is depicted. In the following embodiments, the output signal OS represents a signal output to a connection pad of a target electronic device (such as a DRAM) after being processed by the signal transmission circuit or the signal transmission circuit and the signal timing adjustment circuit. Figure 4 In the embodiment of the present invention, the signal transmission system 400 includes Figure 2 In addition to the signal transmission circuit 101 shown, a duty cycle control circuit 401 is further included. The duty cycle control circuit 401 is used to control a duty cycle (i.e., the ratio of the high logic level and the low logic level) of the control signal mck_dq to adjust the output timing accordingly. As described above, when the control signal mck_dq has a high logic level, the multiplexer MUX_O outputs the second signal mux_b as the output signal OS. On the contrary, when the control signal mck_dq has a low logic level, the multiplexer MUX_O outputs the first signal mux_a as the output signal OS. Therefore, the duty cycle control circuit 401 generates an adjusted control signal amck_dq by adjusting a duty cycle of mck_dq, and generates the output signal OS according to the high logic level and the low logic level of the adjusted control signal amck_dq, so as to adjust the output timing of the output signal OS. As described above, the output timing represents the high and low logic levels of the output signal OS and the timing of the positive edge and the negative edge. In one embodiment, the ratio of the high and low logic levels of the output signal OS generated according to the control signal mck_dq, and the timing relationship of the positive edge and the negative edge are the same as the ratio of the high and low logic levels of the output signal OS generated according to the adjusted control signal amck_dq, and the timing relationship of the positive edge and the negative edge. In other words, the waveform of the output signal OS generated according to the control signal mck_dq and the waveform of the output signal OS generated according to the adjusted control signal amck_dq are the same. For example Figure 3 As shown in , the output signal OS is adjusted to the output signal OS' to be outputted in advance. The adjusted duty cycle of the control signal mck_dq may vary depending on the state of the input data IS, so it is not depicted here.

[0020] exist Figure 5 In the embodiment of the present invention, the signal transmission system 500 includes Figure 2In addition to the signal transmission circuit 101 shown, it further includes a delay circuit 501 and a second multiplexer MUX_2. The delay circuit 501 is used to receive a first output signal OS_1 generated by the signal transmission circuit to generate a delayed output signal OS_d. The second multiplexer MUX_2 is used to selectively output the first output signal OS_1 and the delayed output signal OS_d as the output signal OS. In one embodiment, when the signal transmission system 500 operates in a normal state, that is, when the output signal OS does not need to be compensated, the second multiplexer MUX_2 will output the delayed output signal OS_d as the output signal OS. When the signal transmission system 500 operates in a calibration state, that is, when the output timing of the output signal OS needs to be adjusted for compensation, the second multiplexer MUX_2 will output the first output signal OS_1 as the output signal OS, so as to advance the output timing of the output signal OS.

[0021] The aforementioned delay circuit 501 and the second multiplexer MUX_2 can be replaced by an adjustable delay circuit. Figure 6 In the embodiment of the present invention, the signal transmission system 600 includes Figure 2 In addition to the components shown, an adjustable delay circuit 601 is further included. The adjustable delay circuit 601 is used to delay the first output signal OS_1 to adjust the output timing of the output signal OS accordingly. In one embodiment, when the signal transmission system 600 operates in a normal state, that is, when the output signal OS does not need to be compensated, the adjustable delay circuit 601 will have a larger delay amount. When the signal transmission system 600 operates in a calibration state, that is, when the output signal OS needs to be compensated, the adjustable delay circuit 601 will have a smaller delay amount to advance the output timing of the output signal OS.

[0022] In the above-mentioned embodiment, the output signal OS is outputted in advance to improve the signal quality. However, the output signal OS may also be outputted later to improve the signal quality.

[0023] As mentioned above, the delay caused by the transmission path of the signal transmission circuit 101 or the transmission path before it will make the signal quality received by the receiving end (such as the DRAM end) worse due to the delay, thereby affecting the accurate reception rate of the data. Therefore, if the output timing of the output signal OS is changed, the aforementioned delay problem can be compensated. The quality of the signal can be represented by the eye width of the signal eye diagram. Figure 7 The diagram depicts the eye diagram E_1 at the receiving end when the signal transmission is not compensated and the eye diagram E_2 at the receiving end after the signal transmission is compensated. Figure 7As shown, eye diagram E_1 has eye width W_1 and eye diagram E_2 has eye width W_2. Eye width W_2 is greater than eye width W_1, so the signal quality represented by eye diagram E_2 is higher than the signal quality represented by eye diagram E_1. The eye width of the eye diagram also corresponds to the part where data can be received more accurately, so when the state of the signal corresponds to eye diagram E_2, the receiving end will also have a better data reception rate.

[0024] According to the aforementioned embodiments, a signal transmission method can be obtained. Figure 8 A flow chart of a signal transmission method according to an embodiment of the present invention is depicted, which comprises the following steps:

[0025] Step 801

[0026] A signal transmission circuit receives an input signal to generate an output signal.

[0027] For example Figure 1 The input signal IS and the output signal OS in the DRAM may include data to be provided to the DRAM.

[0028] Step 803

[0029] A signal timing adjustment circuit is used to adjust the output timing of the output signal according to the signal mode of the input signal, for example, to allow the output signal to be output in advance.

[0030] According to the aforementioned embodiments, the output timing of the output signal can be adjusted according to the signal mode, so that the signal received by the receiving end has better signal quality, lower noise, and better data reception success rate.

[0031] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0032] Explanation of symbols

[0033] 100, 400, 500, 600: signal transmission system; 101: signal transmission circuit; 103: signal timing adjustment circuit; 401: duty cycle control circuit; 501: delay circuit; 601: adjustable delay circuit; DL_11, DL_12, DL_21, DL_22: triggers; MUX_11, MUX_12: multiplexers; MUX_O: first multiplexer; MUX_2: second multiplexer.

Claims

1. A signal transmission system, comprising: a signal transmission circuit for receiving an input signal to generate an output signal; and A signal timing adjustment circuit is used to adjust the output timing of the output signal according to the signal mode of the input signal. 2 . The signal transmission system as claimed in claim 1 , wherein the signal timing adjustment circuit outputs the output signal in advance according to a signal mode of the input signal.

3. The signal transmission system as claimed in claim 1, wherein if the signal pattern has at least two consecutive first bits and a second bit following the first bits, the signal timing adjustment circuit causes the output signal to be output in advance, and the first bit and the second bit have different logic values. The signal transmission system as claimed in claim 3 , wherein the first bit is 0 and the second bit is 1. The signal transmission system as claimed in claim 3 , wherein the first bit is 1 and the second bit is 0.

6. The signal transmission system as claimed in claim 1, wherein the signal transmission circuit comprises: A plurality of first shift registers generate a first signal according to a plurality of positive edges of the control signal: A plurality of second shift registers generate a second signal according to a plurality of negative edges of the control signal; and A first multiplexer is used for selectively outputting the first signal or the second signal according to the control signal to generate the output signal. 7 . The signal transmission system as claimed in claim 6 , wherein the signal timing adjustment circuit further comprises a duty cycle control circuit, the duty cycle control circuit is used to control a duty cycle of the control signal to adjust the output timing accordingly. 8 . The signal transmission system as claimed in claim 1 , wherein the signal timing adjustment circuit further comprises an adjustable delay circuit, and the adjustable delay circuit is used to delay the output signal to adjust the output timing accordingly.

9. The signal transmission system as claimed in claim 1, wherein the signal timing adjustment circuit comprises: a delay circuit, for receiving a first output signal generated by the signal transmission circuit to generate a delayed output signal; and A second multiplexer is used for selectively outputting the first output signal and the delayed output signal as the output signal.

10. A signal transmission method, comprising: Receiving an input signal with a signal transmission circuit to generate an output signal; and A signal timing adjustment circuit is used to adjust the output timing of the output signal according to the signal mode of the input signal.

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