Direct memory access device, method and equipment based on single-port SRAM (Static Random Access Memory) and medium

Abstract

The invention relates to the technical field of data transmission, and discloses a direct memory access device, method and equipment based on a single-port SRAM (Static Random Access Memory) and a medium, the direct memory access device based on the single-port SRAM comprises a request management unit and an SRAM array, the request management unit is used for generating a read request according to the received descriptor information so as to obtain write-in data from the memory network and send the write-in data to the SRAM array, or generating a write request so as to obtain write-out data from the SRAM array and send the write-out data to the memory network; the SRAM array is used for buffering data and is composed of a plurality of single-port SRAMs. Through the SRAM array composed of the single-port SRAMs, the working frequency of the direct memory access method is improved, a higher bandwidth is achieved, data write-in or write-out between the single-port SRAMs does not interfere with each other, and the stability of data transmission is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a direct memory access device, method, equipment and medium based on a single-port SRAM. Background Art

[0002] At present, DMA (direct memory access) is mainly developed in terms of function richness, realizing different types of deep customization in various scenarios, and adding various special or general functions. Nowadays, various types of DMA generally use dual-port SRAM (static random access memory) as data buffer.

[0003] However, the upper limit of DMA frequency implemented by dual-port SRAM is limited by the dual-port SRAM implementation. Specifically, dual-port SRAM has two independent read and write ports, which means that it requires a more complex circuit structure to support the parallel operation of the two ports. This complexity not only increases the design difficulty, but also leads to higher power consumption. Moreover, when the two ports of the dual-port SRAM operate on the same row at the same time, read and write interference will occur. This interference may cause data read errors or write failures, reducing the stability of the storage unit.

[0004] Therefore, there is an urgent need for a method that can improve the upper frequency limit of the direct memory access method and reduce read and write interference to make up for the defects of the direct memory access method based on dual-port SRAM. Summary of the invention

[0005] In view of this, the present application provides a direct memory access device, method, equipment and medium based on a single-port SRAM, which improves the frequency upper limit of direct memory access. The technical solution is as follows.

[0006] In a first aspect, the present invention provides a direct memory access device based on a single-port SRAM, the device comprising: a request management unit, an SRAM array;

[0007] The request management unit is used to generate a read request to obtain write data from the memory network and send it to the SRAM array, or generate a write request to obtain write data from the SRAM array and send it to the memory network according to the received descriptor information;

[0008] The SRAM array is used for buffering data and is composed of a number of single-port SRAMs.

[0009] The direct memory access device based on single-port SRAM provided by the present invention has the following advantages.

[0010] The direct memory access device based on single-port SRAM of the present invention comprises a request management unit and an SRAM array; the request management unit is used to receive descriptor information and separate corresponding write requests or read requests therefrom; the descriptor information is forwarded to the request management unit by a descriptor status management module, the read request in the descriptor information includes the amount of data to be transmitted and the source address, and the write request includes the amount of data to be transmitted and the target address; the separated read request is sent to the memory network, various bus interfaces are parsed according to various bus interface protocols, write data is obtained from the memory network, and the data is written into the SRAM array, or write data is obtained from the SRAM array through the separated write request and the data is sent to the memory network. The SRAM array is used to buffer data and is composed of a plurality of single-port SRAMs, each single port can perform read and write control separately, can control a single-port SRAM to write, and control another single-port SRAM to read at the same time, when a single-port SRAM receives a write request and a read request at the same time, arbitration is required, and the read request or the write request is selected and processed according to the set read and write priority. Since single-port SRAM only processes read requests or write requests at the same time, it consumes less power than dual-port SRAM, and can increase the upper frequency limit of direct memory access. Single-port SRAM does not process read and write requests at the same time, so it has lower read and write interference than dual-port SRAM. In addition, the area of ​​single-port SRAM is smaller than that of dual-port SRAM, which can reduce the area of ​​chip design.

[0011] In an optional embodiment, the device further includes: a local buffer control module, which is used to control the request management unit to send write data to the SRAM array according to the read request, or to control the request management unit to obtain write data from the SRAM array according to the write request.

[0012] In an optional embodiment, the device also includes: an arbitration module, which is used to select a corresponding single-port SRAM from the SRAM array to receive write data according to the read request; or select a corresponding single-port SRAM from the SRAM array to obtain write data according to the write request.

[0013] In an optional implementation, the arbitration module is further used to: when the read request and the write request need to read and write the same single-port SRAM, arbitrate the read request and the write request according to a preset request priority so that the read request and the write request are executed in sequence according to priority.

[0014] The direct memory access device based on a single-port SRAM of the present invention is provided with an arbitration module, which is used to perform arbitration according to a read request and a write request, write data to a corresponding single-port SRAM in an SRAM array or read data from a corresponding single-port SRAM in an SRAM array according to the arbitration result, and when a write request and a read request point to the same single-port SRAM in the SRAM array, priority arbitration is performed on the write request and the read request, and a read request or a write request is selected according to a set priority.

[0015] In an optional embodiment, the request management unit includes a read request unpacking module, a read request sending module, and a read feedback processing module; the read request unpacking module is used to generate a read request according to the descriptor information; the read request sending module is used to send the read request to the memory network; the read feedback processing module is used to obtain write data from the memory network and send it to the SRAM array.

[0016] In an optional embodiment, the request management unit also includes a write request unpacking module, a prefetch control module, a prefetch buffer module, and a write packet sending module; the write request unpacking module is used to generate a write request according to the data amount of the write data and the buffer space in the prefetch buffer module; the data amount of the write data is obtained from the descriptor information; the prefetch control module is used to obtain the write data as prefetch data from the corresponding single-port SRAM according to the write request, and send it to the prefetch buffer module; the prefetch buffer module is used to store the prefetch data and the corresponding write request; the write packet sending module is used to send the prefetch data and the corresponding write request to the memory network.

[0017] In an optional embodiment, the prefetch control module includes several read data buffer request modules; the read data buffer request module is used to receive each write data request in the write request, and arbitrate the status of the read data buffer request module through the arbitration module; and select the corresponding read data buffer request module to process the write data request according to the arbitration result.

[0018] In an optional embodiment, the corresponding read data buffer request module is selected according to the arbitration result to process the write data request, including: if the arbitration result indicates that the current read data buffer request module is in an idle state, the write data corresponding to the current write data request is written into the prefetch buffer module, and after the write data is written, the state of the current read data buffer request module is changed to an idle state; if the arbitration result indicates that the current read data buffer request module is in a busy state, the current write data request is sent to the next read data buffer request module for arbitration; if the arbitration result indicates that the current read data buffer request module is in a busy state and the subsequent read data buffer request module of the current read data buffer request module is in a busy state, the current write data request is blocked from being passed backward.

[0019] In an optional embodiment, the method of selecting a corresponding read data buffer request module to process the write data request based on the arbitration result also includes: if the arbitration result indicates that more than one read data buffer request module is in an idle state, selecting a read data buffer request module with a higher priority according to the preset priority of the read data buffer request module to process the write data request.

[0020] The direct memory access device based on single-port SRAM of the present invention is also provided with a pre-fetch control module. Since a write request may correspond to several beats of data, the pre-fetch control module also includes several read data buffer request modules, which split the write request into multiple read single-port SRAM requests and send them to the read data buffer request module, and then arbitrate according to the status of each read data buffer request module. If the current read data buffer request module is in an idle state, the read data buffer request module processes the request of this beat. If the current read data buffer request module is in a busy state, the request of this beat is passed to the next read data buffer request module for continued arbitration. If all read data buffer request modules are traversed and no idle read data buffer request module is found, the request of this beat is temporarily blocked from being passed backward, waiting for an idle read data buffer request module to process the request of this beat. If multiple read data buffer request modules are in an idle state, arbitration is performed according to the set processing priority, and a read data buffer request module with a high priority is selected to process the request of this beat. Such a setting can split the write request, improve the processing efficiency, and can also give full play to the advantages of the single-port SRAM array and improve the overall frequency upper limit.

[0021] In a second aspect, the present invention provides a direct memory access method based on a single-port SRAM, which is applied to the direct memory access device based on a single-port SRAM of the first aspect or any corresponding embodiment thereof, and the method comprises:

[0022] A read request is obtained according to the received descriptor information; write data is obtained from the memory network according to the read request; and the write data is written into the SRAM array.

[0023] In an optional embodiment, the method further includes: obtaining a write request based on the received descriptor information; the write request includes the amount of write data that needs to be obtained; when the amount of the write data is less than or equal to the amount of local buffered data stored in the SRAM array, obtaining the write data from the SRAM array based on the write request; and sending the write data to the memory network.

[0024] In an optional embodiment, before the step of obtaining write data from the SRAM array according to the write request, it also includes: determining whether the buffer space in the prefetch data buffer is not full; if the buffer space is not full, obtaining the prefetch write data from the SRAM array according to the write request, and storing the prefetch write data in the prefetch data buffer; obtaining the prefetch buffer data from the prefetch data buffer and sending it to the memory network.

[0025] In an optional implementation, the method further includes: if the descriptor information includes a read request and a write request, processing the write request and the read request according to preset priorities.

[0026] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the direct memory access method based on a single-port SRAM of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0027] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the direct memory access method based on a single-port SRAM according to the first aspect or any corresponding embodiment thereof.

[0028] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the direct memory access method based on a single-port SRAM according to the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 The diagram is a schematic structural diagram of a direct memory access based on a single-port SRAM according to an exemplary embodiment.

[0031] Figure 2 It is a structural diagram of a write request splitting and pre-fetching control module according to an exemplary embodiment.

[0032] Figure 3 The present invention is a schematic diagram of a read request processing flow of a direct memory access method based on a single-port SRAM according to an exemplary embodiment.

[0033] Figure 4 The present invention is a schematic diagram of a write request processing flow of a direct memory access method based on a single-port SRAM according to an exemplary embodiment.

[0034] Figure 5 It is a structural schematic diagram of a computer device provided by an optional embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0036] It should be understood that the "indication" mentioned in the embodiments of the present application can be a direct indication, an indirect indication, or an indication of an association relationship. For example, A indicates B, which can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association relationship between A and B.

[0037] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0038] In an embodiment of the present application, "predefinition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including a terminal device and a network device). The present application does not limit its specific implementation method.

[0039] Currently, DMA is mainly developed in terms of functional richness, realizing different types of deep customization in various scenarios, and adding various special or general functions. Nowadays, various types of DMA usually use dual-port SRAM as data buffer.

[0040] However, the upper limit of the DMA frequency of the dual-port SRAM implementation is limited by the dual-port SRAM implementation. The operating frequency of the single-port SRAM is much higher than that of the dual-port SRAM at the same depth. This solution will reduce the depth while replacing the dual-port SRAM, which can further increase the operating frequency of the single-port SRAM. The increase in the SRAM operating frequency can further increase the operating frequency of the entire design and achieve higher bandwidth.

[0041] Therefore, an embodiment of the present invention provides a direct memory access device based on a single-port SRAM. By setting an SRAM array based on a single-port SRAM, the operating frequency of direct memory access can be improved. The structure of the device is as follows: Figure 1 As shown, it includes a request management unit and an SRAM array;

[0042] The request management unit is used to generate a read request to obtain write data from the memory network and send it to the SRAM array, or to generate a write request to obtain write data from the SRAM array and send it to the memory network according to the received descriptor information.

[0043] The descriptor information is received and managed by the descriptor status management module, which sends the read and write information to the read request unpacking and write request unpacking parts respectively according to the descriptor content. Specifically, the descriptor status management part sends the transmission data volume and source address to the read request unpacking part; and sends the transmission data volume and target address to the write request unpacking part.

[0044] The SRAM array is used for buffering data and is composed of a plurality of single-port SRAMs. Each single-port SRAM can be controlled individually. One single-port SRAM can be controlled to write, while another single-port SRAM can be controlled to write out.

[0045] It should be noted that the SRAM array adopts a multi-body design to reduce read-write conflicts. Each single-port SRAM in the SRAM can be controlled separately, so there will be a situation where one single-port SRAM is writing and the other single-port SRAM is reading. In theory, the more bodies there are, the lower the probability of read-write conflicts. From an implementation perspective, the amount of data that the SRAM array needs to buffer is limited, so it cannot be simply divided into a large number of bodies; from an area perspective, the more the number of split bodies, the larger the area, and the less conducive to implementation; from a performance perspective, split bodies are conducive to improving SRAM frequency, but a large number of bodies will affect layout and routing, making the supporting control logic subject to greater timing pressure. In summary, the design needs to split the number of bodies according to different situations, and cooperate with advance reading to obtain better bandwidth effects.

[0046] In an optional implementation, the request management unit includes: a read request unpacking module, a read request sending module, a read feedback processing module, a write request unpacking module, a pre-fetch control module, a pre-fetch buffer module, and a write packet sending module; the device is also provided with a local buffer control module and an arbitration module, such as Figure 1 shown.

[0047] The local buffer control module is used to control the request management unit to send write data to the SRAM array according to the read request, or to control the request management unit to obtain write data from the SRAM array according to the write request.

[0048] The arbitration module is used to select a corresponding single-port SRAM from the SRAM array to receive write data according to the read request; or to select a corresponding single-port SRAM from the SRAM array to obtain write data according to the write request. The arbitration module is also used to: when the read request and the write request need to read and write the same single-port SRAM, arbitrate the read request and the write request according to a preset request priority, so that the read request and the write request are executed in sequence according to the priority.

[0049] It should be noted that an arbitration module is set up to arbitrate according to a read request and a write request, and write data to the corresponding single-port SRAM in the SRAM array or read data from the corresponding single-port SRAM in the SRAM array according to the arbitration result. Moreover, when the write request and the read request point to the same single-port SRAM in the SRAM array, priority arbitration is performed on the write request and the read request, and the read request or the write request is selected according to the set priority.

[0050] The read request unpacking module is used to generate a read request according to the descriptor information; the read request sending module is used to send the read request to the memory network; the read feedback processing module is used to obtain write data from the memory network and send it to the SRAM array; the write request unpacking module is used to generate a write request according to the data volume of the write data and the buffer space in the pre-fetch buffer module; the data volume of the write data is obtained from the descriptor information; the pre-fetch control module is used to obtain the write data from the corresponding single-port SRAM as pre-fetch data according to the write request, and send it to the pre-fetch buffer module; the pre-fetch buffer module is used to store the pre-fetch data and the corresponding write request; the write packet sending module is used to send the pre-fetch data and the corresponding write request to the memory network.

[0051] In an optional embodiment, the prefetch control module includes several read data buffer request modules; the read data buffer request module is used to receive each write data request in the write request, and arbitrate the status of the read data buffer request module through the arbitration module; and select the corresponding read data buffer request module to process the write data request according to the arbitration result.

[0052] Specifically, if the arbitration result indicates that the current read data buffer request module is in an idle state, the write data corresponding to the current write data request is written into the pre-fetch buffer module, and after the write data is written, the state of the current read data buffer request module is changed to an idle state; if the arbitration result indicates that the current read data buffer request module is in a busy state, the current write data request is sent to the next read data buffer request module for arbitration; if the arbitration result indicates that the current read data buffer request module is in a busy state and the subsequent read data buffer request module of the current read data buffer request module is in a busy state, the current write data request is blocked from being transmitted backward. In addition, if the arbitration result indicates that more than one read data buffer request module is in an idle state, a read data buffer request module with a high priority is selected according to the preset priority of the read data buffer request module to process the write data request.

[0053] In summary, the direct memory access device based on single-port SRAM provided by the embodiment of the present invention includes a request management unit and an SRAM array; the request management unit is used to receive descriptor information and split the corresponding write request or read request therefrom; the descriptor information is forwarded to the request management unit by the descriptor status management module, the read request in the descriptor information includes the amount of data to be transmitted and the source address, and the write request includes the amount of data to be transmitted and the target address; the split read request is sent to the memory network, various bus interfaces are parsed according to various bus interface protocols, write data is obtained from the memory network, and the data is written into the SRAM array, or write data is obtained from the SRAM array through the split write request and the data is sent to the memory network. The SRAM array is used to buffer data and is composed of a plurality of single-port SRAMs, each single port can be read and written separately, and a single-port SRAM can be controlled to write and another single-port SRAM can be controlled to read. When a single-port SRAM receives a write request and a read request at the same time, arbitration is required, and the read request or write request is selected according to the set read and write priority. Since single-port SRAM only processes read requests or write requests at the same time, it consumes less power than dual-port SRAM, and can increase the upper frequency limit of direct memory access. Single-port SRAM does not process read and write requests at the same time, so it has lower read and write interference than dual-port SRAM. In addition, the area of ​​single-port SRAM is smaller than that of dual-port SRAM, which can reduce the area of ​​chip design.

[0054] In order to better illustrate the write request unpacking and pre-fetching control process of the embodiment of the present invention, a specific example will be used for illustration. The structure of the write request unpacking and pre-fetching control is as follows: Figure 2 As shown, two read data buffer request modules are taken as an example, namely, read data buffer request 0 and read data buffer request 1.

[0055] The write request unpacking and pre-fetch control module determines whether to unpack the write request and read the SRAM array request according to the amount of local buffer data in the descriptor status management module. The reading of the SRAM array is managed in a credit manner to avoid occupying the single-port SRAM due to the inability of the subsequent stage to receive, thereby reducing the bus bandwidth. In order to reduce the bandwidth loss caused by the read-write conflict of the single-port SRAM, the reading is designed to be advanced reading. The specific rules are described in detail below. The write data read from the SRAM array will be temporarily stored in the pre-fetch data buffer to be written out, and the unpacked request will be placed in the request buffer to be sent. The write packet sending module will read the request and data in the pre-fetch buffer, organize the two into the bus protocol required by the network, and then send them to the main memory through the network.

[0056] Specifically, Figure 2In the process, the write request splitting module monitors the amount of local buffered data in the descriptor status management. When the amount of local buffered data is greater than or equal to the amount of data required for a write request and the request buffer in the prefetch buffer module is not full, a corresponding write request is split and sent to the request buffer.

[0057] When the write request splitting module splits a write request, it sends the single-port SRAM start address and data length in the SRAM array to be read to the queue in the write data read splitting module to wait for the data to be read.

[0058] The write data read split module will generate a read single port SRAM request, the corresponding single port SRAM address and the address where the data falls into the pre-fetch buffer according to the read single port SRAM start address and data length in the queue, and send this information to the read data buffer request 0. A write request may correspond to several beats of data, and when the write data read split is corresponding, multiple read single port SRAM requests will be split out and enter the read data buffer request 0 in sequence, and then each request will be arbitrated through the data buffer read write arbitration.

[0059] If the read data buffer request 0 fails to win the arbitration in this beat and the read data buffer request 1 is idle, the corresponding request information is passed to the read data buffer request 1, and a new read SRAM request is received from the write data read split module; if the read data buffer request 0 fails to win the arbitration in this beat and the read data buffer request 1 is valid (busy), the request is blocked from being passed backward; if the read data buffer request 0 wins the arbitration in this beat, the information corresponding to the request is written into the prefetch buffer module and it is invalid (idle); if the read data buffer request 1 wins the arbitration in this beat, the information corresponding to the request is written into the prefetch buffer module and it is invalid (idle).

[0060] If there is no write request, read data buffer request 0 and read data buffer request 1 perform arbitration to read data. If there is a write request, and the write request is not blocked due to arbitration failure, the corresponding single-port SRAM is shielded, and all read requests pointing to the single-port SRAM are blocked. The behavior corresponding to the read single-port SRAM request is: if there is a blocked request in read data buffer request 0 / 1, the unblocked read data buffer request performs arbitration to read data; if read data buffer request 0 / 1 is not blocked, it arbitrates to read data.

[0061] It should be noted that the requests in the read data buffer request 0 and the read data buffer request 1 will be combined with the write vector in the local buffer write control unit for judgment, and then the behavior executed on the SRAM array is determined. Specifically, the priority of the read data buffer request 1 and the read data buffer request 0 can be set, for example, the priority of the read data buffer request 1 is set to be greater than the read data buffer request 0, so as to reduce the small amount of bandwidth loss caused by arbitration. In this example, only two read data buffer request modules are taken as an example. The read data buffer request module can be set with more copies, such as 3 or 4, which can be set according to the actual situation without specific constraints. The priority relationship can be set according to the same logic. The data prefetch buffer and the request buffer are both read out in sequence. Specifically, from the perspective of data writing to the prefetch buffer, the data is acquired non-sequentially, so each time the read single port SRAM request is removed, the storage address in the prefetch buffer has been allocated. This design makes the disordered data become sequential again in the prefetch buffer. The data prefetch buffer can be understood as a queue and is also managed in a queue manner, but the write is with an address, and the upstream module needs to set the corresponding credit control and address management logic according to the depth of the data prefetch buffer.

[0062] In summary, the direct memory access device based on single-port SRAM provided in this example has lower power consumption than dual-port SRAM, because single-port SRAM only processes read requests or write requests at the same time, and can increase the upper limit of the frequency of direct memory access, and improve the performance of direct memory access from the frequency perspective. Moreover, single-port SRAM does not process read requests and write requests at the same time, so it has lower read and write interference than dual-port SRAM. In addition, the area of ​​single-port SRAM is smaller than that of dual-port SRAM, and the device of this example reduces the chip area, and has little impact on performance at the same frequency.

[0063] The single-port SRAM-based direct memory access device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0064] An embodiment of the present invention further provides a direct memory access method based on a single-port SRAM, which is applied to the above-mentioned direct memory access device based on a single-port SRAM. The direct memory access method based on a single-port SRAM includes a read request processing flow and a write request processing flow.

[0065] The read request processing flow is as follows Figure 3 As shown, the following steps are included.

[0066] S301, obtaining a read request according to the received descriptor information;

[0067] S302, obtaining write data from the memory network according to the read request;

[0068] S303, writing the write data into the SRAM array.

[0069] Write request processing flow is as follows Figure 4 As shown, the following steps are included.

[0070] S401, obtaining a write request according to the received descriptor information; the write request includes the amount of write data to be obtained;

[0071] S402: when the amount of the write data is less than or equal to the amount of local buffer data stored in the SRAM array, obtain the write data from the SRAM array according to the write request;

[0072] S403: Send the written data to the memory network.

[0073] In an optional embodiment, in step S402, before the step of obtaining write data from the SRAM array according to the write request, it also includes: determining whether the buffer space in the prefetch data buffer is not full, if the buffer space is not full, obtaining the prefetch write data from the SRAM array according to the write request, and storing the prefetch write data in the prefetch data buffer; obtaining the prefetch buffer data from the prefetch data buffer and sending it to the memory network.

[0074] In an optional implementation, the method further includes: if the descriptor information includes a read request and a write request, processing the write request and the read request according to preset priorities.

[0075] The embodiment of the present invention also provides a computer device, see Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0076] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0077] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0078] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0079] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0080] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0081] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0082] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0083] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A direct memory access device based on a single-port SRAM, characterized in that: The device comprises a request management unit and an SRAM array; The request management unit is used to generate a read request to obtain write data from the memory network and send it to the SRAM array, or generate a write request to obtain write data from the SRAM array and send it to the memory network according to the received descriptor information; The SRAM array is used for buffering data and is composed of a plurality of single-port SRAMs.

2. The device according to claim 1, characterized in that The device also includes: The local buffer control module is used to control the request management unit to send write data to the SRAM array according to the read request, or to control the request management unit to obtain write data from the SRAM array according to the write request.

3. The device according to claim 1, characterized in that The device also includes: The arbitration module is used to select a corresponding single-port SRAM from the SRAM array to receive write data according to the read request; or to select a corresponding single-port SRAM from the SRAM array to obtain write data according to the write request.

4. The device according to claim 3, characterized in that The arbitration module is further used for: When the read request and the write request need to read and write the same single-port SRAM, the read request and the write request are arbitrated according to a preset request priority, so that the read request and the write request are executed in sequence according to the priority.

5. The device according to claim 4, characterized in that The request management unit includes a read request unpacking module, a read request sending module, and a read feedback processing module; The read request unpacking module is used to generate a read request according to the descriptor information; The read request sending module is used to send the read request to the memory network; The read feedback processing module is used to obtain write data from the memory network and send the data to the SRAM array.

6. The device according to claim 5, characterized in that The request management unit also includes a write request unpacking module, a pre-fetch control module, a pre-fetch buffer module, and a write packet sending module; The write request unpacking module is used to generate a write request according to the data amount of the written data and the buffer space in the pre-fetch buffer module; the data amount of the written data is obtained from the descriptor information; The pre-fetch control module is used to obtain the write data from the corresponding single-port SRAM as pre-fetch data according to the write request, and send it to the pre-fetch buffer module; The pre-fetch buffer module is used to store the pre-fetch data and the corresponding write request; The write packet sending module is used to send the pre-fetched data and the corresponding write request to the memory network.

7. The device according to claim 6, characterized in that The pre-fetch control module includes a plurality of read data buffer request modules; The read data buffer request module is used to receive each write data request in the write request, and arbitrate the state of the read data buffer request module through the arbitration module; A corresponding read data buffer request module is selected according to the arbitration result to process the write data request.

8. The device according to claim 7, characterized in that The step of selecting a corresponding read data buffer request module to process the write data request according to the arbitration result includes: If the arbitration result indicates that the current read data buffer request module is in an idle state, the write data corresponding to the current write data request is written into the pre-fetch buffer module, and after the write data is written, the state of the current read data buffer request module is changed to an idle state; If the arbitration result indicates that the current read data buffer request module is in a busy state, the current write data request is sent to the next read data buffer request module for arbitration; If the arbitration result indicates that the current read data buffer request module is in a busy state and the subsequent read data buffer request module of the current read data buffer request module is in a busy state, the write-out data request of the current beat is blocked from being transmitted backwards.

9. The device according to claim 8, characterized in that The step of selecting a corresponding read data buffer request module to process the write data request according to the arbitration result further includes: If the arbitration result indicates that more than one read data buffer request module is in an idle state, a read data buffer request module with a higher priority is selected according to the preset priorities of the read data buffer request modules to process the write data request.

10. A direct memory access method based on a single-port SRAM, characterized in that: Applied to the device according to any one of claims 1 to 9, the method comprising: Obtain a read request based on the received descriptor information; Obtaining write data from the memory network according to the read request; The write data is written into the SRAM array.

11. The method according to claim 10, characterized in that The method further comprises: Obtaining a write request according to the received descriptor information; the write request includes the amount of write data to be obtained; When the amount of the write data is less than or equal to the amount of local buffer data stored in the SRAM array, acquiring the write data from the SRAM array according to the write request; The write data is sent to the memory network.

12. The method according to claim 11, characterized in that Before the step of acquiring write data from the SRAM array according to the write request, the method further includes: Determine whether the buffer space in the pre-fetch data buffer is not full, if the buffer space is not full, obtain the pre-fetch write data from the SRAM array according to the write request, and store the pre-fetch write data in the pre-fetch data buffer; The pre-fetch buffer data is obtained from the pre-fetch data buffer and sent to the memory network.

13. The method according to claim 12, characterized in that The method further comprises: If the descriptor information includes a read request and a write request, the write request and the read request are processed according to the preset priorities.

14. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the direct memory access method based on a single-port SRAM according to any one of claims 10 to 13 by executing the computer instructions.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the direct memory access method based on a single-port SRAM according to any one of claims 10 to 13.

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