Data processing method, chip system and computer readable storage medium

Abstract

The invention provides a data processing method, a chip system and a computer readable storage medium. The chip system comprises a plurality of computing nodes and a shared memory of the computing nodes. The data processing method comprises the steps that at least one computing node in the computing nodes stores at least one piece of corresponding data into the shared memory; the plurality of computing nodes determine target storage addresses of operation results corresponding to the plurality of computing nodes according to the data transmission operation and the storage address of the at least one piece of data; and the plurality of computing nodes respectively read the operation results according to the corresponding target storage addresses. According to the method and the device, the shared memory of the plurality of computing nodes in the chip system is used for storing the data, the plurality of computing nodes realize data transmission operation among the plurality of computing nodes by reading the corresponding storage addresses, communication among the computing nodes is not needed, the data handling and communication overhead is reduced, and the computing performance of the chip system is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a method for processing data, a chip system, and a computer-readable storage medium. Background Art

[0002] With the development of high-performance computing, large-scale data processing is usually achieved by distributed parallel computing. Distributed parallel computing means breaking down a large computing task into multiple smaller subtasks, and then assigning these subtasks to different computing units (such as CPU, GPU, TPU, etc.) for parallel execution. Distributed parallel computing usually requires communication between nodes to exchange data and synchronize. Data transmission operations (such as gather, broadcast, and scatter) are introduced in the data exchange and synchronization process.

[0003] In the related art, chip systems (such as graphics processing units (GPUs)) use a multi-level hardware architecture to achieve parallel processing of computing and communication, thereby reducing the latency of the chip system. However, under the multi-level hardware architecture, a complete data transmission communication operation between nodes (such as an all-gather operation) needs to be communicated on the hardware of each level, and the communication on the hardware of each level needs to complete the data transmission through the actual transmission bandwidth, resulting in a large communication overhead. Summary of the invention

[0004] The present application provides a method for processing data and a chip system to reduce the latency and communication overhead of data transmission operations, thereby improving the computing performance of the chip system.

[0005] In a first aspect, a method for processing data is provided, the method being applied to a chip system, the chip system comprising a plurality of computing nodes and a shared memory of the plurality of computing nodes, the method comprising: at least one computing node among the plurality of computing nodes storing at least one corresponding data into the shared memory; the plurality of computing nodes determining target storage addresses of operation results corresponding to the plurality of computing nodes based on a data transmission operation and a storage address of at least one data, wherein the data transmission operation comprises one of an aggregation operation, a broadcast operation and a dispersion operation; and the plurality of computing nodes respectively reading the operation results according to the corresponding target storage addresses.

[0006] As a possible implementation manner, the shared memory includes multiple storage addresses corresponding to the multiple computing nodes one by one, and the multiple storage addresses are continuous in sequence. The method includes: the multiple computing nodes respectively store multiple data in the multiple storage addresses; the first computing node among the multiple computing nodes merges the multiple storage addresses as the target storage address of the aggregation result corresponding to the aggregation operation, and sends the target storage address to other computing nodes; the multiple computing nodes read the aggregation result according to the target storage address.

[0007] As a possible implementation manner, the shared memory includes multiple storage addresses corresponding to the multiple computing nodes one by one, and the multiple computing nodes store a one-to-one correspondence between the multiple computing nodes and the multiple storage addresses. The method includes: according to the correspondence, the multiple computing nodes respectively store multiple data to multiple storage addresses; the multiple computing nodes merge the multiple storage addresses as the target storage address of the aggregation result corresponding to the aggregation operation, and update the corresponding storage addresses to the target storage address; according to the target storage address, the multiple computing nodes respectively read the aggregation result.

[0008] As a possible implementation, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the chip system includes multiple computing units, and the method further includes: the multiple computing units perform aggregation operations according to their respective corresponding aggregation results.

[0009] As a possible implementation, the shared memory of the multiple computing nodes is a first shared memory, the chip system includes a data transmission unit, the multiple computing units are connected through the data transmission unit, and the data transmission unit includes a second shared memory; the method also includes: the multiple computing units store the first aggregation results corresponding to each other in the corresponding storage addresses in the second shared memory; the storage addresses of the first aggregation results corresponding to each of the multiple computing units are merged to determine the target storage address of the second aggregation result; and the second aggregation result is read according to the target storage address of the second aggregation result.

[0010] As a possible implementation method, the method includes: a first computing node among the multiple computing nodes stores corresponding data to a corresponding storage address; the first computing node uses its corresponding storage address as the target storage address of a broadcast result corresponding to the broadcast operation, and sends the target storage address to other computing nodes; and multiple computing nodes read the broadcast result according to the target storage address.

[0011] As a possible implementation manner, the shared memory includes multiple storage addresses corresponding one to one to the multiple computing nodes, and the multiple computing nodes store a one-to-one correspondence between the multiple computing nodes and the multiple storage addresses. The method includes: according to the correspondence, the first computing node among the multiple computing nodes stores the corresponding data to the corresponding storage address; the multiple computing nodes use the storage address corresponding to the first computing node as the target storage address of the broadcast result corresponding to the broadcast operation, and update their respective corresponding storage addresses to the target storage address; according to the target storage address, the multiple computing nodes respectively read the broadcast result.

[0012] As a possible implementation manner, the shared memory includes a storage address of a first computing node among the multiple computing nodes, and the method includes: the first computing node among the multiple computing nodes stores its corresponding data to the corresponding storage address; the first computing node divides its corresponding storage address to obtain target storage addresses of multiple scattered results, the multiple scattered results correspond one-to-one to the multiple computing nodes, and the multiple target storage addresses corresponding to the multiple scattered results are respectively sent to the corresponding computing nodes; the multiple computing nodes respectively read their corresponding scattered results according to the multiple target storage addresses.

[0013] As a possible implementation manner, the shared memory includes multiple target storage addresses corresponding one-to-one to the multiple computing nodes, and the multiple computing nodes store a one-to-one correspondence between the multiple computing nodes and the multiple target storage addresses. The method includes: a first computing node among the multiple computing nodes divides the data to be dispersed to obtain multiple first dispersed results, wherein the multiple first dispersed results correspond one-to-one to the multiple computing nodes; according to the corresponding relationship, the first computing node stores the multiple first dispersed results to the corresponding multiple target storage addresses respectively; and the multiple computing nodes read the corresponding first dispersed results respectively from the corresponding target storage addresses.

[0014] As a possible implementation manner, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, and the chip system includes multiple computing units. The method also includes: a first computing unit of the multiple computing units divides the data to be dispersed to obtain multiple second dispersed results, wherein the multiple second dispersed results correspond one-to-one to the multiple computing units; a first computing node among the multiple computing nodes in each computing unit divides the corresponding second dispersed result to obtain multiple first dispersed results, wherein the multiple first dispersed results correspond one-to-one to the multiple computing nodes in each computing unit.

[0015] As a possible implementation, the shared memory of the multiple computing nodes is a first shared memory, the chip system includes a data transmission unit, the multiple computing units are connected through the data transmission unit, and the data transmission unit includes a second shared memory; the method also includes: the first computing unit among the multiple computing units stores the data to be dispersed in the corresponding storage address in the second shared memory; the storage address of the data to be dispersed is divided to obtain target storage addresses of multiple second dispersed results, and the multiple second dispersed results correspond one-to-one to the multiple computing units respectively; and the second dispersed result is read according to the target storage address of the second dispersed result.

[0016] As a possible implementation, the computing unit is a chip that supports in-memory computing.

[0017] In a second aspect, a chip system is provided, comprising a plurality of computing nodes and a shared memory of the plurality of computing nodes, wherein at least one computing node among the plurality of computing nodes stores at least one corresponding data in the shared memory; the plurality of computing nodes determine target storage addresses of operation results corresponding to the plurality of computing nodes based on a data transmission operation and a storage address of at least one data, wherein the data transmission operation comprises one of an aggregation operation, a broadcast operation and a scatter operation; and the plurality of computing nodes respectively read the operation results according to the corresponding target storage addresses.

[0018] As a possible implementation, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the aggregation operation between the multiple computing nodes is used to determine the aggregation result within the computing unit, and the chip system includes the multiple computing units, which are communicatively connected to perform aggregation operations between the multiple computing units according to the aggregation results corresponding to each of the multiple computing units.

[0019] As a possible implementation method, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the chip system includes multiple computing units, the multiple computing units are communicatively connected, the scatter operation between the multiple computing units is used to determine the first scatter results corresponding to each of the multiple computing units, and each computing unit performs a scatter operation according to the corresponding second scatter result to obtain multiple second scatter results corresponding to multiple computing nodes in each computing unit.

[0020] According to a third aspect, a computer-readable storage medium is provided, on which a program code for executing the method according to the second aspect or any one of the implementations of the second aspect is stored.

[0021] According to a fourth aspect, a computer program product is provided, wherein the computer program product comprises a program code for executing the method as described in the second aspect or any one of the implementations of the second aspect.

[0022] The method for processing data in the embodiment of the present application utilizes the shared memory of multiple computing nodes in the chip system to store data. Multiple computing nodes read corresponding storage addresses to implement data transmission operations between multiple computing nodes. The data transmission operation can be a communication operation that does not involve calculation, such as an aggregation operation, a broadcast operation, or a dispersion operation. There is no need for actual communication between multiple computing nodes, which reduces data handling and communication overhead, thereby improving the computing performance of the chip system.

[0023] Furthermore, since data transmission operations only involve changes in the storage addresses of writes and reads, the corresponding data transmission operators can be integrated into the previous and subsequent calculation operators in the computation graph to further reduce the communication scheduling overhead, reduce the inference latency of the chip system, and increase the throughput of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and other drawings obtained by ordinary technicians in this field based on these drawings fall within the scope of the present application.

[0025] Figure 1 is an example diagram of a hardware structure to which data transfer operations can be applied in the related art.

[0026] Figure 2 This is an example diagram of the structure of a chip system to which the method for processing data provided in an embodiment of the present application is applied.

[0027] Figure 3 It is a schematic flowchart of performing data transmission operations using shared memory provided in an embodiment of the present application.

[0028] Figure 4 This is another schematic flowchart of performing an aggregation operation using shared memory provided in an embodiment of the present application.

[0029] Figure 5a-5c It is a schematic diagram of performing an aggregation operation using shared memory provided in an embodiment of the present application.

[0030] Figure 6 This is another schematic flowchart of performing an aggregation operation using shared memory provided in an embodiment of the present application.

[0031] Figure 7It is a schematic flowchart of performing broadcast operations using shared memory provided in an embodiment of the present application.

[0032] Figure 8 It is a schematic diagram of performing broadcast operations using shared memory provided in an embodiment of the present application.

[0033] Fig. 9 This is another schematic flowchart of performing broadcast operations using shared memory provided in an embodiment of the present application.

[0034] Fig.10 It is a schematic flowchart of performing distributed operations using shared memory provided in an embodiment of the present application.

[0035] Fig.11 It is a schematic diagram of using shared memory to perform distributed operations provided in an embodiment of the present application.

[0036] Fig.12 This is another schematic flowchart of performing distributed operations using shared memory provided in an embodiment of the present application.

[0037] Fig.11 It is a schematic diagram of using shared memory to perform distributed operations provided in an embodiment of the present application.

[0038] Fig.13 is a schematic diagram of a hardware structure to which a global gather operation and a global scatter operation can be applied.

[0039] Fig.14 This is another schematic diagram of performing an aggregation operation using shared memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained based on the embodiments in the present application belong to the scope of protection of the present application.

[0041] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0042] It should be understood that the specific embodiments described below are only used to explain the present application and are not used to limit the present application.

[0043] The embodiments of the present application can be applied to data transmission operations, which are communication operations that do not involve calculation or reduction, such as aggregation operations, broadcast operations, or scatter operations. For ease of understanding, the data transmission operations mentioned in the embodiments of the present application and the hardware architecture involved in the data transmission operations are first introduced.

[0044] The computing process of a chip system (such as a GPU) often involves data aggregation, broadcasting, or dispersion operations. Among them, the aggregation operation can be understood as an operation that combines multiple data into a complete result through a splicing operation. This complete result can be called an aggregation result. The multiple data here can be data corresponding to different computing nodes. In other words, the aggregation operation can be performed between multiple computing nodes.

[0045] The broadcast operation can be understood as an operation that obtains multiple copies of a single data through a replication operation and distributes them to multiple computing nodes. This data copy can be called a broadcast result. The single data here can be the data corresponding to one of the computing nodes. In other words, the broadcast operation can be performed between multiple computing nodes.

[0046] The scatter operation can be understood as an operation that splits a single data into multiple sub-data and sends the multiple sub-data to different computing nodes. This sub-data can be called a scatter result. The single data here can be the data corresponding to one of the computing nodes. In other words, the scatter operation can be performed between multiple computing nodes.

[0047] Combine the following Figure 1 The hardware architecture shown describes how to perform a gather operation, a broadcast operation, or a scatter operation across multiple compute nodes.

[0048] Figure 1 A hardware architecture diagram of a computing node to which data transfer operations can be applied is shown. Figure 1Four computing nodes are shown, namely computing node 0, computing node 1, computing node 2, and computing node 3. It should be understood that the process of data transmission operation is introduced here by taking four computing nodes as an example. In actual applications, data transmission operations can be performed between a larger number or a smaller number of computing nodes. The memory here can be, for example, a dynamic random access memory (DRAM). Each computing node may include a memory for storing data corresponding to the computing node. The computing node may also have a computing function. In some cases, a computing node may be referred to as a cluster. The four computing nodes can communicate through a network-on-chip (NoC). The communication between the four computing nodes can be implemented, for example, based on the universal chiplet interconnect express (UCIE) protocol. Figure 1 The four computing nodes in the figure form a computing unit. The computing unit here can be, for example, a chip that supports compute-in-memory (CIM). In some cases, the chip that supports CIM can exist in the form of a die. A die can be understood as a chip that is cut from a wafer and contains a complete circuit but has not yet been packaged. The computing unit composed of the above computing nodes can belong to a chip system (chip). The chip system here can be, for example, a GPU.

[0049] The data transmission operation can be performed by any one of the different computing nodes. For ease of description, the computing node that performs the data transmission operation among the multiple computing nodes is referred to as the first computing node in the following text. After obtaining the result of the data transmission operation, the first computing node can store the result of the data transmission operation in its own memory. Figure 1The data stored in computing node 0, computing node 1, computing node 2, and computing node 3 are respectively: data 0, data 1, data 2, data 3, and the first computing node is computing node 0. Computing node 0 can obtain the data stored in the other three computing nodes by communicating with the other three computing nodes. When the data transmission operation is an aggregation operation, computing node 0 can perform a splicing operation on the data stored by itself and the data of the other three computing nodes, and obtain the complete data after the splicing of the four data as the aggregation result. When the data transmission operation is a broadcast operation, computing node 0 can copy the data stored by itself, and send the copied data to the other three computing nodes respectively, and store them in the memory corresponding to the other three computing nodes. When the data transmission operation is a distributed operation, computing node 0 can divide the data stored by itself to obtain multiple sub-data, and send the sub-data corresponding to the other three computing nodes to the other three computing nodes respectively, and store them in the memory corresponding to the other three computing nodes.

[0050] From the above description, it can be seen that in order to obtain data from other computing nodes or distribute data to other computing nodes, the first computing node performing the data transmission operation needs to communicate with other computing nodes. When the number of computing nodes involved in the data transmission operation described above is large, it may cause a large communication overhead in the process of the data transmission operation.

[0051] To solve the above technical problems, the embodiments of the present application provide a method for processing data and a chip system. It should be understood that the chip system mentioned in the embodiments of the present application can be an independent chip or a part of a chip. The chip system includes multiple computing nodes and a shared memory of the multiple computing nodes. The method for processing data involved in the embodiments of the present application utilizes the shared memory of multiple computing nodes in the chip system to store data, and multiple computing nodes read the corresponding storage addresses to realize data transmission operations between multiple computing nodes, without the need to communicate between computing nodes, reducing data handling and communication overhead, thereby improving the computing performance of the chip system.

[0052] Combine the following Figure 2 , the chip system 20 applied to the method for processing data provided in an embodiment of the present application is introduced in more detail.

[0053] The chip system 20 may include multiple computing nodes, where the computing nodes may be, for example, the computing cluster mentioned above.

[0054] The embodiment of the present application does not specifically limit the number of computing nodes included in the chip system 20. Figure 24 computing nodes are shown, namely computing node 200, computing node 210, computing node 220 and computing node 230. However, the number of computing nodes included in the chip system 20 in the embodiment of the present application is not limited thereto. The chip system 20 may include a greater number or a lesser number of computing nodes.

[0055] The chip system 20 may also include a shared memory 240 of multiple computing nodes. The shared memory here can be understood as a memory area shared by multiple computing nodes. The embodiment of the present application does not specifically limit the type of shared memory. Multiple computing nodes can directly access the shared memory, so that data can be written and / or read from the shared memory. In other words, multiple data corresponding to multiple computing nodes can be stored in the shared memory. One or more computing nodes in the multiple computing nodes can directly access the shared memory to read the data corresponding to other computing nodes. In this way, a data sharing mechanism is provided, so that one or more computing nodes of the chip system can obtain data of other computing nodes by directly accessing the shared memory without communicating with other computing nodes, thereby reducing the communication overhead caused by one or more computing nodes obtaining data of other computing nodes. In addition, since the speed at which the computing node obtains the corresponding data of other computing nodes by accessing the shared memory is faster than the speed at which the computing node obtains the corresponding data of other computing nodes by communicating with other computing nodes, the use of shared memory can also reduce the delay caused by one or more computing nodes obtaining data of other computing nodes.

[0056] The above-mentioned multiple computing nodes and shared memory may belong to one computing unit. The computing unit here may have a uniform memory access (UMA) architecture. For a computing unit with a UMA architecture, the computing nodes included in the computing unit may share memory. The memory may be regarded as a unified resource pool, and the computing nodes in the computing unit may access the shared memory through the same path, so the latency of any computing node accessing any memory location is the same. The computing unit here may be a chip that supports in-memory computing.

[0057] As mentioned above, the data transmission operation involves a process in which one or more computing nodes obtain data corresponding to other computing nodes, and the above-mentioned shared memory can be used for a certain (or several) computing nodes to obtain data corresponding to other computing nodes. Therefore, the shared memory 240 in the chip system 20 can be used for the above-mentioned multiple computing nodes to perform data transmission operations. The data transmission operation here can, for example, be one of the primary forms of aggregation operations, broadcast operations, and dispersion operations mentioned above. In addition, the data transmission operations of multiple computing nodes can belong to a hierarchical data transmission operation, or a part of a hierarchical global data transmission operation. The data transmission operation here can be performed by any one of the multiple computing nodes. Alternatively, the data transmission operation here can also be performed separately by multiple computing nodes. For ease of description, the node that performs the data transmission operation can be referred to as the first computing node. That is, the first computing node can be any one of the multiple computing nodes in the chip system or at least one computing node. The chip system has the following Figure 2 Taking the structure shown as an example, the first computing node may include any one or at least one of the following: computing node 200 , computing node 210 , computing node 220 , and computing node 230 .

[0058] Combine the following Figure 3 This article describes in detail the process of multiple computing nodes using shared memory to perform data transmission operations. Figure 3 As shown, the process of performing a data transmission operation using a shared memory may include the following steps S310 to S330.

[0059] In step S310, at least one computing node among the plurality of computing nodes stores corresponding at least one data into the shared memory.

[0060] Here, the at least one data may be the data corresponding to the multiple computing nodes mentioned above, or may be the data corresponding to a certain computing node. For example, the shared memory may have storage addresses corresponding to the multiple computing nodes, and the data corresponding to each computing node in the multiple computing nodes may be stored in the storage address corresponding to the computing node.

[0061] In step S320, at least one computing node among the multiple computing nodes determines a target storage address of operation results corresponding to the multiple computing nodes according to a data transmission operation and a storage address of at least one data, wherein the data transmission operation includes one of an aggregation operation, a broadcast operation, and a scatter operation.

[0062] If the data transmission operation is an aggregation operation, the first computing node or the plurality of computing nodes among the plurality of computing nodes merge the storage addresses of the plurality of data as the target storage address of the aggregation result. If the data transmission operation is a broadcast operation, the first computing node or the plurality of computing nodes among the plurality of computing nodes use the storage address of the single data as the target storage address of the broadcast result. If the data transmission operation is a scatter operation, the first computing node among the plurality of computing nodes divides the storage address of the single data into a plurality of target storage addresses corresponding to the plurality of scatter results.

[0063] In step S330, a plurality of computing nodes read the operation result respectively according to the corresponding target storage address.

[0064] Through the above steps S310 to S330, the shared memory of multiple computing nodes in the chip system is used to store data, and the multiple computing nodes read the corresponding storage addresses to realize the data transmission operation between the multiple computing nodes. It can be seen from the above description that in the process of performing the aggregation operation, any computing node among the multiple computing nodes can obtain the data corresponding to the other computing nodes through the shared memory, rather than obtaining the data corresponding to the other computing nodes by communicating with the other computing nodes. In addition, any computing node among the multiple computing nodes directly splices the data corresponding to itself and the data corresponding to the other computing nodes through the shared memory to obtain the aggregation result, without sending the aggregation result to the other computing nodes by communicating with the other computing nodes; in the process of performing the broadcast operation, the first computing node stores the corresponding single data through the shared memory, and any computing node among the multiple computing nodes can directly obtain the data corresponding to the first computing node through the shared memory, rather than obtaining the broadcast result by communicating with the first computing node; in the process of performing the dispersion operation, the first computing node divides the corresponding single data through the shared memory to obtain multiple dispersion results, and any computing node among the multiple computing nodes can directly obtain the corresponding dispersion result through the shared memory, rather than obtaining the corresponding dispersion result by communicating with the first computing node. Therefore, using shared memory for data transmission operations can reduce data handling and communication overhead.

[0065] Optionally, in some embodiments, the shared memory includes a plurality of storage addresses corresponding to the plurality of computing nodes one by one, the plurality of storage addresses are continuous in sequence, and a first computing node among the plurality of computing nodes stores a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses. Figure 4 As shown, the process of performing the aggregation operation using the shared memory may include the following steps S410 to S430.

[0066] In step S410, the plurality of computing nodes respectively store the plurality of data in the corresponding plurality of storage addresses.

[0067] In this embodiment, the multiple data are the data corresponding to the multiple computing nodes mentioned above. The multiple computing nodes store their corresponding data in the corresponding storage addresses. The multiple storage addresses corresponding to the multiple computing nodes in the shared memory are continuous in order. For example, see Figure 5a , the data corresponding to computing nodes 200, computing nodes 210, computing nodes 220, and computing nodes 230 are recorded as d0, d1, d2, and d3 respectively. These 4 copies of data are stored in the shared memory in sequence, and the sizes of these 4 copies of data are the same. The starting address addr_id of each copy of data in the shared memory is determined according to the base address base_addr, the id parameter (program_id, 0≤program_id≤3) corresponding to each computing node, and the size data_size of the data, that is, the starting address addrs_id of each copy of data = base_addr + program_id *data_size. These 4 copies of data are spliced ​​according to the segmentation dimension of the first computing operator before the aggregation operator. For example, the first computing operator divides the computing tasks according to the row dimension and assigns them to multiple computing nodes for calculation, and the aggregation results are spliced ​​according to the row dimension; the first computing operator divides the computing tasks according to the column dimension and assigns them to multiple computing nodes for calculation, and the aggregation results are spliced ​​according to the column dimension.

[0068] In some optional embodiments, the segmentation dimension of the first computing operator can be determined according to the way in which the second computing operator after the aggregation operator reads the aggregation result. For example, if the operation corresponding to the second computing operator is matrix multiplication, and the aggregation result is used as the left matrix of the computing operator, then the second computing operator reads the aggregation result of the four pieces of data in row-major order, then the segmentation dimension of the first computing operator is the row dimension, that is, the four pieces of data should be stored in sequence in row-major order (see Figure 5b ), and then the four pieces of data are concatenated in the row direction to obtain the aggregation result; for example, if the operation corresponding to the second operator is matrix multiplication, and the aggregation result is used as the right matrix of the operator, then the second operator reads the aggregation result of the four pieces of data in column-major order, then the segmentation dimension of the first operator is the column dimension, that is, the four pieces of data should be stored in sequence in column-major order (see Figure 5c ), and then these four pieces of data are concatenated in the column direction to obtain the aggregation result.

[0069] In step S420, a first computing node among the plurality of computing nodes merges the plurality of storage addresses as a target storage address of an aggregation result corresponding to the aggregation operation, and sends the target storage address to other computing nodes.

[0070] In this embodiment, the first computing node combines multiple storage addresses as the target storage address of the aggregation result corresponding to the aggregation operation, and sends the target storage address corresponding to the aggregation result to other computing nodes. Exemplarily, computing node 200 combines the storage addresses of four copies of data into one target storage address, and sends the target storage address to computing nodes 210, computing node 220, and computing node 230, and the target storage address corresponds to the storage location of the aggregation result.

[0071] In step S430, a plurality of computing nodes read the aggregation result according to the target storage address.

[0072] In this embodiment, the aggregation result is data obtained by splicing data corresponding to multiple computing nodes, and multiple computing nodes can read the aggregation result according to the target storage address. Exemplarily, computing nodes 200, computing nodes 210, computing nodes 220, and computing nodes 230 can read the aggregation result according to the target storage address.

[0073] The present application stores data through shared memory between computing nodes and stores the data in a predetermined storage address. Aggregation operations are implemented by adjusting the storage address where the computing node reads data. This process does not involve actual communication, which can reduce data handling and communication overhead.

[0074] Optionally, in some embodiments, the shared memory includes a plurality of storage addresses corresponding to the plurality of computing nodes one by one, the plurality of storage addresses are continuous in sequence, and the plurality of computing nodes each store a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses. Figure 6 As shown, the process of performing the aggregation operation using the shared memory may include the following steps S610 to S630.

[0075] In step S610, according to the corresponding relationship, the plurality of computing nodes respectively store the plurality of data to the corresponding plurality of storage addresses.

[0076] In step S620, the plurality of computing nodes respectively merge the plurality of storage addresses as the target storage address of the aggregation result corresponding to the aggregation operation, and update the storage addresses corresponding to each of them as the target storage address.

[0077] In step S630, a plurality of computing nodes read the aggregation result according to the target storage address.

[0078] Step S610 is the same as step S410 , and step S630 is the same as step S430 , which will not be described again.

[0079] In step S620, each computing node stores a one-to-one correspondence between the multiple computing nodes and the multiple storage addresses, and each computing node merges the multiple storage addresses as the target storage address of the aggregation result corresponding to the aggregation operation, and updates the storage address corresponding to itself to the target storage address, which corresponds to the storage location of the aggregation result, and can reduce the interaction of storage addresses between computing nodes. Exemplarily, computing node 200, computing node 210, computing node 220, and computing node 230 all merge the storage addresses of four copies of data into one target storage address, and update their respective corresponding storage addresses to the target storage address.

[0080] Optionally, in some embodiments, Figure 7 As shown, the process of performing a broadcast operation using a shared memory may include the following steps S710 to S730.

[0081] In step S710, a first computing node among the plurality of computing nodes stores corresponding data to a corresponding storage address; In step S720, the first computing node uses its corresponding storage address as the target storage address of the broadcast result corresponding to the broadcast operation, and sends the target storage address to other computing nodes; In step S730, a plurality of computing nodes read the broadcast result according to the target storage address.

[0082] In this embodiment, the first computing node stores its corresponding data to the corresponding storage address, and uses its corresponding storage address as the target storage address of the broadcast result, and sends the target storage address to other computing nodes to implement the broadcast operation, and multiple computing nodes read the broadcast result according to the target storage address. Figure 8 , computing node 200 stores the corresponding data d0 in the shared memory, and sends the storage address of data d0 as the target storage address of the broadcast result to computing node 210, computing node 220 and computing node 230 to implement the broadcast operation of data d0.

[0083] Optionally, in some embodiments, the shared memory includes a plurality of storage addresses corresponding to the plurality of computing nodes one by one, and the plurality of computing nodes store a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses, such as Fig. 9 As shown, the process of performing a broadcast operation using a shared memory may include the following steps S910 to S930.

[0084] In step S910, according to the corresponding relationship, the first computing node among the plurality of computing nodes stores the corresponding data to the corresponding storage address; In step S920, the plurality of computing nodes use the storage address corresponding to the first computing node as the target storage address of the broadcast result corresponding to the broadcast operation, and update their respective corresponding storage addresses to the target storage address; In step S930, according to the target storage address, the multiple computing nodes read the broadcast result respectively.

[0085] In this embodiment, each computing node stores a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses, the first computing node stores its corresponding data to the corresponding storage address, the other computing nodes use the storage address corresponding to the first computing node as the target storage address of the broadcast result, and update their own storage address to the target storage address to implement the broadcast operation, and the plurality of computing nodes read the broadcast result according to the target storage address. Exemplarily, computing node 200 stores the corresponding data d0 in the shared memory, computing nodes 210, computing nodes 220, and computing nodes 230 use the storage address of data d0 as the target storage address of the broadcast result, and update their own storage address to the target storage address to implement the broadcast operation of data d0.

[0086] Optionally, in some embodiments, the shared memory includes a storage address of a first computing node among the plurality of computing nodes, such as Fig.10 As shown, the process of performing a scatter operation using a shared memory may include the following steps S1010 to S1030.

[0087] In step S1010, a first computing node among the plurality of computing nodes stores its corresponding data to a corresponding storage address; In step S1020, the first computing node divides its corresponding storage address to obtain target storage addresses of multiple scattered results, the multiple scattered results correspond to the multiple computing nodes one by one, and sends the multiple target storage addresses corresponding to the multiple scattered results to the corresponding computing nodes respectively; In step S1030 , the plurality of computing nodes read the corresponding scattered results respectively according to the plurality of target storage addresses.

[0088] In this embodiment, the first computing node stores its corresponding data to the corresponding storage address, and divides its corresponding storage address into multiple target storage addresses of scattered results, each scattered result corresponding to the target storage address corresponds to multiple computing nodes one by one, and sends the multiple target storage addresses to the corresponding computing nodes to implement the scattered operation, and the multiple computing nodes read the corresponding scattered results according to the multiple target storage addresses. For example, see Fig.11, computing node 200 stores the corresponding data d0 into the shared memory, and then divides the storage address corresponding to the data d0 to obtain the target storage addresses of 4 scattered results (d00, d01, d02 and d03); computing node 200 updates the target storage address corresponding to d00, and sends the target storage addresses of d01, d02 and d03 to computing node 210, computing node 220 and computing node 230 to implement the scattered operation on the data d0, and computing node 200, computing node 210, computing node 220 and computing node 230 read the corresponding scattered results (d00, d01, d02 and d03) according to the corresponding target storage addresses respectively.

[0089] Optionally, in some embodiments, the shared memory includes a plurality of target storage addresses corresponding to the plurality of computing nodes one by one, and the plurality of computing nodes store a one-to-one correspondence between the plurality of computing nodes and the plurality of target storage addresses. Fig.12 As shown, the process of performing a scatter operation using a shared memory may include the following steps S1210 to S1230.

[0090] In step S1210, a first computing node among the plurality of computing nodes divides the corresponding data to obtain a plurality of first scattered results, wherein the plurality of first scattered results correspond one-to-one to the plurality of computing nodes; In step S1220, according to the corresponding relationship, the first computing node stores the plurality of first scattered results to the corresponding plurality of target storage addresses respectively; In step S1230 , the plurality of computing nodes read the corresponding first scattered results respectively from the corresponding target storage addresses.

[0091] In this embodiment, the first computing node divides its corresponding data to obtain multiple first scattered results, and stores the multiple first scattered results to the target storage addresses corresponding to the multiple computing nodes to implement the scattered operation, and the multiple computing nodes read the corresponding scattered results according to the multiple target storage addresses. Fig.11 , computing node 200 divides the corresponding data d0 to obtain four scattered results (d00, d01, d02 and d03), and stores the four scattered results to the target storage addresses corresponding to computing node 200, computing node 210, computing node 220 and computing node 230 respectively to realize the scattered operation on data d0, and computing node 200, computing node 210, computing node 220 and computing node 230 respectively read the corresponding scattered results (d00, d01, d02 and d03) according to the corresponding target storage addresses.

[0092] In an optional embodiment, the chip system may include multiple computing nodes and shared memories of the multiple computing nodes. The multiple computing nodes and the shared memories of the multiple computing nodes may belong to one computing unit. In some implementations, the chip system may include multiple such computing units. That is, the chip system may include multiple computing units, each of which includes multiple computing nodes and shared memories of the multiple computing nodes. In this case, the chip system may have Fig.13 The hardware architecture is shown.

[0093] The plurality of computing units may be chips that support in-memory computing. The chip here may be, for example, a bare chip. The embodiment of the present application does not specifically limit the number of computing units included in the chip system. The number of computing nodes included in the plurality of computing units may be different. Alternatively, the number of computing nodes included in the plurality of computing units may also be the same. For example, the chip system includes 8 CIM bare chips, each of which includes 4 computing clusters and 1 shared memory (see Fig.14 ).

[0094] Multiple computing units can be connected by communication. Optionally, in some embodiments, multiple shared memories of multiple computing units are connected by communication. That is to say, multiple shared memories of multiple computing units can communicate so that each computing unit can obtain data stored in the shared memory of other computing units. Optionally, in some embodiments, multiple computing units can be connected by communication through an IO chip. The IO chip here can be understood as a chip specifically responsible for processing input and output functions. The IO chip can include circuits and logic required to implement data input and output. The IO chip can be, for example, an IO die. Optionally, in some embodiments, multiple computing units can communicate based on the UCIE protocol. The UCIE protocol can be understood as a communication protocol for connecting multiple chips in the same package. As a specific example, the chip system includes 8 CIM dies, and the shared memories of the 8 CIM dies can communicate based on the UCIE protocol through the IO die.

[0095] When the chip system includes multiple computing units, the multiple computing units can all perform the above aggregation operation to obtain the aggregation results corresponding to the multiple computing units. After obtaining the aggregation results corresponding to the multiple computing units, the aggregation operation can be performed between the multiple computing units according to the aggregation results corresponding to the multiple computing units.

[0096] When the chip system includes multiple computing units, a first computing unit of the multiple computing units divides the data to be dispersed to obtain multiple second dispersed results, wherein the multiple second dispersed results correspond one-to-one to the multiple computing units. After obtaining the second dispersed results corresponding to each of the multiple computing units, a first computing node of the multiple computing nodes in each computing unit divides the corresponding second dispersed result to obtain multiple first dispersed results, wherein the multiple first dispersed results correspond one-to-one to the multiple computing nodes in each computing unit.

[0097] In some embodiments, multiple computing units may also perform aggregation operations based on a shared memory. For ease of distinction, the shared memory between the multiple computing nodes mentioned above may be referred to as a first shared memory, the storage address corresponding to the computing node in the shared memory may be referred to as a first storage address, the target storage address after the multiple computing nodes perform the aggregation operation may be referred to as a first target storage address, and the aggregation result obtained by the multiple computing nodes performing the aggregation operation may be referred to as a first aggregation result. In addition to the first shared memory, a second shared memory is set in a data transmission unit between the multiple computing units (for example, the IO chip mentioned above, which is used for data transmission between the multiple computing units). Multiple computing units may perform aggregation operations based on the second shared memory. For example, the second shared memory includes multiple second storage addresses corresponding to the multiple computing units, the multiple second storage addresses are continuous in sequence, and the first computing unit stores a one-to-one correspondence between the multiple computing units and the multiple storage addresses; wherein the multiple computing units store the first aggregation results corresponding to each other in the corresponding multiple second storage addresses, the first computing unit merges the multiple second storage addresses in the second shared memory into the second target storage address of the corresponding second aggregation result, and sends the target storage address to other computing units, and the multiple computing units may read the second aggregation result according to the second target storage address. For example, the second shared memory includes multiple second storage addresses corresponding one to one to the multiple computing units, the multiple second storage addresses are continuous in sequence, and the multiple computing units all store a one-to-one correspondence between the multiple computing units and the multiple second storage addresses; according to the correspondence, the first aggregation results corresponding to each of the multiple computing units are stored in the corresponding multiple second storage addresses, the multiple computing units respectively merge the multiple second storage addresses in the second shared memory into the second target storage addresses of the corresponding second aggregation results, and update the corresponding second storage addresses to the second target storage addresses, and the multiple computing units can read the second aggregation results according to the second target storage addresses.

[0098] In some embodiments, multiple computing units may also perform scatter operations based on a shared memory. For ease of distinction, the shared memory between the multiple computing nodes mentioned above may be referred to as a first shared memory, the storage address in the first shared memory corresponding to the computing node one by one may be referred to as a first storage address, the target storage address after the multiple computing nodes perform the scatter operation may be referred to as a first target storage address, and the scatter results obtained by the multiple computing nodes performing the scatter operation may be referred to as a first scatter result. In addition to the first shared memory, a second shared memory may be provided in a data transmission unit between multiple computing units (for example, the IO chip mentioned above, used for data transmission between multiple computing units). Multiple computing units may perform scatter operations based on the second shared memory. For example, the second shared memory includes a plurality of second storage addresses corresponding one to one to the plurality of computing units, the plurality of second storage addresses are continuous in sequence, and the first computing unit stores a one-to-one correspondence between the plurality of computing units and the plurality of storage addresses; the first computing unit among the plurality of computing units stores its corresponding data to the corresponding second storage address, the first computing unit divides its corresponding second storage address to obtain a plurality of second target storage addresses of second scattered results, the plurality of second scattered results correspond one to one to the plurality of computing units, and the plurality of second target storage addresses corresponding to the plurality of second scattered results are respectively sent to the corresponding computing units; the plurality of computing units read the corresponding second scattered results according to the plurality of second target storage addresses; the first computing node in each computing unit stores the corresponding second scattered result to the corresponding plurality of first storage addresses in the first shared memory, the first computing node divides its corresponding first storage address to obtain a plurality of first target storage addresses of corresponding first scattered results, the plurality of first scattered results correspond one to one to the plurality of computing nodes, and the plurality of first target storage addresses corresponding to the plurality of first scattered results are respectively sent to the corresponding computing nodes. The above is combined with Figures 1 to 12 , describes in detail an embodiment of the method for processing data provided by the present application. The product embodiment of the present application is described in detail below. It should be understood that the description of the product embodiment corresponds to the description of the method embodiment for processing data. Therefore, the part not described in detail can refer to the description of the method embodiment for processing data above.

[0099] As described above, the chip system 20 includes multiple computing nodes and a shared memory of the multiple computing nodes, wherein at least one computing node among the multiple computing nodes stores at least one corresponding data in the shared memory; the multiple computing nodes determine the target storage addresses of the operation results corresponding to the multiple computing nodes based on the data transmission operation and the storage address of at least one data, wherein the data transmission operation includes one of an aggregation operation, a broadcast operation and a scatter operation; and the multiple computing nodes read the operation results respectively according to the corresponding target storage addresses.

[0100] Optionally, in some embodiments, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the aggregation operation between the multiple computing nodes is used to determine the aggregation result within the computing unit, and the chip system includes multiple computing units, which are communicatively connected to perform aggregation operations between the multiple computing units according to the aggregation results corresponding to each of the multiple computing units.

[0101] Optionally, in some embodiments, the multiple computing nodes and the shared memory belong to a computing unit in the chip system, the chip system includes multiple computing units, the multiple computing units are communicatively connected, the scattering operation between the multiple computing units is used to determine the first scattering results corresponding to each of the multiple computing units, and each computing unit performs a scattering operation according to the corresponding first scattering result to obtain multiple second scattering results corresponding to multiple computing nodes in each computing unit. In some implementations, the computing unit is a chip that supports in-memory computing.

[0102] The embodiment of the present application further provides a computer-readable storage medium having program codes stored thereon, and the program codes can be used to execute the method for processing data in any of the above embodiments.

[0103] The embodiment of the present application further provides a computer program product, which includes program code for executing the method for processing data in any of the above embodiments.

[0104] It should be understood that in the embodiment of the present application, determining B based on A does not mean determining B only based on A, but B can also be determined based on A and / or other information.

[0105] It should be understood that in the embodiment of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0106] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0107] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0108] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0109] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0110] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0111] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be read by a computer or a data storage device such as a server or data center that contains one or more available media integrated. The available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, digital video disc (DVD)), or semiconductor media (eg, solid state disk (SSD)), etc.

[0112] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for processing data, characterized in that: The method is applied to a chip system, wherein the chip system includes a plurality of computing nodes and a shared memory of the plurality of computing nodes. The method comprises: At least one computing node among the plurality of computing nodes stores corresponding at least one data in the shared memory; The plurality of computing nodes determine target storage addresses of operation results corresponding to the plurality of computing nodes according to a data transmission operation and a storage address of at least one data, wherein the data transmission operation includes one of a gathering operation, a broadcasting operation, and a scattering operation; Multiple computing nodes read the operation results respectively according to the corresponding target storage addresses.

2. The method according to claim 1, characterized in that The shared memory includes a plurality of storage addresses corresponding to the plurality of computing nodes one by one, the plurality of storage addresses are continuous in sequence, and a first computing node among the plurality of computing nodes stores a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses, and the method includes: According to the corresponding relationship, the plurality of computing nodes respectively store the plurality of data to the corresponding plurality of storage addresses; A first computing node among the plurality of computing nodes merges the plurality of storage addresses as a target storage address of an aggregation result corresponding to the aggregation operation, and sends the target storage address to other computing nodes; A plurality of computing nodes read the aggregation result according to the target storage address.

3. The method according to claim 1, characterized in that The shared memory includes a plurality of storage addresses corresponding to the plurality of computing nodes one by one, and the plurality of computing nodes store a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses, The method comprises: According to the corresponding relationship, the plurality of computing nodes respectively store the plurality of data to the plurality of storage addresses; The multiple computing nodes merge the multiple storage addresses as the target storage address of the aggregation result corresponding to the aggregation operation, and update the storage addresses corresponding to each of them as the target storage address; According to the target storage address, the multiple computing nodes read the aggregation result respectively.

4. The method according to any one of claims 1 to 3, characterized in that The multiple computing nodes and the shared memory belong to a computing unit in the chip system, the chip system includes multiple computing units, and the method further includes: The plurality of computing units perform aggregation operations according to their respective corresponding aggregation results.

5. The method according to claim 4, characterized in that The shared memory of the plurality of computing nodes is a first shared memory, the chip system comprises a data transmission unit, the plurality of computing units are connected via the data transmission unit, and the data transmission unit comprises a second shared memory; the method further comprises: The plurality of computing units store the first aggregation results corresponding to the respective ones into corresponding storage addresses in the second shared memory; Merging the storage addresses of the first aggregation results corresponding to the plurality of computing units respectively to determine a target storage address of the second aggregation result; The second aggregate result is read according to the target storage address of the second aggregate result.

6. The method according to claim 1, characterized in that The method comprises: A first computing node among the plurality of computing nodes stores corresponding data to a corresponding storage address; The first computing node uses its corresponding storage address as the target storage address of the broadcast result corresponding to the broadcast operation, and sends the target storage address to other computing nodes; A plurality of computing nodes read the broadcast result according to the target storage address.

7. The method according to claim 1, characterized in that The shared memory includes a plurality of storage addresses corresponding to the plurality of computing nodes one by one, and the plurality of computing nodes store a one-to-one correspondence between the plurality of computing nodes and the plurality of storage addresses, The method comprises: According to the corresponding relationship, a first computing node among the plurality of computing nodes stores corresponding data to a corresponding storage address; The multiple computing nodes use the storage address corresponding to the first computing node as the target storage address of the broadcast result corresponding to the broadcast operation, and update the storage addresses corresponding to each of them to the target storage address; According to the target storage address, the multiple computing nodes read the broadcast result respectively.

8. The method according to claim 1, characterized in that: The shared memory includes a storage address of a first computing node among the plurality of computing nodes, and the method includes: A first computing node among the plurality of computing nodes stores its corresponding data to a corresponding storage address; The first computing node divides its corresponding storage address to obtain target storage addresses of multiple scattered results, the multiple scattered results correspond to the multiple computing nodes one by one, and sends the multiple target storage addresses corresponding to the multiple scattered results to the corresponding computing nodes respectively; The multiple computing nodes read the corresponding scattered results respectively according to the multiple target storage addresses.

9. The method according to claim 1, characterized in that: The shared memory includes a plurality of target storage addresses corresponding to the plurality of computing nodes one by one, and the plurality of computing nodes store a one-to-one correspondence between the plurality of computing nodes and the plurality of target storage addresses, and the method includes: A first computing node among the plurality of computing nodes divides the corresponding data to obtain a plurality of scattered results, wherein the plurality of scattered results correspond one to one to the plurality of computing nodes; According to the corresponding relationship, the first computing node stores the multiple scattered results to the corresponding multiple target storage addresses respectively; The plurality of computing nodes read the corresponding first scattered results respectively from the corresponding target storage addresses.

10. The method according to claim 1, 8 or 9, characterized in that: The multiple computing nodes and the shared memory belong to a computing unit in the chip system, the chip system includes multiple computing units, and the method further includes: A first computing unit of the plurality of computing units divides the data to be dispersed to obtain a plurality of second dispersed results, wherein the plurality of second dispersed results correspond one-to-one to the plurality of computing units; A first computing node among the multiple computing nodes in each computing unit divides the corresponding second distributed result to obtain multiple first distributed results, wherein the multiple first distributed results correspond one-to-one to the multiple computing nodes in each computing unit.

11. The method according to claim 10, characterized in that The shared memory of the plurality of computing nodes is a first shared memory, the chip system comprises a data transmission unit, the plurality of computing units are connected via the data transmission unit, and the data transmission unit comprises a second shared memory; the method further comprises: The first computing unit among the plurality of computing units stores the data to be dispersed in a corresponding storage address in the second shared memory; Splitting the storage address of the data to be dispersed to obtain target storage addresses of a plurality of second dispersed results, wherein the plurality of second dispersed results correspond one-to-one to the plurality of computing units respectively; The second scatter result is read according to a target storage address of the second scatter result.

12. The method according to claim 4 or 10, characterized in that: The computing unit is a chip that supports in-memory computing.

13. A chip system, characterized in that: comprising a plurality of computing nodes and a shared memory of the plurality of computing nodes, Wherein, at least one computing node among the plurality of computing nodes stores corresponding at least one data in the shared memory; The plurality of computing nodes determine target storage addresses of operation results corresponding to the plurality of computing nodes according to a data transmission operation and a storage address of at least one data, wherein the data transmission operation includes one of a gathering operation, a broadcasting operation, and a scattering operation; Multiple computing nodes read the operation results respectively according to the corresponding target storage addresses.

14. The chip system according to claim 13, characterized in that: The multiple computing nodes and the shared memory belong to a computing unit in the chip system, the aggregation operation between the multiple computing nodes is used to determine the aggregation result within the computing unit, and the chip system includes the multiple computing units, which are communicatively connected to perform aggregation operations between the multiple computing units according to the aggregation results corresponding to each of the multiple computing units.

15. The chip system according to claim 13, characterized in that: The multiple computing nodes and the shared memory belong to a computing unit in the chip system. The chip system includes multiple computing units, and the multiple computing units are communicatively connected. The scatter operation between the multiple computing units is used to determine the first scatter results corresponding to each of the multiple computing units. Each computing unit performs a scatter operation according to the corresponding first scatter result to obtain multiple second scatter results corresponding to multiple computing nodes in each computing unit.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes for executing the method according to any one of claims 1 to 12.

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