Processor setting and instruction broadcasting method, processor, equipment and storage medium

Abstract

The embodiment of the invention provides a processor setting and instruction broadcasting method, a processor, equipment and a storage medium. In an embodiment of the present application, a first register for controlling a broadcast domain of a processor core is added in a processor. On the basis of the first register, the first register can be allocated to the virtual instance in the virtual instance creation process; and the broadcast domain of the processor core of the virtual instance and the broadcast domain limited by the target processor core allocated to the virtual instance are set in the first register, so that the broadcast range of the processor core of the virtual instance is reduced. Therefore, when the processor core of the virtual instance broadcasts the operation instruction, the broadcasting range of the operation instruction can be limited in the target processor core to which the virtual instance is allocated, and broadcasting to all processor cores in the processor is not needed, so that the broadcasting range of the operation instruction is reduced; the waiting time of the processor core which broadcasts the operation instruction to receive the response message can be reduced, and the processing speed of the virtual instance can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor setting and instruction broadcasting method, processor, device and storage medium. Background Art

[0002] A multi-core processor is a processor system with higher performance composed of multiple central processing unit (CPU) cores connected through a system bus. The CPU core is the processing core inside the CPU, also known as the physical core of the CPU.

[0003] In some cases, a CPU core needs to broadcast instructions to other CPU cores to perform system-wide operations. Subsequent processing can only be performed after the system-wide operations are completed. For example, a CPU core can invalidate the corresponding TLB entry through the Translation Lookaside Buffer Invalidate (TLBi) instruction. In the above-mentioned multi-core processor system, when a CPU core executes a TLBi instruction using the traditional TLBi instruction broadcast method, the CPU core that broadcasts the TLBi instruction has a long waiting time. However, in a virtualized scenario, the existing instruction broadcast method increases the waiting time for the CPU core that broadcasts the instruction. Summary of the invention

[0004] Multiple aspects of the present application provide a processor setting and instruction broadcasting method, processor, device and storage medium, which are used to reduce the broadcast domain of the processor core of the virtual instance, thereby helping to reduce the waiting time of the processor core of the virtual instance.

[0005] The present application embodiment provides a processor setting method, including:

[0006] During the virtual instance creation process, allocating a target processor core in a processor to the virtual instance;

[0007] Allocating a first register in the processor to the virtual instance; the first register is used to control a broadcast domain of a processor core;

[0008] A broadcast domain of any processor core in the target processor cores is set in the first register, which is a broadcast domain defined by the target processor core, so that any processor core can broadcast operation instructions to other processor cores in the target processor cores.

[0009] The embodiment of the present application also provides an instruction broadcast method, wherein a virtual instance is allocated with multiple target processor cores, and the method comprises:

[0010] In the case where the first processor core among the multiple target processor cores broadcasts the operation instruction, acquiring the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance; the first register is used to control the broadcast domain of the processor core; the broadcast domain of the processor core of the virtual instance is the broadcast domain defined by the multiple target processor cores;

[0011] Broadcasting the operation instruction to a second processor core among the multiple target processor cores corresponding to the broadcast domain; the second processor core is another processor core among the multiple target processor cores except the first processor core;

[0012] When receiving a response message returned by the second processor core to the operation instruction, the first processor core is controlled to execute the next instruction of the operation instruction.

[0013] The embodiment of the present application also provides a cache refresh instruction broadcast method, wherein a virtual instance is allocated with multiple target processor cores, and the method comprises:

[0014] In the case where a first processor core among the multiple target processor cores broadcasts a cache refresh instruction, acquiring a broadcast domain of the processor core of the virtual instance from a first register allocated to the virtual instance; the first register is used to control the broadcast domain of the processor core; the broadcast domain of the processor core of the virtual instance is the broadcast domain defined by the multiple target processor cores;

[0015] Broadcasting the cache refresh instruction to a second processor core corresponding to the broadcast domain of the processor core of the virtual instance; the second processor core is another processor core among the multiple target processor cores except the first processor;

[0016] When receiving a response message returned by the second processor core to the cache flush instruction, the first processor core is controlled to execute the next instruction of the cache flush instruction.

[0017] The embodiment of the present application further provides a processor, comprising: a plurality of processor cores and at least one register; the at least one register comprises a first register; the first register is used to control the broadcast domain of the processor core;

[0018] When deployed in an electronic device, the processor is used to execute the steps in the above-mentioned processor setting method, and / or instruction broadcasting method, and / or cache refresh instruction broadcasting method.

[0019] The embodiment of the present application further provides a computing device, comprising: a memory and a processor; wherein the memory is used to store a computer program; the processor comprises a plurality of processor cores; each processor core comprises at least one register; the at least one register comprises a first register; the first register is used to control a broadcast domain of the processor core;

[0020] The processor is coupled to the memory and is used to execute the steps in the above-mentioned processor setting method, and / or instruction broadcasting method, and / or cache refresh instruction broadcasting method.

[0021] An embodiment of the present application also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the above-mentioned processor setting method, and / or instruction broadcasting method, and / or cache refresh instruction broadcasting method.

[0022] In an embodiment of the present application, a first register for controlling the broadcast domain of the processor core is added to the processor. Based on the first register, the first register can be allocated to the virtual instance during the virtual instance creation process; and the broadcast domain of the processor core of the virtual instance is set in the first register, which is the broadcast domain defined by the target processor core assigned to the virtual instance, thereby reducing the broadcast range of the processor core of the virtual instance. In this way, when the processor core of the virtual instance broadcasts an operation instruction, the broadcast range of the operation instruction can be limited to the target processor core assigned to the virtual instance, without broadcasting to all processor cores in the processor, thereby reducing the broadcast range of the operation instruction, and reducing the waiting time for the processor core that broadcasts the operation instruction to receive the response message, which helps to improve the processing speed of the virtual instance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0024] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a processor setting process provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the process of broadcasting operation instructions for a virtual instance provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of the structure of the bits of the first register provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the structure of the bits of the second register provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of the structure of the bits of the third register provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of the structure of the bits of the first register provided in an embodiment of the present application;

[0031] Figure 8 A flowchart of a processor setting method provided in an embodiment of the present application;

[0032] Fig. 9 A flowchart of the command broadcasting method provided in an embodiment of the present application;

[0033] Fig.10 A schematic diagram of a flow chart of a method for broadcasting a cache refresh instruction provided in an embodiment of the present application;

[0034] Fig.11 A schematic diagram of the structure of a processor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0036] In a virtualization scenario, a virtual instance refers to multiple virtual servers deployed on a host machine using virtual machine technology to provide different services. A virtual instance can be a virtual machine (VM), a container, or a container group (such as a Pod). A virtualized instance can also be called a client (Guest). For example, a host machine can deploy multiple virtual machines.

[0037] The processor may be a multi-core processor, which is composed of multiple processor cores connected through a system bus to form a high-performance processor system. A virtual instance has an independent processor, memory, network, and disk. The processor corresponding to the virtual instance may also be called a virtual processor. The processor cores assigned to the virtual instance are part of the processor cores in the multi-core processor. When the processor core broadcasts the operation instruction, it can meet the use needs by broadcasting the operation instruction to other processor cores inside the virtual instance, without broadcasting to all processor cores in the multi-core processor. However, the current operation instruction broadcasting method requires broadcasting the operation instruction to all other processor cores through the system bus. After all other processor cores have completed executing the operation instruction, the processor core that broadcasts the operation instruction can perform subsequent processing. This undoubtedly increases the waiting time of the processor core in the virtualization scenario. For example, the CPU core can invalidate the corresponding TLB entry through the Translation Lookaside Buffer Invalidate (TLBi) instruction. When a CPU core executes a TLBi instruction, the TLBi instruction will be broadcast to all other CPU cores on the CPU through the bus, and it is necessary to wait for all other CPU cores to send back responses before the TLBi instruction is considered to have been executed and the next instruction will continue to be executed. Therefore, executing a TLBi instruction requires the CPU core that broadcasts the TLBi instruction to wait for a long time.

[0038] In order to solve the above technical problems, in some embodiments of the present application, a first register for controlling the broadcast domain of the processor core is added to the processor. Based on the first register, the first register can be allocated to the virtual instance during the virtual instance creation process; and the broadcast domain of the processor core of the virtual instance is set in the first register, which is the broadcast domain defined by the target processor core assigned to the virtual instance, thereby reducing the broadcast range of the processor core of the virtual instance. In this way, when the processor core of the virtual instance broadcasts an operation instruction, the broadcast range of the operation instruction can be limited to the target processor core assigned to the virtual instance, without broadcasting to all processor cores in the processor, thereby reducing the broadcast range of the operation instruction, and reducing the waiting time for the processor core that broadcasts the operation instruction to receive the response message, which helps to improve the processing speed of the virtual instance.

[0039] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0040] It should be noted that the same reference numerals denote the same objects in the following drawings and embodiments, and therefore, once an object is defined in one drawing or embodiment, it does not need to be further discussed in the subsequent drawings and embodiments.

[0041] Figure 1A schematic diagram of the structure of a computing device provided in an embodiment of the present application. In this embodiment, the computing device can be a single server device, or a cloud server array, etc. Of course, the computing device can also be a terminal device such as a mobile phone, a tablet computer, a personal computer, a wearable device, etc.

[0042] like Figure 1 As shown, the computing device includes: a processor 10. The processor 10 includes: a plurality of processor cores 101. The plurality of processor cores 101 can be connected via a system bus. A plurality refers to two or more. The plurality of processor cores 101 can be located in the same processor die 20. Of course, the plurality of processor cores 101 can also be distributed in a plurality of processor dies 20. Figure 1 The example in which the processor 10 includes multiple (such as 2) processor dies is used for illustration only, but it does not constitute a limitation. Each processor die may include one or more processor cores 101. Among them, the processor die refers to the die before the processor chip is packaged. Each processor die is an independent functional chip. One or more processor die are packaged to become our common processor chip. In some embodiments, the processor die (Die) refers to the small blocks cut from the wafer (Silicon Wafer) during the production process of the processor. Before cutting, each die (Die) needs to undergo various processing to engrave the circuit logic onto the die.

[0043] The processor core 101 is a physical core and is a physical resource of the processor. Each processor core 101 may include: a control unit and an operation unit (not shown in the figure). The control unit is the control center of the processor 10. The control unit can sequentially take out each instruction from the memory according to a pre-written computer program, put it in the instruction register, determine the operation to be performed through instruction decoding, and then send micro-operation control signals to the corresponding components through the operation controller according to the determined timing. The control unit can control the operation of the operation unit through control instructions.

[0044] The operation unit is the core of the processor 10 and can perform arithmetic and logical operations. The operation unit accepts the command of the control unit and performs actions, that is, all operations performed by the operation unit are instructed by the control signal issued by the control unit. The operation unit is the execution component of the instruction.

[0045] In this embodiment, the processor 10 may further include: at least one register 102. The register 102 is where the processor 10 fetches instructions and data when operating. The register 102 is very fast and can be used to temporarily store instructions, data and addresses.

[0046] There are generally multiple registers 102, which may include: general registers, processor state (Processor State, PSTATE) registers and program counter (Program Counter, PC) registers (not shown in the drawings), but are not limited to these.

[0047] The above general registers are general registers used when the basic instruction set processes instructions. In some embodiments, the processor 10 may include 32 general registers. These registers can be used as 32 64-bit registers, or 32 32-bit registers. The PSTATE register indicates the current state of the processor. The PC register is usually used to point to the address of the next instruction of the currently running instruction (i.e., the address of the current instruction to be executed), and is used to control the execution order of instructions in the program.

[0048] In this embodiment, the computing device is deployed with a virtual instance 30. The virtual instance 30 may be a virtual machine VM, a container or a container group (such as a Pod, etc.). The virtual instance is allocated with independent processing resources, memory, network, and disk, etc. The processing resource corresponding to the virtual instance may be a processor core 101. Among them, the processor core 101 allocated to the virtual instance may be located on the same processor die, or may be distributed on multiple processor die, that is, the processor core 101 allocated to the virtual instance crosses the die.

[0049] The processor core 101 to which the virtual instance is allocated is all or part of the processor cores, generally part of the processor cores, in the processor 10. The embodiment of the present application is mainly aimed at the virtualization scenario in which the virtual instance is allocated to part of the processor cores in the processor 10.

[0050] In the embodiment of the present application, in order to optimize the broadcast range of the processor core of the virtual instance, so that when the processor core of the virtual instance broadcasts an operation instruction, the broadcast range of the operation instruction is limited to the processor core inside the virtual instance, a specific register 102a is added to the processor 10. For ease of description, the register 102a is defined as the first register 102a. Among them, the first register 102a is used to control the broadcast domain of the processor core. The broadcast domain of the processor core, which can also be called the broadcast range of the processor core, is used to limit other processor cores that receive the operation instruction broadcast by a certain processor core.

[0051] It should be noted that in the embodiment of the present application, the operation instruction is a system instruction that all processor cores to which the virtual instance is assigned must execute. For example, the operation instruction may be a cache refresh instruction, etc. The cache refresh instruction is used to refresh the cache. Figure 1As shown, the computing device may further include: the cache 103 may be a cache 103a or a translation lookaside buffer (TLB) 103b. The cache 103 may be located inside the processor 10 or between the processor 10 and the memory 50, or the cache 103 may be partially located inside the processor 10 and partially located between the processor 10 and the memory 50.

[0052] The cache 103a is a storage unit for temporarily storing data in the processor, and is used to store data waiting to be processed or data that has been processed. The time taken by the processor 10 to access the cache 103a is shorter than the time taken to access the memory 50. The use of the cache 103a can reduce the number of times the processor 10 accesses the memory 50, thereby improving the data processing speed of the processor 10.

[0053] TLB 103b is used to cache the mapping relationship between virtual memory address (VA) and physical memory address (PA). TLB 103b is a cache of the virtual memory address to physical memory address translation table used by memory management unit (MMU) 104. MMU 104 is a hardware circuit unit responsible for converting virtual memory addresses to physical memory addresses.

[0054] The mapping relationship between the virtual memory address and the physical memory address is stored in the memory. When the MMU 104 converts the virtual memory address to the physical memory address, if the physical memory address corresponding to the virtual memory address is obtained in the TLB 103b, the MMU 104 does not need to access the mapping relationship between the virtual memory address and the physical memory address in the memory, which can improve the address translation rate.

[0055] During the execution of a computer program, data stored in the Cache 103a often needs to be swapped in and out, which results in the Cache 103a often needing to be refreshed. When a processor core corresponding to a virtual instance refreshes the Cache 103a, a cache refresh instruction needs to be broadcast to other processor cores corresponding to the virtual instance to prevent other processor cores from erroneously consuming data stored in the Cache 103a during the Cache refresh period.

[0056] The TLB is not static. In some scenarios, some TLB entries in some TLBs will become invalid. At this time, it is necessary to refresh these invalid TLB entries. Among them, a TLB entry stores a mapping relationship between a physical memory address and a virtual memory address. For example, during memory replacement, the original physical memory address of the TLB cache is assigned to a new virtual memory address, which also causes the original TLB entry in the TLB that records the mapping relationship between the physical memory address and the virtual memory address to become invalid, and it is necessary to refresh the invalid TLB entry. When a processor core corresponding to a virtual instance refreshes TLB103b, it is necessary to broadcast the TLB refresh instruction to other processor cores corresponding to the virtual instance to prevent other processor cores from mistakenly using the TLB entries stored in TLB 103b during the refresh period of TLB 103b. For TLB, the cache refresh instruction is a TLB refresh (TLB Flush) instruction, such as a TLBi instruction. The TLBi instruction is used to invalidate some or all of the TLB entries in the TLB.

[0057] Whether it is the cache or TLB, there will be situations where the cache refresh instruction needs to be broadcast. Since the processor cores and memories between different virtual instances are independent, when a cache refresh occurs in a virtual instance, the processor core of the virtual instance broadcasts the cache refresh instruction, and the broadcast range is limited to the processor cores within the virtual instance to meet the requirement.

[0058] For the virtualized instances, the computing device is also deployed with a virtualization manager 40. The virtualization manager 40 refers to a computer program that manages the virtual instances, which can be implemented as a software function module or a plug-in. The operating system of the virtual instance can communicate with the hardware through the virtualization manager 40. The virtualization manager 40 can virtualize the hardware resources of the host machine and allocate them to different virtual instances, so that the virtual instances include hardware resources such as processors, memory, motherboards, graphics cards, and network cards. The virtual instances of the virtualization manager 40 are implemented in different forms, and the virtualization managers are different.

[0059] For example, in an embodiment where the virtual instance is a container or a container group, an operating system virtualization architecture can be used to divide a single operating system of a host into multiple containers, which are managed using a container manager. Multiple refers to 2 or more. Accordingly, the virtualization manager is implemented as a container manager.

[0060] For another example, in an embodiment where the virtual instance is a virtual machine, the underlying hardware resources are no longer divided, but a virtual machine monitor (VMM) is installed on the host machine's operating system. The virtual layer exists as application-level software and does not involve the operating system kernel. The virtual layer simulates a set of independent hardware devices for each virtual machine, including hardware resources such as processors, memory, motherboards, graphics cards, and network cards, and installs the client operating system on them. Accordingly, the virtualization manager is implemented as a VMM.

[0061] Based on the virtualization process of the virtual instance, it can be known that the virtualization manager 40 implements processor virtualization, obtains a virtual processor, and allocates the virtual processor to different virtual instances. Therefore, in this embodiment, the first register 102a for controlling the broadcast domain of the processor core can be configured for the broadcast domain by the virtualization manager 40. The processor 10 includes one or more first registers 102a. Multiple means 2 or more. Generally, the processor 10 includes multiple first registers 102a. For an embodiment in which the processor 10 includes one or more processor crystal grains 20, each processor crystal grain 20 includes at least one first register 102a, and generally each processor crystal grain 20 includes multiple first registers 102a. For example, in some embodiments, the processor crystal grain 20 may include 8, 16, 32 or more first registers 102a. Figure 1 In the figure, only one first register 102 a is included on each processor die 20 , but this is not a limitation.

[0062] The number of bits of the first register 102a may be determined by the number of processor cores 101 included in the processor die 20. For example, the number of bits of the first register 102a may be greater than or equal to the number of processor cores 101 included in the processor die 20. For example, if the processor die 20 includes 64 processor cores 101, the first register 102a may be a 64-bit register.

[0063] In this embodiment, if Figure 2 As shown in step 1, the virtualization manager 40 may allocate a target processor core to the virtual instance 30 during the creation of the virtual instance 30. Specifically, the virtualization manager 40 may select a target processor core that meets the computing requirements of the virtual instance from the unallocated processor cores in the processor 10 during the creation of the virtual instance; and allocate the target processor core to the virtual instance. The target processor core allocated to the virtual instance may be located on the same processor crystal, or may be located on multiple processor crystals, such as on 2 or more processor crystals. The number of processor crystals where the target processor core is located is less than or equal to the number of processor crystals included in the processor 10.

[0064] Further, if Figure 2 As shown in step 2, the virtualization manager 40 may also allocate the first register 102a to the virtual instance during the virtual instance creation process. Specifically, the virtualization manager 40 may select one of the unallocated first registers 102a in the processor 10 to allocate to the virtual instance during the virtual instance creation process.

[0065] In some embodiments, the target processor core to which the virtual instance is assigned is located on the same processor die. In this case, the virtualization manager 40 can, during the virtual instance creation process, select any unassigned first register on the processor die where the target processor core is located and assign it to the virtual instance.

[0066] In other embodiments, the target processor core to which the virtual instance is allocated is located on multiple processor dies, and the virtualization manager 40 can select a first register from the unallocated first registers on the multiple processor dies where the target processor core is located and allocate it to the virtual instance during the virtual instance creation process. The virtual instance is allocated multiple first registers 102a, and the multiple first registers 102a correspond to the multiple processor dies one by one, that is, a first register 102a is allocated to the virtual instance on each processor dies where the target processor core is located.

[0067] Based on the first register 102a allocated to the virtual instance, such as Figure 2 As shown in step 3, the broadcast domain of any processor core A in the target processor core can be set in the first register 102a allocated to the virtual instance, which is a broadcast domain limited to the target processor core. In this way, the broadcast range of the operation instructions of the processor core of the virtual instance can be limited to the target processor core of the virtual instance.

[0068] Accordingly, if Figure 3 As shown in step 1, based on the pre-set broadcast domain of the processor core of the virtual instance, when any processor core A in the target processor core of the virtual instance broadcasts an operation instruction, the broadcast domain of the processor core of the virtual instance can be obtained from the first register 102a allocated to the virtual instance. The broadcast domain is the broadcast domain limited by the target processor core allocated to the virtual instance. Figure 3 As shown in step 2, the operation instruction broadcast by any processor core A can be broadcast to other processor cores B except any processor core A in the target processor cores corresponding to the broadcast domain of the processor cores of the virtual instance. Figure 3 Any processor core A is the second processor core. Processor core B is the third processor core.

[0069] When other processor cores B receive the operation instruction, they can respond to the operation instruction and return a response message to processor core A. When processor core A receives the response message returned by all other processor cores B in the target processor core, it executes the next instruction of the operation instruction. In the embodiment of the present application, the specific content of the next instruction of the operation instruction is not limited. In some embodiments, the next instruction of the operation instruction is an operation instruction, such as a logical operation instruction or an arithmetic operation instruction; or, the next instruction of the operation instruction is a memory operation instruction, etc.

[0070] In this embodiment, a first register for controlling the broadcast domain of the processor core is added to the processor. Based on the first register, the first register in the processor can be allocated to the virtual instance during the virtual instance creation process; and the broadcast domain of the processor core of the virtual instance is set in the first register, which is the broadcast domain defined by the target processor core allocated to the virtual instance, thereby reducing the broadcast range of the processor core of the virtual instance. In this way, when the processor core of the virtual instance broadcasts an operation instruction, the broadcast range of the operation instruction can be limited to the target processor core allocated to the virtual instance, without broadcasting to all processor cores in the processor, thereby reducing the broadcast range of the operation instruction, and reducing the waiting time for the processor core that broadcasts the operation instruction to receive the response message, which helps to improve the processing speed of the virtual instance.

[0071] In some embodiments, the number of bits of the first register 102a on the processor die 20 is greater than or equal to the number of processor cores 101 on the processor die 20, and each bit of the first register 102a can represent a processor core 101. Figure 4 As shown, the first register 102a is a 64-bit register, and bits 0-63 correspond to a processor core 101 on the processor crystal 20, and the processor crystal 20 may have 64 processor cores. Based on this, the virtualization manager 40 can set the broadcast domain of any processor core A in the target processor core in the form of a bitmap. Specifically, when setting the broadcast domain of any processor core A in the target processor core, the virtualization manager 40 can determine the flag bit (i.e., bit bit) corresponding to the target processor core assigned to the virtual instance in the first register 102a assigned to the virtual instance; and set the flag bit corresponding to the target processor core to a specified identifier. The specified identifier indicates that the processor core corresponding to the flag bit belongs to the broadcast domain of the processor core of the virtual instance.

[0072] In the embodiments of the present application, the specific implementation form of the designated identifier is not limited. In some embodiments, the designated identifier may be a binary value different from the initial value of the first register 102a. For example, the designated identifier may be 1 or 0, etc., which may be specifically determined by the circuit logic related to the first register 102a.

[0073] For the embodiment in which the target processor core assigned to the virtual instance is located in the same processor die, the flag bit corresponding to the target processor core in the first register 102a on the processor die where the target processor core is located and allocated to the virtual instance may be set to a specified identifier.

[0074] For an embodiment in which the target processor core assigned to the virtual instance is located in multiple processor grains, for any processor grain X among the multiple processor grains where the target processor core is located, the broadcast domain of the processor core of the virtual instance can be set in the first register 102a assigned to the virtual instance on processor grain X to the broadcast domain defined by the target processor core on the processor grain X.

[0075] Specifically, in the first register 102a allocated to the virtual instance on the processor crystal X, a flag bit (i.e., a bit) corresponding to the target processor core on the processor crystal X may be determined; and the flag bit corresponding to the target processor core on the processor crystal X may be set to a specified flag. The specified flag indicates that the processor core corresponding to the flag bit belongs to the broadcast domain of the processor core of the virtual instance.

[0076] The first register of the target processor core located on each processor grain among the multiple processor grains can be set for broadcast domain according to the broadcast domain setting method corresponding to the above-mentioned processor grain X, and then the broadcast domain of the processor core of the virtual instance is set to the broadcast domain limited by the target processor core assigned to the virtual instance, that is, the broadcast domain of the processor core of the virtual instance is limited to the inside of the virtual instance.

[0077] The solution for autonomously configuring the broadcast domain of the processor core of the virtual instance provided in the above embodiment may be a function supported by the virtual instance by default. However, in some embodiments, the virtual instance does not support broadcast domain configuration by default, but needs to be pre-configured to support autonomous broadcast domain configuration before the processor setting method provided in the above embodiment can be used to configure the broadcast domain of the processor core of the virtual instance.

[0078] In order to realize the autonomous selection of whether the virtual instance supports broadcast domain configuration, such as Figure 1As shown, a register 102b for controlling whether a virtual instance supports broadcast domain configuration may also be added to the processor 10. For ease of description, the register 102b is defined as a second register 102b. The processor 10 includes one or more second registers 102b. Multiple refers to two or more. Generally, the processor 10 includes multiple second registers 102b. For an embodiment in which the processor 10 includes one or more processor crystal grains 20, each processor crystal grain 20 includes at least one second register 102b, and generally each processor crystal grain 20 includes multiple second registers 102b. For example, in some embodiments, the processor crystal grain 20 may include 8, 16, 32 or more second registers 102b. Among them, the number of bits of the second register 102b may be the same as that of the first register 102a.

[0079] like Figure 5 As shown, the second register 102b may include: a field representing a virtual instance and a field representing whether the virtual instance supports broadcast domain configuration. The field representing the virtual instance can be used to configure the virtual instance identifier, and the second register 102b is bound to the virtual instance, that is, the second register 102b is assigned to the virtual instance represented by the virtual instance identifier. The virtual instance identifier is information that uniquely represents a virtual instance, and can be an identity identifier (Identity, ID) of the virtual instance, such as a virtual machine identifier (VMID). Figure 5 In the figure, the field representing the virtual instance is the vmid field, and the field representing whether the virtual instance supports broadcast domain configuration is the valid field as an example, but it does not constitute a limitation.

[0080] In some embodiments, the second register 102b may further include a mask field, which is used to verify whether the virtual instance of the broadcast operation instruction is the virtual instance corresponding to the virtual instance identifier in the second register 102b when the operation instruction is subsequently broadcast. Of course, the second register 102b may also include some reserved fields, etc.

[0081] Based on the second register 102b, the virtualization manager 40 can further allocate the second register 102b to the virtual instance during the virtual instance creation process. Specifically, the virtualization manager 40 can select a first register from the unallocated second registers 102b of the processor 10 and allocate it to the virtual instance during the virtual instance creation process.

[0082] Further, the virtualization manager 40 may set the field representing the virtual instance in the second register 102b assigned to the virtual instance to the identifier of the virtual instance so as to bind the second register 102b to the virtual instance; and set the field in the second register 102b assigned to the virtual instance for representing whether the virtual instance supports broadcast domain configuration to the identifier corresponding to the virtual instance supporting broadcast domain configuration so that the virtual instance supports broadcast domain configuration.

[0083] In some embodiments, the field used to indicate whether the virtual instance supports broadcast domain configuration may be one or more bits. In the initial stage, the field is generally set to other default characters except for the identifier corresponding to the virtual instance supporting broadcast domain configuration. Figure 5 In the figure, only the field (such as the valid field) used to characterize whether the virtual instance supports the broadcast domain configuration is 1 bit as an example. In the embodiment of the present application, the specific implementation form of the identifier corresponding to the virtual instance supporting the broadcast domain configuration is not limited. In some embodiments, the identifier corresponding to the virtual instance supporting the broadcast domain configuration may be a binary value different from the initial value of the field. For example, if the initial default value of the field used to characterize whether the virtual instance supports the broadcast domain configuration is 0, the identifier corresponding to the virtual instance supporting the broadcast domain configuration may be 1; if the initial default value of the field used to characterize whether the virtual instance supports the broadcast domain configuration is 1, the identifier corresponding to the virtual instance supporting the broadcast domain configuration may be 0, etc.

[0084] Accordingly, based on the above second register 102b, when any processor core A of the virtual instance broadcasts an operation instruction, the field representing the virtual instance in the second register 102b can be queried; and the second register 102b assigned to the virtual instance can be determined according to the virtual instance identifier stored in the field representing the virtual instance. Further, the field in the second register assigned to the virtual instance used to represent whether the virtual instance supports the broadcast domain configuration can be queried; and when the field used to represent whether the virtual instance supports the broadcast domain configuration is set to the identifier corresponding to the virtual instance supporting the broadcast domain configuration, the above operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register assigned to the virtual instance is performed.

[0085] In some embodiments, the target processor core to which the virtual instance is assigned is located on the same processor die. In this case, the virtualization manager 40 can, during the virtual instance creation process, select any unassigned second register on the processor die where the target processor core is located and assign it to the virtual instance.

[0086] Accordingly, when any processor core A of a virtual instance broadcasts an operation instruction, the field representing the virtual instance of each second register 102b on the processor crystal grain where the target processor core is located can be queried; and according to the virtual instance identifier stored in the field representing the virtual instance, the second register 102b allocated to the virtual instance can be determined from the processor crystal grain where the target processor core is located. Further, the field used to represent whether the virtual instance supports the broadcast domain configuration in the second register allocated to the virtual instance can be queried; and when the field used to represent whether the virtual instance supports the broadcast domain configuration is set to the identifier corresponding to the virtual instance supporting the broadcast domain configuration, the above operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance is performed.

[0087] In other embodiments, the target processor core to which the virtual instance is allocated is located on multiple processor dies, and the virtualization manager 40 can select one second register from the unallocated second registers on the multiple processor dies where the target processor core is located and allocate it to the virtual instance during the virtual instance creation process. The virtual instance is allocated multiple second registers 102b, and the multiple second registers 102b correspond to the multiple processor dies one by one, that is, a second register 102b is allocated to the virtual instance on each processor dies where the target processor core is located.

[0088] Accordingly, when any processor core A of a virtual instance broadcasts an operation instruction, the field representing the virtual instance of each second register 102b on the multiple processor grains where the target processor core is located can be queried; and according to the virtual instance identifier stored in the field representing the virtual instance, the second register 102b allocated to the virtual instance can be determined from the multiple processor grains where the target processor core is located. Further, the field used to represent whether the virtual instance supports the broadcast domain configuration in the second registers allocated to the virtual instance on the multiple processor grains can be queried; and when the fields used to represent whether the virtual instance supports the broadcast domain configuration in the second registers allocated to the virtual instance on the multiple processor grains are all set to the identifier corresponding to the virtual instance supporting the broadcast domain configuration, the above operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance is performed.

[0089] The solution for autonomously configuring the broadcast domain of the processor core of the virtual instance provided in the above embodiment may be a function supported by the computing device by default. However, in some embodiments, the computing device does not support broadcast domain configuration by default, but needs to be pre-configured to support autonomous broadcast domain configuration before the processor setting method provided in the above embodiment can be used to configure the broadcast domain of the processor core of the virtual instance.

[0090] In order to realize the autonomous selection of whether computing devices support broadcast domain configuration, such as Figure 1As shown, a register 102c for controlling whether the computing device supports broadcast domain configuration may be added to the processor 10. For ease of description, the register 102c is defined as a third register 102c. The third register 102c may be one or more. Multiple means two or more. Generally, the third register 102c is one and may be set on any processor die or in other circuit structures outside the processor die. The number of bits of the third register 102c may be the same as that of the first register 102a and the second register 102c.

[0091] like Figure 6 As shown, the third register 102c may include: a field for indicating whether the host machine (ie, computing device) supports broadcast domain configuration. The field may occupy one or more bits. Figure 6 Of course, the third register 102c may also include other fields, such as reserved fields and other functional fields.

[0092] Based on the third register 102c, the virtualization manager 40 may also set the field in the third register 102c used to characterize whether the host machine supports broadcast domain configuration to an identifier corresponding to the host machine supporting broadcast domain configuration before allocating the first register and the second register to the virtual instance, so that the host machine supports broadcast domain configuration.

[0093] In the embodiments of the present application, the specific implementation form of the identifier corresponding to the host machine supporting the broadcast domain configuration is not limited. In some embodiments, the identifier corresponding to the host machine supporting the broadcast domain configuration may be a binary value different from the initial default value of the field. For example, if the initial default value of the field representing whether the host machine supports the broadcast domain configuration is 0, then the identifier corresponding to the host machine supporting the broadcast domain configuration may be 1; if the initial default value of the field representing whether the host machine supports the broadcast domain configuration is 1, then the identifier corresponding to the host machine supporting the broadcast domain configuration may be 0, etc.

[0094] Accordingly, when any processor core A of the virtual instance broadcasts an operation instruction, the field in the third register 102c used to characterize whether the host machine supports the broadcast domain configuration can be queried; when the field used to characterize whether the host machine supports the broadcast domain configuration is set to the identifier corresponding to the host machine supporting the broadcast domain configuration, the above-mentioned operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register assigned to the virtual instance is performed.

[0095] In an embodiment in which a second register 102b for controlling whether a virtual instance supports broadcast domain configuration is provided in the processor 10, when the field for characterizing whether the host machine supports broadcast domain configuration is set to an identifier corresponding to the host machine supporting broadcast domain configuration, the above-mentioned operation of determining the second register assigned to the virtual instance and subsequent operations based on the virtual instance identifier recorded in the field characterizing the virtual instance in the second register can be performed, such as: querying the field in the second register assigned to the virtual instance for characterizing whether the virtual instance supports broadcast domain configuration; when the field for characterizing whether the virtual instance supports broadcast domain configuration is set to an identifier corresponding to the virtual instance supporting broadcast domain configuration, obtaining the broadcast domain of the processor core of the virtual instance from the first register assigned to the virtual instance; and broadcasting the operation instruction to other processor cores B in the broadcast domain of the processor core of the virtual instance except any one of the above-mentioned processor cores A.

[0096] In some embodiments, the target processor cores assigned to the virtual instance are located on the same processor die, and any processor core A among the target processor cores assigned to the virtual instance can broadcast operation instructions to other processor cores B belonging to the virtual instance on the processor die.

[0097] In other embodiments, the target processor cores to which the virtual instances are assigned are located on multiple processor grains. Multiple processor grains 20 are independent of each other, and channels between multiple processor grains 20 need to be set to achieve broadcasting between multiple processor grains 20. Accordingly, the processor 10 may also include a register 102d for controlling the channel range between multiple processor grains. For ease of description, the register 102d may be defined as a fourth register 102d. The fourth register 102d may be one or more. Multiple means two or more. Generally, the processor 10 includes multiple fourth registers 102d. For embodiments in which the processor 10 includes one or more processor grains 20, each fourth register 102d includes at least one fourth register 102d, and generally each processor grain 20 includes multiple fourth registers 102d. For example, in some embodiments, the processor grain 20 may include 8, 16, 32 or more fourth registers 102d. Optionally, the number of fourth registers 102d, first registers 102a and second registers 102c on each processor die 20 is the same. For example, each processor die 20 may include: 16 first registers 102a, 16 second registers 102c and 16 fourth registers 102d.

[0098] In this embodiment, the number of bits of the fourth register 102 d may be the same as that of the first register 102 a , for example, both are 64-bit registers.

[0099] The virtualization manager 40 may also allocate a fourth register 102d to the virtual instance during the virtual instance creation process. Specifically, since the target processor core to which the virtual instance is allocated is located on multiple processor crystals, the virtualization manager 40 may select a fourth register from the unallocated fourth registers on the multiple processor crystals where the target processor core is located and allocate it to the virtual instance during the virtual instance creation process. The virtual instance is allocated multiple fourth registers 102d, and the multiple fourth registers 102d correspond to the multiple processor crystals one by one, that is, a fourth register 102d is allocated to the virtual instance on each processor crystal where the target processor core is located.

[0100] The virtualization manager 40 may respectively configure the channel ranges between the plurality of processor dies 20 in the plurality of fourth registers 102d allocated to the virtual instance, so that any processor core A of the virtual instance can broadcast the operation instruction to the target processor cores on other processor dies based on the channel ranges between the plurality of processor dies. The other processor dies refer to the processor dies other than the target processor dies where the processor core A is located among the plurality of processor dies where the target processor core allocated to the virtual instance is located.

[0101] In some embodiments, the number of bits of the fourth register 102d on the processor die 20 is greater than or equal to the number of channels of the processor die 20, and each bit of the fourth register 102d can represent a channel. Figure 7 As shown, the fourth register 102d is a 64-bit register, and the processor die 20 has 8 channels in total, so bits 0-7 can each correspond to a channel.

[0102] Accordingly, the virtualization manager 40 may set the channel range between the multiple processor dies 20 where the target processor core assigned to the virtual instance is located in the form of a bitmap. Specifically, the virtualization manager 40 may set the flag bit corresponding to the target channel between the multiple processor dies 20 to another designated flag (such as 1 or 0, etc.) in the fourth register 102d assigned to the virtual instance. The designated flag indicates that the target channel corresponding to the flag bit belongs to the channel range of the multiple processor dies 20. The target channel may be one or more, and the specific number may be flexibly set according to actual needs. In order to reduce the broadcast range, the fewer the number of target channels, the better. Therefore, the target channel may be one. The designated flag is generally other characters different from the initial default value of the corresponding flag bit. For example, the designated flag may be a binary value different from the initial default value of the corresponding flag bit. For example, if the initial default value of the flag bit corresponding to the target channel is 0, the designated flag may be 1; if the initial default value of the flag bit corresponding to the target channel is 1, the designated flag may be 0, etc.

[0103] Based on the set channel range between multiple processor crystals 20, for any processor core A assigned to the virtual instance, the operation instruction can be broadcast to other processor cores B assigned to the virtual instance on the target processor crystal; and the channel range between the target processor crystal and other processor crystals is obtained from the fourth register 102d assigned to the virtual instance on the target processor crystal; other processor crystals are other processor crystals except the target processor crystal among the multiple processor crystals where the target processor core assigned to the virtual instance is located. Further, the operation instruction can be broadcast to the processor core B assigned to the virtual instance on other processor crystals through the channel corresponding to the channel range between the target processor crystal and other processor crystals, so as to realize the cross-crystal broadcast of the operation instruction.

[0104] It is worth noting that the computing device provided in the embodiment of the present application includes the above Figure 1 In addition to the components shown, other storage media other than memory and cache may also be included. Memory, cache and other storage media may be collectively referred to as memory. The memory may store computer programs, including but not limited to: computer programs related to the broadcast domain device method executed by the above-mentioned virtualization manager and / or the instruction broadcast method executed by the processor core, etc. Of course, computer programs of the virtualization manager may also be included. In this embodiment, the above-mentioned processor 10 is coupled to the memory, and the computer program stored in the memory may be executed to execute the broadcast domain device method and / or the instruction broadcast method executed by the processor core provided in the following embodiments.

[0105] Of course, the computing device may also include: communication components, power components, display components, audio components and other components (not shown in the drawings). Figure 1 The components are shown schematically only and do not necessarily include Figure 1 The components shown do not necessarily mean that the computing device can only include Figure 1 Components shown.

[0106] In addition to the above-mentioned computing device, the embodiments of the present application also provide a processor setting method and an operation instruction broadcasting method. The processor setting method and the operation instruction broadcasting method provided in the embodiments of the present application are exemplarily described below.

[0107] Figure 8 Schematic diagram of the process flow of the processor setting method provided in the embodiment of the present application. Figure 8 As shown, the processor setting method mainly includes:

[0108] 801. During the virtual instance creation process, a target processor core in a processor is allocated to the virtual instance.

[0109] 802. Allocate a first register in a processor for the virtual instance; the first register is used to control a broadcast domain of the processor core.

[0110] 803. A broadcast domain of any processor core in the target processor cores is set in a first register, which is a broadcast domain defined by the target processor core, so that any processor core can broadcast an operation instruction to other processor cores in the target processor cores.

[0111] In order to optimize the broadcast range of the processor core of the virtual instance, so that when the processor core of the virtual instance broadcasts an operation instruction, the broadcast range of the operation instruction is limited to the processor core inside the virtual instance, a first register is added to the processor. The first register is used to control the broadcast domain of the processor core. The broadcast domain of the processor core, which can also be called the broadcast range of the processor core, is used to limit other processor cores that receive the operation instruction broadcast by a certain processor core.

[0112] It should be noted that in the embodiment of the present application, the operation instruction is a system instruction that all processor cores to which the virtual instance is assigned must perform. For example, the operation instruction may be a cache refresh instruction, etc. The cache refresh instruction is used to refresh the cache. For TLB, the cache refresh instruction is a TLB refresh instruction, such as a TLBi instruction. The TLBi instruction is used to invalidate some or all TLB entries in the TLB.

[0113] In this embodiment, as shown in step 801, a target processor core in a processor may be allocated to a virtual instance during the virtual instance creation process. The processor may be a processor of a host machine where the virtual instance is located. Specifically, during the virtual instance creation process, a target processor core that meets the computing requirements of the virtual instance may be selected from unallocated processor cores in the processor; and the target processor core may be allocated to the virtual instance. The target processor core allocated to the virtual instance may be located on the same processor crystal grain, or may be located on multiple processor crystal grains, such as on 2 or more processor crystal grains. The number of processor crystal grains where the target processor core is located is less than or equal to the number of processor crystal grains included in the processor.

[0114] Furthermore, in step 802, a first register may be allocated to the virtual instance during the virtual instance creation process. Specifically, during the virtual instance creation process, one first register may be selected from unallocated first registers in the processor and allocated to the virtual instance.

[0115] In some embodiments, the target processor core to which the virtual instance is allocated is located on the same processor die. In this case, during the virtual instance creation process, one first register can be selected from unallocated first registers on the processor die where the target processor core is located and allocated to the virtual instance.

[0116] In other embodiments, the target processor core to which the virtual instance is allocated is located on multiple processor dies, and during the virtual instance creation process, one first register can be selected from the unallocated first registers on the multiple processor dies where the target processor core is located and allocated to the virtual instance. The virtual instance is allocated multiple first registers, and the multiple first registers 102a correspond one-to-one to the multiple processor dies, that is, one first register can be allocated to the virtual instance on each processor dies where the target processor core is located.

[0117] Based on the first register allocated to the virtual instance, in step 803, the broadcast domain of any processor core A in the target processor core can be set in the first register allocated to the virtual instance, which is a broadcast domain limited to the target processor core. In this way, the broadcast range of the operation instructions of the processor core of the virtual instance can be limited to the target processor core of the virtual instance.

[0118] Accordingly, the embodiment of the present application also provides an operation instruction broadcasting method. Fig. 9 As shown, the operation instruction broadcast method mainly includes:

[0119] 901. When a first processor core among multiple target processor cores broadcasts an operation instruction, a broadcast domain of the processor core of the virtual instance is obtained from a first register allocated to the virtual instance; the first register is used to control the broadcast domain of the processor core; the broadcast domain of the processor core of the virtual instance is a broadcast domain defined by multiple target processor cores.

[0120] 902. Broadcast the operation instruction to a second processor core among the multiple target processor cores corresponding to the broadcast domain; the second processor core is other processor cores among the multiple target processor cores except the first processor core.

[0121] 903. When receiving a response message returned by the second processor core in response to the operation instruction, control the first processor core to execute the next instruction of the operation instruction.

[0122] Based on the pre-set broadcast domain of the processor core of the virtual instance, when any processor core A (defined as the first processor core) in the target processor core of the virtual instance broadcasts an operation instruction, in step 901, the broadcast domain of the processor core of the virtual instance can be obtained from the first register allocated to the virtual instance. The broadcast domain is a broadcast domain limited by the target processor core allocated to the virtual instance. Further, in step 902, the operation instruction broadcasted by the first processor core A can be broadcasted to the second processor core B in the target processor core corresponding to the broadcast domain of the processor core of the virtual instance, except the first processor core A.

[0123] When the second processor core B receives the operation instruction, it can respond to the operation instruction and return a response message to the first processor core A. Accordingly, in step 903, when the first processor core A receives the response messages returned by all the second processor cores B in the target processor core, the first processor core A can be controlled to execute the next instruction of the operation instruction. In the embodiment of the present application, the specific content of the next instruction of the operation instruction is not limited. In some embodiments, the next instruction of the operation instruction is an operation instruction, such as a logic operation instruction or an arithmetic operation instruction; or, the next instruction of the operation instruction is a memory operation instruction, etc.

[0124] In this embodiment, a first register for controlling the broadcast domain of the processor core is added to the processor. Based on the first register, the first register can be allocated to the virtual instance during the virtual instance creation process; and the broadcast domain of the processor core of the virtual instance is set in the first register, which is the broadcast domain defined by the target processor core assigned to the virtual instance, thereby reducing the broadcast range of the processor core of the virtual instance. In this way, when the processor core of the virtual instance broadcasts an operation instruction, the broadcast range of the operation instruction can be limited to the target processor core assigned to the virtual instance, without broadcasting to all processor cores in the processor, thereby reducing the broadcast range of the operation instruction, and reducing the waiting time for the processor core that broadcasts the operation instruction to receive the response message, which helps to improve the processing speed of the virtual instance.

[0125] In some embodiments, the number of bits of the first register on the processor die is greater than or equal to the number of processor cores on the processor die, and each bit of the first register can represent a processor core. Based on this, the broadcast domain of any processor core A in the target processor core can be set in the form of a bitmap. Specifically, the above step 803 can be implemented as follows: in the first register allocated to the virtual instance, determine the flag bit (i.e., the bit bit) corresponding to the target processor core allocated to the virtual instance; and set the flag bit corresponding to the target processor core to a specified identifier. Among them, the specified identifier indicates that the processor core corresponding to the flag bit belongs to the broadcast domain of the processor core of the virtual instance.

[0126] For the embodiment in which the target processor core assigned to the virtual instance is located in the same processor die, the flag bit corresponding to the target processor core in the first register on the processor die where the target processor core is located and allocated to the virtual instance may be set to a specified identifier.

[0127] For an embodiment in which the target processor core assigned to the virtual instance is located in multiple processor grains, for any processor grain X among the multiple processor grains where the target processor core is located, the broadcast domain of the processor core of the virtual instance can be set in the first register assigned to the virtual instance on processor grain X to the broadcast domain defined by the target processor core on the processor grain X.

[0128] Specifically, in the first register allocated to the virtual instance on the processor crystal X, a flag bit (i.e., a bit) corresponding to the target processor core on the processor crystal X may be determined; and the flag bit corresponding to the target processor core on the processor crystal X may be set to a specified flag. The specified flag indicates that the processor core corresponding to the flag bit belongs to the broadcast domain of the processor core of the virtual instance.

[0129] The first register of the target processor core located on each processor grain among the multiple processor grains can be set for broadcast domain according to the broadcast domain setting method corresponding to the above-mentioned processor grain X, and then the broadcast domain of the processor core of the virtual instance is set to the broadcast domain limited by the target processor core assigned to the virtual instance, that is, the broadcast domain of the processor core of the virtual instance is limited to the inside of the virtual instance.

[0130] The solution for autonomously configuring the broadcast domain of the processor core of the virtual instance provided in the above embodiment may be a function supported by the virtual instance by default. However, in some embodiments, the virtual instance does not support broadcast domain configuration by default, but needs to be pre-configured to support autonomous broadcast domain configuration before the processor setting method provided in the above embodiment can be used to configure the broadcast domain of the processor core of the virtual instance.

[0131] In order to realize the autonomous selection of whether the virtual instance supports the broadcast domain configuration, a register for controlling whether the virtual instance supports the broadcast domain configuration can also be added to the processor, which is defined as the second register. The description of the number and deployment location of the second register can refer to the relevant content of the above embodiment, which will not be repeated here.

[0132] The second register may include: a field representing the virtual instance and a field representing whether the virtual instance supports broadcast domain configuration. The field representing the virtual instance can be used to configure the virtual instance identifier, and the second register is bound to the virtual instance, that is, the second register is assigned to the virtual instance represented by the virtual instance identifier.

[0133] Based on the second register, the second register can also be allocated to the virtual instance during the virtual instance creation process. Specifically, the virtualization manager can select one of the first registers from the unallocated second registers of the processor and allocate it to the virtual instance during the virtual instance creation process.

[0134] Furthermore, the field representing the virtual instance in the second register assigned to the virtual instance can be set to the identifier of the virtual instance to bind the second register to the virtual instance; and the field in the second register 102b assigned to the virtual instance that represents whether the virtual instance supports broadcast domain configuration can be set to the identifier corresponding to the virtual instance supporting broadcast domain configuration, so that the virtual instance supports broadcast domain configuration.

[0135] In some embodiments, the field used to characterize whether the virtual instance supports broadcast domain configuration may be one or more bits. In the embodiments of the present application, the specific implementation form of the identifier corresponding to the virtual instance supporting broadcast domain configuration is not limited. In some embodiments, the identifier corresponding to the virtual instance supporting broadcast domain configuration may be a binary value different from the initial default value of the field. For example, the identifier corresponding to the virtual instance supporting broadcast domain configuration may be 1 or 0, etc.

[0136] Accordingly, based on the above second register, when the first processor core A of the virtual instance broadcasts an operation instruction, the field representing the virtual instance in the second register can be queried; and the second register assigned to the virtual instance can be determined according to the virtual instance identifier stored in the field representing the virtual instance. Further, the field in the second register assigned to the virtual instance used to represent whether the virtual instance supports the broadcast domain configuration can be queried; and when the field used to represent whether the virtual instance supports the broadcast domain configuration is set to the identifier corresponding to the virtual instance supporting the broadcast domain configuration, the above operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register assigned to the virtual instance is performed.

[0137] In some embodiments, the target processor core to which the virtual instance is assigned is located on the same processor die. The virtualization manager may, during the virtual instance creation process, select any unassigned second register on the processor die where the target processor core is located and assign it to the virtual instance.

[0138] Accordingly, when the first processor core A of the virtual instance broadcasts an operation instruction, the field representing the virtual instance of each second register on the processor crystal where the target processor core is located can be queried; and according to the virtual instance identifier stored in the field representing the virtual instance, the second register allocated to the virtual instance can be determined from the processor crystal where the target processor core is located. Further, the field used to represent whether the virtual instance supports the broadcast domain configuration in the second register allocated to the virtual instance can be queried; and when the field used to represent whether the virtual instance supports the broadcast domain configuration is set to the identifier corresponding to the virtual instance supporting the broadcast domain configuration, the above operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance is performed.

[0139] In other embodiments, the target processor core to which the virtual instance is allocated is located on multiple processor dies, and then during the virtual instance creation process, one second register can be selected from the unallocated second registers on the multiple processor dies where the target processor core is located and allocated to the virtual instance. The virtual instance is allocated multiple second registers, and the multiple second registers correspond one-to-one to the multiple processor dies, that is, one second register can be allocated to the virtual instance on each processor dies where the target processor core is located.

[0140] Accordingly, in the case where the first processor core A of the virtual instance broadcasts an operation instruction, the field representing the virtual instance of each second register on the multiple processor grains where the target processor core is located can be queried; and according to the virtual instance identifier stored in the field representing the virtual instance, the second register allocated to the virtual instance can be determined from each of the multiple processor grains where the target processor core is located. Further, the field used to represent whether the virtual instance supports the broadcast domain configuration in the second registers allocated to the virtual instance on the multiple processor grains can be queried; and when the fields used to represent whether the virtual instance supports the broadcast domain configuration in the second registers allocated to the virtual instance on the multiple processor grains are all set to the identifier corresponding to the virtual instance supporting the broadcast domain configuration, the above operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance is performed.

[0141] The solution for autonomously configuring the broadcast domain of the processor core of the virtual instance provided in the above embodiment may be a function supported by the computing device by default. However, in some embodiments, the computing device does not support broadcast domain configuration by default, but needs to be pre-configured to support autonomous broadcast domain configuration before the processor setting method provided in the above embodiment can be used to configure the broadcast domain of the processor core of the virtual instance.

[0142] In order to realize the autonomous selection of whether the computing device supports the broadcast domain configuration, a register for controlling whether the computing device supports the broadcast domain configuration may be added to the processor 10, which is defined as a third register. For the description of the number and deployment location of the third register, please refer to the relevant content of the aforementioned embodiment, which will not be repeated here.

[0143] The third register may include: a field for indicating whether the host machine (ie, computing device) supports broadcast domain configuration. The field may occupy one or more bits.

[0144] Based on the third register, before allocating the first register and the second register to the virtual instance, the field in the third register used to characterize whether the host machine supports the broadcast domain configuration can be set to an identifier corresponding to the host machine supporting the broadcast domain configuration, so that the host machine supports the broadcast domain configuration.

[0145] In the embodiments of the present application, the specific implementation form of the identifier corresponding to the host machine supporting the broadcast domain configuration is not limited. In some embodiments, the identifier corresponding to the host machine supporting the broadcast domain configuration may be a binary value different from the initial default value of the field. For example, the identifier corresponding to the host machine supporting the broadcast domain configuration may be 1 or 0, etc.

[0146] Accordingly, when the first processor core A of the virtual instance broadcasts an operation instruction, the field in the third register used to characterize whether the host machine supports the broadcast domain configuration can be queried; when the field used to characterize whether the host machine supports the broadcast domain configuration is set to the corresponding identifier of the host machine supporting the broadcast domain configuration, the above-mentioned operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register assigned to the virtual instance is performed.

[0147] In an embodiment in which a second register for controlling whether a virtual instance supports broadcast domain configuration is provided in a processor, when the field for characterizing whether the host machine supports broadcast domain configuration is set to an identifier corresponding to the host machine supporting broadcast domain configuration, the above-mentioned operation of determining the second register assigned to the virtual instance and subsequent operations based on the virtual instance identifier recorded in the field characterizing the virtual instance in the second register can be performed, such as: querying the field in the second register assigned to the virtual instance for characterizing whether the virtual instance supports broadcast domain configuration; when the field for characterizing whether the virtual instance supports broadcast domain configuration is set to an identifier corresponding to the virtual instance supporting broadcast domain configuration, obtaining the broadcast domain of the processor core of the virtual instance from the first register assigned to the virtual instance; and broadcasting the operation instruction to other second processor cores B in the broadcast domain of the processor core of the virtual instance except the above-mentioned first processor core A.

[0148] In some embodiments, the target processor cores assigned to the virtual instance are located on the same processor die, and the first processor core A among the target processor cores assigned to the virtual instance can broadcast operation instructions to other second processor cores B belonging to the virtual instance on the processor die.

[0149] In other embodiments, the target processor cores to which the virtual instances are assigned are located on multiple processor crystals. The multiple processor crystals are independent of each other, and channels between the multiple processor crystals need to be set to achieve broadcasting between the multiple processor crystals 20. Accordingly, the processor may also include a register for controlling the channel range between the multiple processor crystals, which is defined as a fourth register. For the description of the number and deployment location of the fourth register, please refer to the relevant content of the aforementioned embodiment, which will not be repeated here.

[0150] Accordingly, a fourth register may also be allocated to the virtual instance during the virtual instance creation process. Specifically, since the target processor core to which the virtual instance is allocated is located on multiple processor crystals, a fourth register may be selected from the unallocated fourth registers on the multiple processor crystals where the target processor core is located during the virtual instance creation process and allocated to the virtual instance. Multiple fourth registers are allocated to the virtual instance, and the multiple fourth registers correspond one-to-one to the multiple processor crystals, so that a fourth register may be allocated to the virtual instance on each processor crystal where the target processor core is located.

[0151] Furthermore, channel ranges between multiple processor grains may be configured in multiple fourth registers allocated to the virtual instance, respectively, so that the first processor core A of the virtual instance can broadcast the operation instruction to the target processor cores on other processor grains based on the channel ranges between the multiple processor grains. The other processor grains refer to the processor grains other than the target processor grain where the first processor core A is located among the multiple processor grains where the target processor core allocated to the virtual instance is located.

[0152] In some embodiments, if the number of bits of the fourth register on the processor crystal is greater than or equal to the number of channels of the processor crystal, each bit of the fourth register can represent a channel. Accordingly, the channel range between the multiple processor crystals 20 where the target processor core assigned to the virtual instance is located can be set in the form of a bitmap. Specifically, in the fourth register assigned to the virtual instance, the flag bit corresponding to the target channel between the multiple processor crystals can be set to another specified identifier (such as 1 or 0, etc.). The specified identifier can be a binary value different from the initial default value of the corresponding flag bit. Among them, the specified identifier indicates that the target channel corresponding to the flag bit belongs to the channel range of multiple processor crystals. The target channel can be one or more, and the specific number can be flexibly set according to actual needs. In order to reduce the broadcast range, the number of target channels is as small as possible. Therefore, the target channel can be one.

[0153] Based on the set channel range between multiple processor grains, the above step 902 can be implemented as follows: for the first processor core A assigned to the virtual instance, the operation instruction can be broadcast to the other second processor cores B of the processor core A on the target processor grain assigned to the virtual instance; and the channel range between the target processor grain and other processor grains is obtained from the fourth register assigned to the virtual instance on the target processor grain; the other processor grains are the other processor grains except the target processor grain among the multiple processor grains where the target processor core assigned to the virtual instance is located. Further, the operation instruction can be broadcast to the second processor cores B on other processor grains assigned to the virtual instance through the channel corresponding to the channel range between the target processor grain and other processor grains, so as to realize the cross-grain broadcast of the operation instruction.

[0154] The following uses the cache refresh instruction as an example to illustrate the instruction broadcasting method provided in the embodiment of the present application.

[0155] Fig.10 A schematic diagram of a cache refresh instruction broadcast method provided in an embodiment of the present application. A virtual instance is allocated with multiple target processor cores. Fig.10 As shown, the cache refresh instruction broadcast method may include:

[0156] 1001. When a first processor core among multiple target processor cores broadcasts a cache refresh instruction, a broadcast domain of the processor core of the virtual instance is obtained from a first register allocated to the virtual instance; the first register is used to control the broadcast domain of the processor core; the broadcast domain of the processor core of the virtual instance is a broadcast domain defined by multiple processor cores.

[0157] 1002. Broadcast a cache refresh instruction to a second processor core among multiple target processor cores corresponding to a broadcast domain of the processor core of the virtual instance; the second processor core is another processor core among the multiple target processor cores except the first processor core.

[0158] 1003. When receiving a response message returned by the second processor core in response to the cache flush instruction, control the first processor core to execute the next instruction of the cache flush instruction.

[0159] In this embodiment, the first processor core is any processor core in the target processor cores to which the virtual instance is allocated. The cache refresh instruction may be an instruction to refresh the cache, or an instruction to refresh the TLB, such as a TLBi instruction. In this embodiment, the specific content of the next instruction of the cache refresh instruction is not limited. For example, the next instruction of the cache refresh instruction may be an operation instruction, such as an arithmetic operation instruction or a logical operation instruction, or a memory reallocation instruction, or a memory page deletion instruction, etc.

[0160] When the processor core of the virtual instance of this embodiment broadcasts a cache refresh instruction, it limits the broadcast scope of the cache refresh instruction to the target processor core assigned to the virtual instance through the broadcast domain pre-configured by the first register, without broadcasting it to all processor cores in the processor, thereby narrowing the broadcast scope of the cache refresh instruction and reducing the waiting time for the processor core that broadcasts the cache refresh instruction to receive a response message, thereby helping to improve the processing speed of the virtual instance.

[0161] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 801 and 802 can be device A; for another example, the execution subject of step 801 can be device A, and the execution subject of step 802 can be device B; and so on.

[0162] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations appearing in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel, and the sequence numbers of the operations, such as 801, 802, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel.

[0163] Accordingly, an embodiment of the present application also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the above-mentioned broadcast domain device method, and / or instruction broadcast method, and / or cache refresh instruction broadcast method.

[0164] Fig.11 This is a schematic diagram of the structure of the processor provided in the embodiment of the present application. Fig.11 As shown, the processor 10 may include: multiple processor cores 101 and at least one register 102. The at least one register 102 includes a first register 102a; the first register 102a is used to control the broadcast domain of the processor core. The multiple processor cores 101 may be on the same processor die 20, or may be located on different multiple processor die 20.

[0165] In some embodiments, Fig.11 As shown, the processor 10 may further include: a second register 102b, a third register 102c and / or a fourth register 102d. For descriptions of the processor core 101, the first register 102a, the second register 102b, the third register 102c and the fourth register 102d, see the above Figure 1 The relevant content will not be repeated here.

[0166] In some embodiments of the present application, when the processor 10 is deployed in an electronic device, it can run a computer program related to the virtualization manager to execute the relevant steps in the processor setting method provided in the above embodiments. For the description of each step in the processor setting method, please refer to the relevant content of the above embodiments, which will not be repeated here.

[0167] In other embodiments, when the processor 10 is deployed in an electronic device, it can also be used to execute the relevant steps in the instruction broadcast method and / or cache refresh instruction broadcast method provided in the above embodiments. For the description of each step in the instruction broadcast method and cache refresh instruction broadcast method, please refer to the relevant content of the above embodiments, which will not be repeated here.

[0168] In an embodiment of the present application, the memory is used to store a computer program and can be configured to store various other data to support operations on the device where it is located. Among them, the processor can execute the computer program stored in the memory to implement the corresponding control logic. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random-Access Memory, SRAM), electrically erasable programmable read only memory (Electrically Erasable Programmable Read Only Memory, EEPROM), erasable programmable read only memory (Electrical Programmable Read Only Memory, EPROM), programmable read only memory (Programmable Read Only Memory, PROM), read only memory (Read Only Memory, ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0169] In the embodiment of the present application, the processor can be any hardware processing device that can execute the logic of the above method. Optionally, the processor can be a central processing unit (CPU), a graphics processing unit (GPU) or a microcontroller unit (MCU); it can also be a field programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), a complex programmable logic device (CPLD) and other programmable devices; or an advanced reduced instruction set (RISC) processor (Advanced RISC Machines, ARM) or a system on chip (SoC), etc., but not limited to this.

[0170] In an embodiment of the present application, the communication component is configured to facilitate wired or wireless communication between the device in which it is located and other devices. The device in which the communication component is located can access a wireless network based on a communication standard, such as Wireless Fidelity (WiFi), 2G or 3G, 4G, 5G or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be based on Near Field Communication (NFC) technology, Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology or other technologies.

[0171] In an embodiment of the present application, the display component may include a liquid crystal display (LCD) and a touch panel (TP). If the display component includes a touch panel, the display component may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0172] In an embodiment of the present application, a power supply component is configured to provide power to various components of the device in which it is located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply component is located.

[0173] In an embodiment of the present application, the audio component may be configured to output and / or input audio signals. For example, the audio component includes a microphone (Microphone, MIC), and when the device where the audio component is located is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal may be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting an audio signal. For example, for a device with a language interaction function, voice interaction with a user can be achieved through an audio component.

[0174] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0175] It should also be noted that the descriptions such as "first" and "second" in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit "first" and "second" to different types.

[0176] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical storage, etc.) that contain computer-usable program code.

[0177] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0178] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0179] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0180] In a typical configuration, a computing device includes one or more processors (CPU, etc.), input / output interfaces, network interfaces, and memory.

[0181] Memory may include non-permanent storage in a computer-readable medium, random-access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0182] The storage medium of a computer is a readable storage medium, which may also be referred to as a readable medium. The readable storage medium includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0183] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the above elements.

[0184] The above contents are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A processor setting method, characterized in that: include: During the virtual instance creation process, allocating a target processor core in a processor to the virtual instance; Allocating a first register in the processor to the virtual instance; the first register is used to control a broadcast domain of a processor core; A broadcast domain of any processor core in the target processor cores is set in the first register, which is a broadcast domain defined by the target processor core, so that any processor core can broadcast operation instructions to other processor cores in the target processor cores.

2. The method according to claim 1, characterized in that The step of setting the broadcast domain of any one of the target processor cores in the first register as the broadcast domain defined by the target processor core includes: Determining a flag bit corresponding to the target processor core in the first register; The flag bit corresponding to the target processor core is set to a specified identifier; the specified identifier indicates that the target processor core belongs to the broadcast domain of the processor core of the virtual instance.

3. The method according to claim 1, characterized in that The processor further includes: a second register; the second register is used to control whether the virtual instance supports broadcast domain configuration; the method further includes: During the virtual instance creation process, allocating a second register to the virtual instance; Setting the field representing the virtual instance in the second register to the identifier of the virtual instance, so as to bind the second register to the virtual instance; The field in the second register used to indicate whether the virtual instance supports broadcast domain configuration is set to an identifier corresponding to the virtual instance supporting broadcast domain configuration, so that the virtual instance supports broadcast domain configuration.

4. The method according to claim 3, characterized in that The processor further includes: a third register; the third register is used to control whether the host machine where the virtual instance is located supports broadcast domain configuration; before allocating the first register and the second register to the virtual instance, the method further includes: The field in the third register used to indicate whether the host machine supports broadcast domain configuration is set to an identifier corresponding to the host machine supporting broadcast domain configuration, so that the host machine supports broadcast domain configuration.

5. The method according to claim 1, characterized in that The target processor core is located on a plurality of processor dies; the first register is distributed on the plurality of processor dies; The allocating a first register to the virtual instance comprises: During the virtual instance creation process, a plurality of first registers on the plurality of processor crystals are allocated to the virtual instance; the plurality of first registers correspond one-to-one to the plurality of processor crystals; The step of setting the broadcast domain of any one of the target processor cores in the first register as the broadcast domain defined by the target processor core includes: For any processor grain among the multiple processor grains, in the first register allocated to the virtual instance on the any processor grain, the broadcast domain of the any processor core is set, which is a broadcast domain defined for the target processor core corresponding to the any processor grain, so that the any processor core broadcasts operation instructions to the target processor core corresponding to the any processor grain.

6. The method according to claim 3, characterized in that The target processor core is located on a plurality of processor dies; the second register is distributed on the plurality of processor dies; In the process of creating the virtual instance, allocating a second register to the virtual instance includes: During the virtual instance creation process, a plurality of second registers on the plurality of processor dies are allocated to the virtual instance; the plurality of second registers correspond one-to-one to the plurality of processor dies; The step of setting the field representing the virtual instance in the second register as the identifier of the virtual instance includes: For any processor die among the multiple processor die, setting a field representing the virtual instance in a second register allocated to the virtual instance on the any processor die to an identifier of the virtual instance, so as to bind the second register allocated to the virtual instance on the any processor die to the virtual instance; The step of setting the virtual instance in the second register to support broadcast domain configuration includes: In a second register allocated to the virtual instance on any one of the processor dies, setting the virtual instance to support broadcast domain configuration.

7. The method according to claim 5 or 6, characterized in that: The any processor core is located in a target processor grain among the multiple processor grains; each processor grain is provided with a fourth register; the fourth register is used to control the channel range between the multiple processor grains; the method further includes: During the virtual instance creation process, a plurality of fourth registers on the plurality of processor dies are allocated to the virtual instance; the plurality of fourth registers correspond one-to-one to the plurality of processor dies; In the plurality of fourth registers, channel ranges between the plurality of processor crystal grains are respectively configured so that any one of the processor cores can broadcast the operation instruction to target processor cores on other processor crystal grains except the target processor crystal grain based on the channel range between the plurality of processor crystal grains.

8. A command broadcasting method, characterized in that: The virtual instance is allocated with a plurality of target processor cores, and the method comprises: In the case where the first processor core among the multiple target processor cores broadcasts the operation instruction, acquiring the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance; the first register is used to control the broadcast domain of the processor core; the broadcast domain of the processor core of the virtual instance is the broadcast domain defined by the multiple target processor cores; Broadcasting the operation instruction to a second processor core among the multiple target processor cores corresponding to the broadcast domain; the second processor core is another processor core among the multiple target processor cores except the first processor core; When receiving a response message returned by the second processor core to the operation instruction, the first processor core is controlled to execute the next instruction of the operation instruction.

9. The method according to claim 8, characterized in that The virtual instance is allocated with a second register; the second register is used to control whether the virtual instance supports broadcast domain configuration; Before obtaining the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance, the method further includes: In the case where the first processor core broadcasts the operation instruction, determining a second register allocated to the virtual instance according to the virtual instance identifier recorded in the field representing the virtual instance in the second register; querying a field in a second register allocated to the virtual instance for indicating whether the virtual instance supports broadcast domain configuration; When the field used to characterize whether the virtual instance supports broadcast domain configuration is set to the identifier corresponding to the virtual instance supporting broadcast domain configuration, the operation of obtaining the broadcast domain of the processor core of the virtual instance from the first register allocated to the virtual instance is performed.

10. The method according to claim 9, characterized in that The virtual instance is allocated with a third register; the third register is used to control whether the host machine supports broadcast domain configuration; Before querying the field allocated to the second register for characterizing whether the virtual instance supports broadcast domain configuration, the method further includes: In the case where the first processor core broadcasts the operation instruction, querying a field in the third register for indicating whether the host machine supports broadcast domain configuration; The host machine is the physical machine where the virtual instance is located; When the field used to characterize whether the host machine supports broadcast domain configuration is set to an identifier corresponding to the host machine supporting broadcast domain configuration, the operation of determining the second register assigned to the virtual instance is performed based on the virtual instance identifier recorded in the virtual instance field in the second register.

11. A cache refresh instruction broadcast method, characterized in that: The virtual instance is allocated with a plurality of target processor cores, and the method comprises: In the case where a first processor core among the multiple target processor cores broadcasts a cache refresh instruction, acquiring a broadcast domain of the processor core of the virtual instance from a first register allocated to the virtual instance; the first register is used to control the broadcast domain of the processor core; the broadcast domain of the processor core of the virtual instance is the broadcast domain defined by the multiple target processor cores; Broadcasting the cache refresh instruction to a second processor core corresponding to the broadcast domain of the processor core of the virtual instance; the second processor core is another processor core among the multiple target processor cores except the first processor; When receiving a response message returned by the second processor core to the cache flush instruction, the first processor core is controlled to execute the next instruction of the cache flush instruction.

12. A processor, characterized in that: include: A plurality of processor cores and at least one register; the at least one register comprises a first register; the first register is used to control a broadcast domain of the processor core; When the processor is deployed in an electronic device, it is used to execute the steps in the method according to any one of claims 1 to 11.

13. A computing device, characterized in that: include: A memory and a processor; wherein the memory is used to store computer programs; the processor includes multiple processor cores; Each processor core includes at least one register; the at least one register includes a first register; the first register is used to control the broadcast domain of the processor core; The processor is coupled to the memory and is configured to execute the computer program for performing the steps in the method according to any one of claims 1 to 11.

14. A computer-readable storage medium storing computer instructions, characterized in that: When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the method according to any one of claims 1 to 11.

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