Data storage method, processing unit, processor, system on chip, computer storage medium and computer program product

Abstract

The embodiment of the invention provides a data storage method, a processing unit, a processor, a system on chip, a computer storage medium and a computer program product. The processing unit is configured on a local node of the network-on-chip, the processing unit comprises a first index buffer used for managing a local memory in the local node, and the first index buffer determines a first address allocation state when obtaining first data from an upstream node, when the first address allocation state indicates that the remaining index space meeting the data length of the first data exists, allocating an address field of the first data in the remaining index space, and updating the first address allocation state; the address management unit is used for managing a first address mapping relationship between the first index space of the first index buffer and the first memory space of the local memory; and the memory bus unit is used for storing the first data in a memory address field corresponding to the address field of the first data in the first memory space.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular, to a data storage method, a processing unit, a processor, a system on a chip, a computer storage medium, and a computer program product. Background Art

[0002] In the System on Chip (SoC) architecture, the Network on Chip (NoC) is widely used to connect various processing units, which can include processing cores, digital signal processing modules (DSPs), dedicated hardware accelerators (PEs), and memory and other hardware components. The bandwidth and throughput of the NoC are crucial to the performance of the entire system and directly affect the efficiency and speed of data transmission.

[0003] Since the processing unit includes hardware components such as DSPs, PEs and memory, different interface protocols may be used to optimize the performance of the hardware components. In order to enable the hardware components to communicate effectively through NoC, the data of the hardware component protocol is usually converted into transaction data packets suitable for NoC through a network interface controller (NIC), and then the NoC is used to route the transaction data packets between different processing units.

[0004] In order to ensure the reliability of data transmission between different processing units, the processing core in the processing unit needs to know the memory occupancy status of other processing units, which reduces the processing efficiency of the processing core in the processing unit. Summary of the invention

[0005] In view of this, embodiments of the present invention provide a data storage method, a processing unit, a processor, a system on chip, a computer storage medium, and a computer program product to solve the above problems.

[0006] According to a first aspect of an embodiment of the present invention, a processing unit is provided, which is configured in a local node of an on-chip network, and the processing unit includes: a first index buffer, used to manage local memory in the local node, when the first index buffer obtains first data from an upstream node, determines a first address allocation state, and when the first address allocation state indicates that there is remaining index space that meets the data length of the first data, allocates an address segment of the first data in the remaining index space, and updates the first address allocation state; an address management unit, used to manage a first address mapping relationship between a first index space of the first index buffer and a first memory space of the local memory; a memory bus unit, used to store the first data in a memory address segment in the first memory space corresponding to the address segment of the first data.

[0007] In another implementation of the present invention, the processing unit further includes an on-chip bus unit, wherein the on-chip bus unit is used to: parse a first data packet obtained from the upstream node based on a first bus protocol with the upstream node to obtain the first data and its data length. The memory bus unit is used to: store the first data into a corresponding memory address segment in the first memory space based on a second bus protocol with the access memory.

[0008] In another implementation of the present invention, the processing unit further includes a data buffer. The data buffer is used to read the first data into a data buffer queue, and when the first data is dequeued from the data buffer queue, store the first data into a corresponding memory address segment in the first memory space through the memory bus unit.

[0009] In another implementation of the present invention, the processing unit further includes a second index buffer. The second index buffer is used to: determine a second address allocation state when the first address allocation state indicates that there is no remaining index space that satisfies the data length of the first data, and when the second address allocation state indicates that there is remaining index space that satisfies the data length of the first data, allocate the address segment of the first data in the remaining index space, and update the second address allocation state. The address management unit is also used to: map the second address between the second index space of the second index buffer and the second memory space of the local memory. The memory bus unit is also used to: store the first data in the memory address segment in the second memory space that corresponds to the address segment of the first data.

[0010] In another implementation of the present invention, the processing unit also includes an initialization unit, which is used to: map the continuous memory space of the local memory to the first index space and the second index space, so that the first memory space in the continuous memory space corresponds to the first index space of the first index buffer, and the second memory space in the continuous memory space corresponds to the second index space.

[0011] In another implementation of the present invention, the address management unit is also used to: after storing the first data in a memory address segment corresponding to the address segment of the first data in the first memory space, when the first address allocation state meets a preset memory refresh condition, create a third address mapping relationship between the third memory space and the first index space to update the first address mapping relationship.

[0012] In another implementation of the present invention, the first index buffer is specifically used to: determine the allocation pointer corresponding to the end address of the currently allocated address segment based on the first address allocation status, and move the allocation pointer to the corresponding address segment of the data length of the first data, perform an allocation operation on the corresponding address segment, and update the corresponding address segment to the currently allocated address segment.

[0013] In another implementation of the present invention, the first index buffer is further used to update the next allocated address segment to the current allocated address segment when the allocation pointer reaches the next allocated address segment before moving the address segment corresponding to the data length of the first data.

[0014] In another implementation of the present invention, the first index buffer is also used to: when the allocation pointer reaches the next allocated address segment before moving the address segment corresponding to the data length of the first data, determine the starting address of the next allocated address segment as the ending address of the current allocated address segment.

[0015] In another implementation of the present invention, the first index buffer is a circular buffer, and the end address of the first index space is continuous with the start address.

[0016] In another implementation of the present invention, the first index buffer is further used to release the allocated address segment of the first data in the first index space after the first data is deleted from the memory address segment corresponding to the first memory space.

[0017] In another implementation of the present invention, the first index buffer is specifically used to: determine the release pointer corresponding to the end address of the last released address segment based on the first address allocation status, place the release pointer at the starting position of the allocated address segment of the first data, and move the release pointer from the starting position to the end position of the allocated address segment to release the allocated address segment.

[0018] According to a second aspect of an embodiment of the present invention, there is provided a processor, comprising: a plurality of processing units, each processing unit being configured as the processing unit according to the first aspect.

[0019] According to a third aspect of an embodiment of the present invention, there is provided a system on chip, comprising: an on-chip network and the processor according to the second aspect, wherein a plurality of processing units in the processor are interconnected via the on-chip network.

[0020] According to a fourth aspect of an embodiment of the present invention, a data storage method is provided, which is applied to a local node of an on-chip network, and the method comprises: when first data is obtained from an upstream node, determining a first address allocation state of a first index buffer, wherein the first index buffer is used to manage a local memory in the local node, and a first index space of the first index buffer is configured to have a first address mapping relationship with a first memory space of the local memory; when the first address allocation state indicates that there is remaining index space that satisfies a data length of the first data, allocating an address segment of the first data in the remaining index space, and updating the first address allocation state; and storing the first data in a memory address segment in the first memory space that corresponds to the address segment of the first data.

[0021] According to the fifth aspect of an embodiment of the present invention, a processing unit is provided, comprising: a controller, a memory, an on-chip bus interface and an internal bus, wherein the controller, the memory and the on-chip bus interface communicate with each other via the internal bus; the memory is used to store at least one executable instruction, and the executable instruction enables the controller to execute the method described in the fourth aspect.

[0022] According to a sixth aspect of an embodiment of the present invention, there is provided a computer storage medium on which a computer program is stored. When the program is executed by a processing unit, the method described in the fourth aspect is implemented.

[0023] According to a seventh aspect of an embodiment of the present invention, there is provided a computer program product, comprising computer instructions, which, when executed by a processing unit, implement the method as described in the fourth aspect.

[0024] In the scheme of the embodiment of the present invention, the first index space of the first index buffer has a first address mapping relationship with the first memory space of the local memory, which reduces the configuration complexity of the first index buffer and is conducive to the configuration of the first index buffer through hardware. In addition, when the first index buffer obtains the first data from the upstream node, it determines the first address allocation state, and when the first address allocation state indicates that there is a remaining index space that meets the data length of the first data, it allocates the address segment of the first data in the remaining index space, and updates the first address allocation state, so that without the need for the processing core to intervene in the data storage process of the local memory, the first index buffer can achieve efficient management of the data storage process through the first address allocation state, thereby ensuring the processing efficiency of the processing core in the processing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0026] Figure 1 A schematic block diagram of a system on a chip to which some embodiments of the present invention are applicable.

[0027] Figure 2 Schematic block diagrams of processing units according to some other embodiments of the present invention.

[0028] Figure 3A for Figure 2 Schematic block diagram of a processing unit of some examples of embodiments.

[0029] Figure 3B for Figure 2 Schematic diagram of the address mapping relationship of the embodiment.

[0030] Figure 4A for Figure 2 Schematic diagram of address segment management of index buffers of some examples of embodiments.

[0031] Figure 4B for Figure 2 Schematic diagram of address segment management of index buffers in some other examples of embodiments.

[0032] Figure 4C for Figure 2 Schematic diagram of address segment management of index buffers in some other examples of embodiments.

[0033] Figure 5 for Figure 2 A schematic diagram of an embodiment of a data management process through different index buffers.

[0034] Figure 6 The present invention is a flowchart of the steps of a data storage method according to some other embodiments of the present invention.

[0035] Figure 7 Schematic diagram of the structure of a processing unit according to some other embodiments of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0037] The specific implementation of the embodiment of the present invention is further described below in conjunction with the accompanying drawings of the embodiment of the present invention.

[0038] Figure 1 A system on a chip is shown to which some embodiments of the present invention are applicable. Figure 1 The system on chip 100 includes a processor composed of multiple processing units 10 and an on-chip network 20. Each processing unit 10 in the processor is deployed on a routing node (i.e., R0-R11) of the on-chip network 20 to transmit data with other processing units 10 through the on-chip network 20 with the help of the routing node. The processing unit 10 includes but is not limited to hardware components such as processing cores, digital signal processing modules (DSPs), dedicated hardware accelerators (PEs), and memory (i.e., MEM). The processing unit 10 generally also includes a network interface controller (NIC), and the data of the protocol of the hardware component is converted into a transaction data packet suitable for NoC through the NIC, and then the transaction data packet is routed by NoC between different processing units.

[0039] The network interface controller usually handles the input and output between the on-chip network and the hardware components in the processing unit, performs necessary protocol conversion, and manages the routing of transaction data packets. The bus protocols of the on-chip network and the bus protocols of the hardware components converted by the network interface controller include but are not limited to: Advanced Microcontroller Bus Architecture (AMBA), Advanced Extension Interface (AXI), Advanced Peripheral Bus (APB), Open Core Protocol (OCP), Peripheral Component Interconnect Express (PCIe), Wishbone protocol, etc. By performing protocol conversion between the bus protocols of the on-chip network and the bus protocols of the hardware components, data transmission efficiency between different processing units is achieved.

[0040] In order to ensure the reliability of data transmission between different processing units, the processing core in a processing unit needs to know the memory occupancy status of other processing units, which reduces the processing efficiency of the processing core in the processing unit. The various embodiments of the present invention can ensure the processing efficiency of the processing core in the processing unit.

[0041] For example, in Figure 2In some embodiments shown, the processing unit 10 is configured in a local node of the on-chip network 20. The processing unit 10 includes a first index buffer 210, an address management unit 220, and a memory bus unit 230.

[0042] Specifically, the first index buffer 210 is used to manage the local memory in the local node. When the first index buffer obtains the first data from the upstream node, it determines the first address allocation state, and when the first address allocation state indicates that there is remaining index space that meets the data length of the first data, it allocates the address segment of the first data in the remaining index space and updates the first address allocation state.

[0043] It should be understood that in some examples, the first index buffer 210 can be set in the network interface controller, and the first index controller 210 performs address management on the first data after the network interface controller parses the first data packet to obtain the first data. Similarly, the processing unit can also include a second index buffer (not shown), and the second index buffer can also be set in the network interface controller.

[0044] It should also be understood that the local memory can be accessed by the processing core in the processing unit. The first memory space can be part of the memory space divided in the local memory, and the other part of the memory space is a memory space dedicated to the processing core. The storage process of the first memory space can be managed by the first index buffer, that is, the first index buffer can manage write operations to the first memory space. The first memory space can be a continuous memory space or a non-continuous memory space. Similarly, the storage process of the second memory space can be managed by the second index buffer, that is, the second index buffer can manage write operations to the second memory space. For example, the second memory space can be part of the memory space divided in the local memory, and the second memory space can be a continuous memory space or a non-continuous memory space.

[0045] In addition, the address management unit 220 is used to manage a first address mapping relationship between a first index space of the first index buffer and a first memory space of the local memory.

[0046] It should be understood that the first address mapping relationship indicates the correspondence between the first index space and the first memory space. For example, the index address in the first index space can be used as the first address of the memory address of the first memory space, and the memory address of the first memory space = the first address + the address offset. Similarly, the second address mapping relationship managed by the second index buffer indicates the correspondence between the second index space and the second memory space. For example, the index address in the second index space can be used as the first address of the memory address of the second memory space, and the memory address of the second memory space = the first address + the address offset.

[0047] It should also be understood that the first memory space and the second memory space can constitute a continuous memory space in the local memory, and this continuous memory space can be a part of the memory space divided from the entire memory space of the local memory, and can be dynamically allocated. For example, when it is full or nearly full, or when the memory space dedicated to the processing core in the local memory is insufficient, the memory space managed by the index buffer can be dynamically allocated, for example, releasing part of the memory space managed by the index buffer as a dedicated memory space for the processing core. In addition, both the first memory space and the second memory space can be non-continuous memory spaces, and the continuous memory space of the local memory is managed as a whole by the first index buffer and the second index buffer.

[0048] In addition, the memory bus unit 230 is used to store the first data into a memory address segment in the first memory space corresponding to the address segment of the first data.

[0049] It should be understood that the memory bus unit 230 may be a memory bus interface of a network interface controller, and the on-chip bus interface of the network interface controller is used to obtain the first data packet and parse the first data packet to obtain the first data.

[0050] In the scheme of the embodiment of the present invention, the first index space of the first index buffer has a first address mapping relationship with the first memory space of the local memory, which reduces the configuration complexity of the first index buffer and is conducive to the configuration of the first index buffer through hardware. In addition, when the first index buffer obtains the first data from the upstream node, it determines the first address allocation state, and when the first address allocation state indicates that there is a remaining index space that meets the data length of the first data, it allocates the address segment of the first data in the remaining index space, and updates the first address allocation state, so that the first index buffer can achieve efficient management of the data storage process through the first address allocation state without the need for the processing core etc. to intervene in the data storage process of the local memory.

[0051] In some cases, in order to ensure the reliability of data transmission between different processing units, the processing core in a processing unit needs to know the memory occupancy status of other processing units, for example, setting the memory in other processing units to be the global memory or shared memory of the processing unit. However, the processing unit of an embodiment of the present invention does not need to know the memory status of other processing units when sending data packets.

[0052] In some cases, after a processing unit learns about the memory occupancy status of other processing units, other processing units will request space in a buffer used to manage memory space allocation. In an embodiment of the present invention, the index buffer can achieve efficient management of the data storage process through the address allocation status without the need for the processing core to intervene in the data storage process of the local memory.

[0053] In some cases, a processing unit sends a snoop request to other processing units to obtain the memory occupancy status of other processing units, while the embodiment of the present invention avoids sending data consistency operations such as snoop requests to other processing units.

[0054] Specifically, in some embodiments, Figure 3A As shown, the processing unit 10 includes a processing core (not shown), a network interface controller 200 and a local memory 30. The network interface controller 200 includes a first index buffer 210, an address management unit 220, a memory bus unit 230, a data buffer 240, and an on-chip bus unit 250.

[0055] Exemplarily, the on-chip bus unit 250 parses the first data packet obtained from the upstream node, obtains the first data and its data length, stores the first data in the data buffer 240, and provides the data packet attribute information such as the data length to the first index buffer 210. Then, the first index buffer 210 determines the allocated address segment of the first data in the first index space, and determines the memory address segment corresponding to the allocated address segment in the first memory space of the local memory 30 by querying the first address mapping relationship of the address management unit 220. Then, the memory bus unit 230 stores the first data in the corresponding memory address segment in the first memory space based on the second bus protocol.

[0056] Without loss of generality, the on-chip bus unit 250 is used to parse the first data packet obtained from the upstream node based on the first bus protocol between the upstream node and obtain the first data and its data length. The memory bus unit 230 is used to store the first data into the corresponding memory address segment in the first memory space based on the second bus protocol between the access memory. It should be understood that by configuring the address management of the first index buffer in the protocol conversion process of the network interface controller, the protocol conversion of the network interface controller is compatible and the address management logic is simplified.

[0057] Further, the on-chip bus unit 250 parses the first data packet obtained from the upstream node, obtains the first data and its data length, and stores the first data in the data buffer 240. For example, the data buffer is used to read the first data into the data buffer queue, and when the first data is dequeued from the data buffer queue, the first data is stored in the corresponding memory address segment in the first memory space through the memory bus unit. It should be understood that the data buffer is separated from the first index buffer, which is compatible with the configuration of the data buffer. In addition, the reliability of storing the first data in the first memory space of the local memory is guaranteed through the notification logic between the data buffer and the first index buffer.

[0058] Further, in the case where the occupancy rate of the first index space is high, the address segment corresponding to the first data in the first index space is continuously occupied, and accordingly, the first address mapping relationship can be updated by the address management unit. For example, after the address management unit stores the first data in the memory address segment corresponding to the address segment of the first data in the first memory space, when the first address allocation state meets the preset memory refresh condition, a third address mapping relationship between the third memory space and the first index space is created to update the first address mapping relationship. It should be understood that the first memory space can be accessed by the processing core in the processing unit. After the first data is stored in the first memory space, in order to avoid conflicts in the first memory space, the address segment corresponding to the first data in the first index space is continuously occupied. Therefore, when the preset memory refresh condition such as the case where the occupancy rate of the first index space is high is met, a third address mapping relationship between the third memory space and the first index space is created to update the first address mapping relationship, which releases the first index space and can improve the address segment allocation efficiency of the first index space.

[0059] In some examples, the address management unit is used to manage a first address mapping relationship between a first index space of the first index buffer and a first memory space of the local memory, and / or a second address mapping relationship between a second index space of the second index buffer and a second memory space of the local memory. As an example of the first address mapping relationship, Figure 3B As shown, the index address segment in the first index space corresponds to the memory address segment of the first memory space, and the address length of the memory address segment is an integer multiple of the address length of the corresponding index address segment, for example, 1024 times. Specifically, 1024 bits in the first index space represent 1024*1024 bits in the first memory space. Among them, the 3rd bit in the first index space corresponds to the 1024*3rd bit in the first memory space. It should be understood that the index address in the index address segment can also be used as the first address of the memory address in the memory address segment, and the memory address is the first address + address offset. In addition, as an example of the second address mapping relationship, such as Figure 3B As shown, the index address segment in the second index space corresponds to the memory address segment in the second memory space, and the address length of the memory address segment is an integer multiple of the address length of the corresponding index address segment. It should be understood that the index address in the index address segment can also be used as the first address of the memory address in the memory address segment, and the memory address is the first address + address offset.

[0060] The following will be combined Figure 4A-4C The diagram of Figure 2 The embodiments of the present invention are described in detail. Figure 4A-4CIn the example, a blank square with a value of 0 represents an uninitialized address segment; a shaded square with a value of 1 represents an initialized unallocated address segment; a grayscale square with a value of 0 represents an allocated address segment; a shaded square with a value of 0 represents an initialized residual address segment, which can be determined as an allocated address segment or an unallocated address segment.

[0061] Further, in Figure 4A-4C In the example, the index space of the first index buffer has 1K bits, for example, the address range of the index space is the address segment between the first address and the last address, that is, the last address of the index space = the first address + 1023 bits, and the first index space is the result of initializing at least part of the address segment of the index space, that is, the initialized address segment. Figure 4A-4C In the example of , the first index space has 65 bits, for example, the first address of the first index space = the last address of the first index space + 64 bits, and the first address of the first index space can be any address. Figure 4A In the example, the first address allocation state indicates that none of the address segments in the first index space is a free address segment, that is, the occupied address length is 0 (that is, the memory address segment is 0 bits). The allocation pointer and the release pointer are both at the first address. It should be understood that for convenience, the example of the first address being 0 is used to illustrate and describe the first index space, but those skilled in the art can use any other first address to obtain other examples.

[0062] Furthermore, if Figure 4B As shown, when the data length of the first data corresponds to a 3-bit index address segment, the address of the allocation pointer is determined to be the 59th bit. Accordingly, the pointer movement direction of the first index space is the direction of increasing index addresses. When the allocation pointer reaches the end address of the first index space, it continues to move from the first address, and the allocation pointer moves 3 bits from the 59th bit as the starting position to the 62nd bit. It should be understood that the address of the allocation pointer can be any address in the free address segment, for example, the allocation pointer is at the end address of the allocated address segment after completing the allocation of the previous data, or the address behind the end address of the allocated address segment. In other words, the first index buffer can determine the allocation pointer corresponding to the end address of the current allocated address segment based on the first address allocation state, or directly determine the allocation pointer corresponding to the specified address.

[0063] Without loss of generality, when allocating the address segment of the first data, the first index buffer moves the allocation pointer to the corresponding address segment of the data length of the first data, performs an allocation operation on the corresponding address segment, obtains the allocated address segment of the first data, and updates the corresponding address segment to the currently allocated address segment.

[0064] In this example, the first address allocation state indicates that the address segment from bit 59 to bit 62 in the first index space is an allocated address segment, and the other address segments are space address segments. In addition, the release pointer is at the first address, and the allocation pointer is at the 62nd bit.

[0065] Further, refer to Figure 4B , when the first data length corresponds to a 5-bit index address segment, the address of the allocation pointer is first determined to be the 62nd bit. When there is a sufficient free address segment after the 62nd bit, the allocation pointer can move 5 bits with the 62nd bit as the starting position. In fact, the end address of the first index space is the 64th bit. The allocation pointer moves 2 bits with the 62nd bit as the starting position to reach the end address of the first index space, thereby failing to allocate an address segment that meets the data length of the first data. Then, the allocation pointer is placed at the end address of the next allocated address segment. Although the end address and the first address of the first index space are continuous when the first index buffer is a circular buffer, since the addresses of the end address and the first address in the first memory space are actually discontinuous, the first address of the first index space is equivalent to the end address of the next allocated address segment (that is, the address segment between the 62nd bit and the 64th bit can be regarded as an allocated address segment). Therefore, if Figure 4B As shown, the allocation pointer moves 5 bits from the 0th bit as the starting position to the 5th bit, that is, the address segment between the 0th bit and the 5th bit is determined as the allocated address segment of the first data. In addition, the allocated address segment of the first data is updated to the current allocated address segment, that is, the allocation pointer is at the end address of the allocated address segment of the first data.

[0066] Without loss of generality, when the allocation pointer reaches the next allocated address segment before the allocation pointer moves to the address segment corresponding to the data length of the first data, the first index buffer updates the next allocated address segment to the current allocated address segment.

[0067] In addition, when the first index buffer reaches the next allocated address segment before the allocation pointer moves the address segment corresponding to the data length of the first data, the start address of the next allocated address segment is determined as the end address of the current allocated address segment. For example, in the first index space, the next allocated address segment is before the current allocated address segment, and the first address of the first index space is equivalent to the end address of the next allocated address segment. Figure 4B In the example of , bits 62 to 64 are determined as the allocated address segment.

[0068] In this example, the first address allocation state indicates that the address segment from bit 0 to bit 5 and the address segment from bit 59 to bit 62 in the first index space are allocated address segments, that is, the occupied address length is 10 (that is, the memory address segment is 1024*10 bits), and the other address segments are space address segments. In addition, the release pointer is at the first address, and the allocation pointer is at the 5th bit.

[0069] Further, in Figure 4C In the example, when the address segment from the 59th to the 64th bit is released, the release pointer can be placed at the 59th bit and moved by a length not greater than the length of the allocated address field to obtain the released address segment. For example, when the first index buffer receives a release request for the first data, the release pointer is moved from the 59th bit to the 62nd bit. Alternatively, when the 62nd to the 64th bit is determined to be the allocated address segment, the release pointer can be moved from the 59th bit to the 63rd bit, as shown in FIG. Figure 4C Alternatively, the release pointer may be moved from bit 59 to bit 64.

[0070] In addition, when releasing at least part of the address segment of the 59th to 64th bits, at least part of the address segment can be forcibly released by generating a release request. It is also possible to respond to the release request of the first data and use the release pointer to release the allocated address segment of the first data. For example, the first index buffer generates a release request for the first data after the first data is deleted from the memory address segment corresponding to the first memory space, and releases the allocated address segment of the first data in the first index space.

[0071] In some specific examples, the first index buffer determines the release pointer corresponding to the end address of the last released address segment based on the first address allocation status, places the release pointer at the starting position of the allocated address segment of the first data, and moves the release pointer from the starting position to the end position of the allocated address segment to perform a release operation on the allocated address segment.

[0072] It should be understood that the allocated address segment of the first data may not include the address segment between the starting address of the next allocated address segment and the ending address of the current allocated address segment, or may include the address segment between the starting address of the next allocated address segment and the ending address of the current allocated address segment.

[0073] In this example, the first address allocation state indicates that the address segment from bit 0 to bit 5 in the first index space and the address segment corresponding to bit 63 are allocated address segments, that is, the occupied address length is 6 (that is, the memory address segment is 1024*6 bits), and the other address segments are space address segments. In addition, the release pointer is at bit 63 and the allocation pointer is at bit 5.

[0074] In some other embodiments, the processing unit includes a first index buffer and a second index buffer. The address management unit is used to manage a first address mapping relationship between the first index space and the first memory space, and a second address mapping relationship between the second index space and the second memory space.

[0075] In addition, the processing unit also includes an initialization unit, which can initialize part of the space in at least one of the first index space and the second index space. For example, the initialization unit maps the continuous memory space of the local memory to the first index space and the second index space, so that the first memory space in the continuous memory space corresponds to the first index space of the first index buffer, and the second memory space in the continuous memory space corresponds to the second index space. It should be understood that the continuous memory space of the local memory is mapped to the first index space and the second index space, which can ensure the global consistency of the first index space and the second index space when switching between the first index buffer and the second index buffer, avoid data management conflicts between the first index buffer and the second index buffer, and further improve the reliability of data storage.

[0076] That is to say, the first memory space and the second memory space can constitute a continuous memory space in the local memory, and this continuous memory space can be a part of the memory space divided from the whole memory space of the local memory, and can be dynamically allocated. For example, when it is full or nearly full, or when the memory space dedicated to the processing core in the local memory is insufficient, the memory space managed by the index buffer can be dynamically allocated, for example, releasing part of the memory space managed by the index buffer as the dedicated memory space for the processing core. In addition, both the first memory space and the second memory space can be non-continuous memory spaces, and the continuous memory space of the local memory is managed as a whole by the first index buffer and the second index buffer.

[0077] Figure 5 The data storage process in the case of two index buffers is shown, where index buffer 0 is an example of a first index buffer and index buffer 1 is an example of a second index buffer. In buffer state (a), index buffer 0 and index buffer 1 are initialized.

[0078] In buffer state (b), when the current data packet is received, index buffer 0 allocates index address segments for the current data packet, and when the remaining index space of index buffer 0 is sufficient, index address segments continue to be allocated for subsequent data packets.

[0079] In the buffer state (c), the remaining index space of the index buffer 0 is insufficient, the available state of the index buffer 0 is locked, and the index buffer 1 is switched to the available state.

[0080] In buffer state (d), index buffer 1 allocates index address segments for subsequent data packets. That is, when the first address allocation state indicates that there is no remaining index space that meets the data length of the first data, the second index buffer determines the second address allocation state, and when the second address allocation state indicates that there is remaining index space that meets the data length of the first data, the second index buffer allocates the address segment of the first data in the remaining index space, updates the second address allocation state, and the second index buffer stores the first data in the memory address segment corresponding to the address segment of the first data in the second memory space through the memory bus unit. It should be understood that by the separate setting of the first index buffer and the second index buffer, when the first address allocation state indicates that there is no remaining index space that meets the data length of the first data, the second index buffer is used to ensure the timeliness of the data input processing of the first data. At the same time, by switching between different index buffers, the time resources of data input processing of one index buffer are fully utilized, and the time resources of data output management of another index buffer are improved.

[0081] In buffer state (e), the remaining index space of index buffer 1 is insufficient, the available state of index buffer 1 is locked, and when index buffer 1 processes a data packet, at least part of the index space of index buffer 0 is gradually released, and index buffer 0 can be switched to the available state. It should be understood that the remaining index space of index buffer 0 is insufficient, the available state of index buffer 0 can be locked, and it is checked whether the index space of index buffer 1 is available, and if it is available, index buffer 1 is switched to the available state.

[0082] In buffer state (f), the index space of index buffer 1 is unavailable, in which case the available states of index buffer 0 and index buffer 1 are both locked. In connection, an address mapping relationship between the update memory space of index buffer 0 and its index space may be created to update the previous address mapping relationship, thereby making the index space of index buffer 0 available, or an address mapping relationship between the update memory space of index buffer 1 and its index space may be created to update the previous address mapping relationship, thereby making the index space of index buffer 1 available. Without loss of generality, for the first index buffer, a third address mapping relationship between the third memory space and the first index space may be created to update the first address mapping relationship; for the second index buffer, a third address mapping relationship between the third memory space and the second index space may be created to update the second address mapping relationship.

[0083] The following will be combined Figure 6 To describe data storage methods according to other embodiments of the present invention. Figure 6 The data storage method corresponds to Figure 2Specifically, the data storage method is applied to a local node of the on-chip network, including:

[0084] S610: When the first data is obtained from the upstream node, a first address allocation state of a first index buffer is determined, wherein the first index buffer is used to manage the local memory in the local node, and a first index space of the first index buffer is configured to have a first address mapping relationship with a first memory space of the local memory.

[0085] S620: When the first address allocation status indicates that there is remaining index space that satisfies the data length of the first data, allocate an address segment of the first data in the remaining index space, and update the first address allocation status.

[0086] S630: Store the first data in a memory address segment in the first memory space that corresponds to the address segment of the first data.

[0087] In the scheme of the embodiment of the present invention, the first index space of the first index buffer has a first address mapping relationship with the first memory space of the local memory, which reduces the configuration complexity of the first index buffer and is conducive to the configuration of the first index buffer through hardware. In addition, when the first index buffer obtains the first data from the upstream node, it determines the first address allocation state, and when the first address allocation state indicates that there is a remaining index space that meets the data length of the first data, it allocates the address segment of the first data in the remaining index space, and updates the first address allocation state, so that the first index buffer can achieve efficient management of the data storage process through the first address allocation state without the need for the processing core etc. to intervene in the data storage process of the local memory.

[0088] In some cases, in order to ensure the reliability of data transmission between different processing units, the processing core in a processing unit needs to know the memory occupancy status of other processing units, for example, setting the memory in other processing units to be the global memory or shared memory of the processing unit. However, the processing unit of an embodiment of the present invention does not need to know the memory status of other processing units when sending data packets.

[0089] In some cases, after a processing unit learns about the memory occupancy status of other processing units, other processing units will request space in a buffer used to manage memory space allocation. In an embodiment of the present invention, the index buffer can achieve efficient management of the data storage process through the address allocation status without the need for the processing core to intervene in the data storage process of the local memory.

[0090] In some cases, a processing unit sends a snoop request to other processing units to obtain the memory occupancy status of other processing units, while the embodiment of the present invention avoids sending data consistency operations such as snoop requests to other processing units.

[0091] In some other embodiments, the data storage method further comprises: based on a first bus protocol with the upstream node, parsing a first data packet obtained from the upstream node to obtain the first data and its data length. Storing the first data in a memory address segment corresponding to the address segment of the first data in the first memory space comprises: based on a second bus protocol with the access memory, storing the first data in a corresponding memory address segment in the first memory space.

[0092] In some other embodiments, the data storage method further includes: reading the first data into a data buffer queue of the local node. Storing the first data in a memory address segment corresponding to the address segment of the first data in the first memory space includes: when the first data is dequeued from the data buffer queue, storing the first data in the corresponding memory address segment in the first memory space.

[0093] In some other embodiments, the data storage method also includes: when the first address allocation state indicates that there is no remaining index space that meets the data length of the first data, determining a second address allocation state of a second index buffer, wherein the second index space of the second index buffer is configured to have a second address mapping relationship with the second memory space of the local memory; when the second address allocation state indicates that there is remaining index space that meets the data length of the first data, allocating an address segment of the first data in the remaining index space, and updating the second address allocation state; and storing the first data in a memory address segment in the second memory space that corresponds to the address segment of the first data.

[0094] In other embodiments, the data storage method also includes: mapping the continuous memory space of the local memory to the first index space and the second index space, so that the first memory space in the continuous memory space corresponds to the first index space of the first index buffer, and the second memory space in the continuous memory space corresponds to the second index space.

[0095] In other embodiments, after storing the first data in a memory address segment corresponding to the address segment of the first data in the first memory space, the data storage method further includes: when the first address allocation state satisfies a preset memory refresh condition, creating a third address mapping relationship between a third memory space and the first index space to update the first address mapping relationship.

[0096] In other embodiments, when the first address allocation status indicates that there is remaining index space that satisfies the data length of the first data, an address segment of the first data is allocated in the remaining index space, and the first address allocation status is updated, including: based on the first address allocation status, determining an allocation pointer corresponding to the end address of the currently allocated address segment; moving the allocation pointer to the corresponding address segment of the data length of the first data, performing an allocation operation on the corresponding address segment, and updating the corresponding address segment to the currently allocated address segment.

[0097] In some other embodiments, the data storage method further includes: when the allocation pointer reaches the next allocated address segment before moving the address segment corresponding to the data length of the first data, updating the next allocated address segment to the current allocated address segment.

[0098] In other embodiments, before updating the next allocated address segment to the current allocated address segment, the method further includes: when the allocation pointer reaches the next allocated address segment before moving the corresponding address segment of the data length of the first data, determining the starting address of the next allocated address segment as the ending address of the current allocated address segment.

[0099] In some other embodiments, the first index buffer is a circular buffer, and the end address of the first index space is continuous with the start address.

[0100] In some other embodiments, the data storage method further includes: after the first data is deleted from the memory address segment corresponding to the first memory space, releasing the allocated address segment of the first data in the first index space.

[0101] In other embodiments, releasing the allocated address segment of the first data in the first index space includes: determining a release pointer corresponding to the end address of the last released address segment based on the first address allocation status; placing the release pointer at the starting position of the allocated address segment of the first data; moving the release pointer from the starting position to the end position of the allocated address segment, and performing a release operation on the allocated address segment.

[0102] It should be understood that the specific implementation of each step in the data storage method can refer to the corresponding description of the corresponding unit in the processing unit, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above data storage method and steps can refer to the description of the corresponding unit in the processing unit, which will not be repeated here.

[0103] Reference Figure 7, shows a schematic diagram of the structure of a processing unit according to another embodiment of the present invention. The specific embodiment of the present invention does not limit the specific implementation of the processing unit.

[0104] like Figure 7 As shown, the processing unit may include: a controller (processor) 702 for executing a program 710 , an on-chip bus interface (NoC Bus Interface) 704 , a memory (memory) 706 , and an internal bus 708 .

[0105] The controller, on-chip bus interface, and memory communicate with each other via the internal bus.

[0106] On-chip bus interface for communication with other processing units or servers.

[0107] The controller is used to execute the program, and specifically can execute the relevant steps in the above method embodiment.

[0108] Specifically, the program may include program codes including computer operation instructions.

[0109] The controller may be a CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0110] The memory is used to store programs. The memory may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0111] The program may include multiple computer instructions. Specifically, the program may enable the processing unit to execute the data storage method described in any of the aforementioned method embodiments through the multiple computer instructions.

[0112] The specific implementation of each step in the program can refer to the corresponding description of the corresponding steps, modules or units in the above method embodiments, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described device, equipment or module can refer to the corresponding process description in the above method embodiments, which will not be repeated here.

[0113] The embodiment of the present invention further provides a computer storage medium on which a computer program is stored, and when the program is executed by a processing unit, the method described in any of the above-mentioned multiple method embodiments is implemented. The computer storage medium includes, but is not limited to: a compact disc read-only memory (CD-ROM), a random access memory (RAM), a floppy disk, a hard disk or a magneto-optical disk, etc.

[0114] An embodiment of the present invention further provides a computer program product, including computer instructions, which instruct a computing device to execute the data storage method in the above-mentioned multiple method embodiments.

[0115] In addition, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant regulations and standards, and corresponding operation entrances are provided for users to choose to authorize or refuse.

[0116] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present invention can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0117] The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA)). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., a random access memory (RAM), a read-only memory (ROM), a flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a dedicated computer for executing the method shown here.

[0118] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present invention.

[0119] The above implementation methods are only used to illustrate the embodiments of the present invention, and are not limitations of the embodiments of the present invention. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present invention. The patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A processing unit, configured in a local node of a network on chip, the processing unit comprising: a first index buffer, used to manage the local memory in the local node, wherein the first index buffer determines a first address allocation state when acquiring the first data from the upstream node, and when the first address allocation state indicates that there is a remaining index space that satisfies the data length of the first data, allocates an address segment of the first data in the remaining index space, and updates the first address allocation state; An address management unit, configured to manage a first address mapping relationship between a first index space of the first index buffer and a first memory space of the local memory; A memory bus unit is used to store the first data into a memory address segment in the first memory space corresponding to the address segment of the first data.

2. The processing unit according to claim 1, wherein: The processing unit further comprises an on-chip bus unit, The on-chip bus unit is used to: parse a first data packet obtained from the upstream node based on a first bus protocol between the upstream node and the upstream node to obtain the first data and its data length; The memory bus unit is used to: store the first data into a corresponding memory address segment in the first memory space based on a second bus protocol between the access memory and the memory.

3. The processing unit according to claim 1, wherein: The processing unit further comprises a data buffer, The data buffer is used to read the first data into a data buffer queue, and when the first data is dequeued from the data buffer queue, the first data is stored in a corresponding memory address segment in the first memory space through the memory bus unit.

4. The processing unit according to claim 1, wherein: The processing unit further comprises a second index buffer, The second index buffer is used to: determine a second address allocation state when the first address allocation state indicates that there is no remaining index space that satisfies the data length of the first data, and when the second address allocation state indicates that there is remaining index space that satisfies the data length of the first data, allocate an address segment of the first data in the remaining index space, and update the second address allocation state; The address management unit is further used to: manage a second address mapping relationship between a second index space of the second index buffer and a second memory space of the local memory; The memory bus unit is further used to: store the first data into a memory address segment in the second memory space corresponding to the address segment of the first data.

5. The processing unit according to claim 4, wherein: The processing unit also includes an initialization unit, which is used to: map the continuous memory space of the local memory to the first index space and the second index space, so that the first memory space in the continuous memory space corresponds to the first index space of the first index buffer, and the second memory space in the continuous memory space corresponds to the second index space.

6. The processing unit according to claim 1, wherein: The address management unit is also used to: after storing the first data in a memory address segment corresponding to the address segment of the first data in the first memory space, when the first address allocation state meets a preset memory refresh condition, create a third address mapping relationship between the third memory space and the first index space to update the first address mapping relationship.

7. The processing unit according to claim 1, wherein: The first index buffer is specifically used to: determine the allocation pointer corresponding to the end address of the currently allocated address segment based on the first address allocation status, move the allocation pointer to the corresponding address segment of the data length of the first data, perform an allocation operation on the corresponding address segment, and update the corresponding address segment to the currently allocated address segment.

8. The processing unit according to claim 7, wherein: The first index buffer is further used for updating the next allocated address segment to the current allocated address segment when the allocation pointer reaches the next allocated address segment before moving the address segment corresponding to the data length of the first data.

9. The processing unit according to claim 8, wherein: The first index buffer is also used to: when the allocation pointer reaches the next allocated address segment before moving the address segment corresponding to the data length of the first data, determine the starting address of the next allocated address segment as the ending address of the current allocated address segment.

10. The processing unit according to claim 9, wherein: The first index buffer is a circular buffer, and the end address of the first index space is continuous with the start address.

11. The processing unit according to claim 1, wherein: The first index buffer is further used for: After the first data is deleted from the memory address segment corresponding to the first memory space, the allocated address segment of the first data is released in the first index space.

12. The processing unit according to claim 11, wherein: The first index buffer is specifically used to: determine the release pointer corresponding to the end address of the last released address segment based on the first address allocation status, place the release pointer at the starting position of the allocated address segment of the first data, and move the release pointer from the starting position to the end position of the allocated address segment to release the allocated address segment.

13. A processor, comprising: A plurality of processing units, each processing unit being configured as a processing unit according to any one of claims 1-12.

14. A system on chip, comprising: The processor according to claim 13; A network on chip, wherein multiple processing units in the processor are interconnected via a network on chip.

15. A data storage method, applied to a local node of a network on chip, the method comprising: When first data is acquired from an upstream node, determining a first address allocation state of a first index buffer, wherein the first index buffer is used to manage a local memory in the local node, and a first index space of the first index buffer is configured to have a first address mapping relationship with a first memory space of the local memory; When the first address allocation state indicates that there is a remaining index space that satisfies the data length of the first data, an address segment of the first data is allocated in the remaining index space, and the first address allocation state is updated; The first data is stored in a memory address segment in the first memory space that corresponds to the address segment of the first data.

16. A processing unit, comprising: A controller, a memory, an on-chip bus interface and an internal bus, wherein the controller, the memory and the on-chip bus interface communicate with each other through the internal bus; The memory is used to store at least one executable instruction, and the executable instruction enables the controller to execute the method according to claim 15.

17. A computer storage medium having a computer program stored thereon, which, when executed by a processing unit, implements the method according to claim 15.

18. A computer program product comprising computer instructions, which implement the method of claim 15 when executed by a processing unit.

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