A SRAM-based double-bit input feature-optimized DCIM circuit

Abstract

The application discloses a double-bit input feature optimization DCIM circuit based on SRAM and belongs to the technical field of electronic circuits. The circuit comprises an input preprocessing module, an SRAM memory and computing array, a split adder tree, a result correction module and an uninterrupted accumulator, supports feature optimization of multiple groups of double-bit data, reverses low-sparse input data to improve sparsity, and corrects calculation errors generated in the subsequent correction. After sparsification, the input data is reorganized into two groups of input data with lower average reversal rate. Feature optimization can significantly improve sparsity and reduce reversal rate. The hybrid computing unit and the split adder tree embedded in each SRAM unit of the SRAM memory and computing array are used to complete the multiplication and addition operation of the reorganized input data and weights. The uninterrupted accumulator completes accumulation in the least period. The circuit aims to improve the operation energy efficiency and data throughput of the DCIM architecture for edge AI devices.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of electronic circuits, and particularly relates to a DCIM circuit based on double-bit input feature optimization of SRAM. BACKGROUND

[0002] Artificial intelligence (AI) edge devices provide significant advantages for AI tasks, including enhanced privacy, reduced latency, and increased bandwidth, but are often limited by power consumption. However, the separation of on-chip / off-chip memory and processing elements (PEs) in traditional von Neumann architecture leads to a "memory wall" bottleneck. When using a processor based on the von Neumann architecture to perform neural network model operations in AI tasks, a large number of weight parameters in the model need to be frequently transferred from the storage device to the calculation unit, which will greatly limit the energy efficiency and latency of the processor when performing such tasks. Unlike traditional von Neumann-based systems, the CIM architecture can significantly improve the throughput and energy efficiency of multiplication and addition operations, and thus is a more optimal solution for artificial intelligence edge devices.

[0003] In-memory computing (CIM) based on static random access memory (SRAM) is attracting more attention due to its high speed and high reliability. Analog in-memory computing (ACIM) based on SRAM has advantages in terms of wiring resources and energy efficiency. However, PVT (process, voltage, temperature) and signal tolerance have a great impact on the accuracy of analog CIM. In contrast, digital in-memory computing (DCIM) based on SRAM has the advantage of PVT insensitivity, and the calculation accuracy in the digital domain is higher and more stable, making it have higher calculation accuracy when facing neural network tasks. However, DCIM faces three major challenges: (1) As the input data inversion rate increases, the energy consumption of DCIM will increase significantly. (2) Large-scale adder trees for partial product summation will result in considerable energy consumption. (3) The calculation parallelism of DCIM is limited by wiring resources, resulting in low throughput.

[0004] Many works have been devoted to improving the energy efficiency of DCIM, especially the optimization of adder trees and local calculation units. For example, Chih et al. used a 14 / 28T hybrid adder tree to improve the energy efficiency by 30%. Wang et al. replaced the non-overlapping partial multiplication addition operation with a bitwise OR logic operation to improve the energy efficiency of DCIM. Guo et al. reduced the number of adders by approximating partial products to reduce the energy efficiency of DCIM. How to further reduce the energy efficiency of DCIM on the basis of the above is a problem to be solved by the present application. SUMMARY

[0005] In view of the above, the application proposes a DCIM circuit based on SRAM double-bit input feature optimization, which is oriented to edge AI computing, adopts a MAC operation mechanism with high energy efficiency and high throughput, can optimize the key features (including sparsity and inversion rate) of input data, improve the computing energy efficiency of DCIM, and relieve the limitation of DCIM on wiring resources.

[0006] In order to achieve the above purpose, the technical scheme adopted by the application is as follows:

[0007] In the first aspect, the application discloses a DCIM circuit based on SRAM double-bit input feature optimization, which is applied to the multiply-add operation of neural network input data and neural network weights.

[0008] The DCIM circuit adopts a double-bit data serial calculation model: an input preprocessing module supporting feature optimization of multiple groups of double-bit data, an SRAM storage and calculation array supporting double-bit parallel calculation and a split adder tree, a result correction module, and an uninterrupted accumulator.

[0009] The input preprocessing module includes an input data sparsification module and an input reorganization module; the input data sparsification module determines the sparsity of neural network input data through a delay mechanism, and inverts the input data with low sparsity bit by bit, keeps the input data with high sparsity unchanged, and generates an inversion flag signal; the input reorganization module reorganizes the double-bit input data processed by the input data sparsification module into left input and right input with lower average inversion rate, and generates a shift control signal.

[0010] The SRAM storage and calculation array pre-calculates and stores neural network weights and the sum of weights, and the hybrid calculation unit embedded in each SRAM unit in the SRAM storage and calculation array respectively completes the dot product of the left input, the right input and the weight, to obtain two groups of partial products; the partial products are shifted according to the shift control signal; the two groups of partial products are summed by the split adder tree divided into two, to obtain two partial sums, which are corrected by the result correction module using the sum of weights stored in the SRAM storage and calculation array, to calculate the corrected intermediate sum, and then the uninterrupted accumulator is used to complete the accumulation and output the final multiply-add result.

[0011] Preferably, the input data sparsification module comprises an input sparsity detection unit and an input inversion control unit, the input sparsity detection unit comprises an input control delay chain and a reference delay chain composed of buffer delay units; a double-bit input data is sampled, a delay controlled by the sampled input data is generated through the input control delay chain, and the size of the delay is negatively related to the number of "1"s in the sampled input data; the input control signal of the reference delay chain is set to have 50% of "1"s; if the input delay is less than the reference delay, the sparsity of the input data is lower than 50%, at this time, a corresponding input inversion flag signal P = 1 is generated, and the input data is inverted bit by bit through the input inversion control unit; otherwise, P = 0, and the input data remains unchanged.

[0012] Preferably, the input inversion control unit comprises two inverters and a 2-to-1 multiplexer, the enable signal of the multiplexer is P, and the two input signals of the multiplexer are the outputs of the two inverters; when P = 1, the logical function of the input inversion control unit is an inverter, and when P = 0, the logical function of the input inversion control unit is a buffer.

[0013] Preferably, the calculation of the input reorganization module comprises:

[0014] When IN[i+1] is a non-sign bit, INL = IN[i]&IN[i+1], INR = IN[i]|IN[i+1], the original input data is reorganized into more sparse left input INL and more dense right input INR; wherein the bit weight of INL is 2, and the bit weight of INR is 1; and when IN[i] = 0, IN[i+1] = 1, the input reorganization module generates a shift signal SHIFT = 1, otherwise SHIFT = 0.

[0015] When IN[i+1] is a sign bit, INR = IN[i]|IN[i+1]; wherein the bit weight of INL is 2, and the bit weight of INR is -1.

[0016] Preferably, the hybrid computing unit embedded in each SRAM cell in the SRAM computing array comprises two independent computing modules for calculating the dot product of the left input and the weight and the dot product of the right input and the weight, respectively, to obtain two groups of partial products.

[0017] The computing module for processing the left input is a 3T structure based on transmission logic, comprising a transmission gate and a grounded NMOS tube, the transmission gate is opened when the neural network weight is 1, and the input data is transmitted to the split adder tree; the transmission gate is closed when the neural network weight is 0, the NMOS tube is opened, and the output signal is 0.

[0018] The calculation module for processing the right input is a NOR logic gate, and the calculation of the right input INR is shown in the following formula The calculation of the right input INR is shown in the following formula i The point multiplication of the weight w i .

[0019] Preferably, the split adder tree is located on the two sides of the SRAM memory and calculation array respectively, including a left adder tree and a right adder tree, and two groups of partial products output by the SRAM memory and calculation array are connected to the left adder tree and the right adder tree in a cross-wiring manner.

[0020] Preferably, the calculation of the result correction module includes:

[0021] (1) The right partial sum generated by the sign bit of the input data is corrected: when the bit weight of the right input is -1, the right partial sum generated by the right input is taken negative after being summed by the split adder tree to obtain the right partial sum after sign bit correction; when the bit weight of the right input is not -1, the right partial sum does not need to be corrected;

[0022] (2) The left partial sum is left shifted by one bit and then added to the corrected right partial sum to obtain an intermediate sum;

[0023] (3) When the input inversion flag signal P=1, it is judged whether the double-bit input data contains a sign bit, if yes, the final intermediate sum result is obtained by selecting the sum of the weights in the negative SRAM memory and calculation array minus the intermediate sum; if not, the final intermediate sum result is obtained by selecting the sum of the weights in the 3 times SRAM memory and calculation array minus the intermediate sum;

[0024] When the input inversion flag signal P=0, the intermediate sum does not need to be corrected;

[0025] (4) The final intermediate sum is output as the output result of the result correction module.

[0026] Preferably, the sum of the weights in the 3 times SRAM memory and calculation array and the sum of the weights in the negative SRAM memory and calculation array are pre-calculated and stored in the SRAM memory and calculation array.

[0027] Preferably, the uninterrupted accumulator accumulates the intermediate sum output by the result correction module; when the double-bit input data is the highest bit and the second highest bit of a certain round of multi-bit input data, at the next clock rising edge, the accumulator outputs the accumulated result of the last round of multi-bit input data and sets the intermediate accumulated result to zero; the initial accumulation of the intermediate sum of the highest bit and the second highest bit of the current input is completed in the next clock cycle.

[0028] In the second aspect, the application discloses a high-parallel double-bit multiplication and addition calculation method based on the DCIM circuit, including the following steps:

[0029] 1) In the weight write mode, multiple sets of multi-bit weights are written into the SRAM memory-computing array column by column, and the sum of 3 times the weight and the sum of the negative weight are written into the additional SRAM cells of the SRAM memory-computing array;

[0030] 2) In the calculation mode, the input data is input in the highest bit first and double-bit serial input mode, and the input preprocessing module detects the sparsity of a set of multiple double-bit input data. If the sparsity is higher than 50%, the original input data is reversed, and the reversal flag signal P is set to 1, otherwise P is set to 0. Then, the input data is reorganized into left input and right input, and the shift control signal corresponding to the right input is generated;

[0031] 3) The hybrid computing unit embedded in each SRAM cell in the SRAM memory-computing array calculates two sets of partial products corresponding to the left input and the right input respectively, and performs a shift operation on the non-partial product corresponding to the right input according to the shift control signal, and then sums up by the left adder tree and the right adder tree respectively to obtain the left partial sum and the right partial sum;

[0032] 4) The result correction module calculates two-step correction:

[0033] The first step is to take the negative of the right partial sum when the bit weight of the right input is -1, and the right partial sum does not need to be corrected when the bit weight of the right input is not -1;

[0034] The left partial sum is left shifted by one bit and then added to the corrected right partial sum to obtain the intermediate sum;

[0035] The second step is to calculate the final intermediate sum result according to the reversal flag signal P:

[0036] When the double-bit input data contains a sign bit, PS2 = -P∑w i +(1-2P)PS1;

[0037] When the double-bit input data does not contain a sign bit, PS2 = 3P∑w i +(1-2P)PS1;

[0038] Where PS1 is the intermediate sum, ∑w i is the sum of the neural network weights, and PS2 is the corrected intermediate sum;

[0039] 5) The uninterrupted accumulator accumulates the intermediate sum PS2 calculated by the multi-bit input data, and outputs the multiplication result of the last round of multi-bit input data and the neural network weight on the next clock rising edge after the highest bit and the second highest bit of the next round of multi-bit input data are input into the DCIM circuit.

[0040] Compared with the prior art, the application has the beneficial effects of:

[0041] The DCIM operation throughput is significantly improved by adopting a double-bit data parallel computing mode and using an uninterrupted accumulator; the input data sparsity is increased and the input data inversion rate is significantly reduced by optimizing the characteristics of the input data, including sparsification processing and reorganization, thereby significantly improving the energy efficiency of the DCIM multiplication and addition operation; the application has significant advantages in computing energy efficiency and throughput, and can better adapt to the low-power high-parallelism operation needs of edge AI devices. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The application provides a circuit architecture schematic diagram of a DCIM macro circuit.

[0043] Figure 2 The application provides a principle schematic diagram of input data sparsification and reorganization.

[0044] Figure 3 The application provides a circuit schematic diagram of an IPM.

[0045] Figure 4 The application provides a schematic diagram of a SAT circuit and a HSCU circuit structure and a PSUM correction process.

[0046] Figure 5 The application provides a circuit structure of an uninterrupted accumulator and a working waveform schematic diagram. DETAILED DESCRIPTION

[0047] The application will be further described and illustrated in conjunction with the specific embodiments. The embodiments are only exemplary and do not limit the scope of the disclosure. The technical features of each embodiment in the application can be combined accordingly without conflict.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the application belongs. The terms used herein are only for the purpose of describing the application and are not intended to limit the application.

[0049] The application will be further described and illustrated in conjunction with the specific embodiments.

[0050] The DCIM circuit of the application has a plurality of identical CIM arrays. Figure 1As shown, in an optional embodiment of the present application, the DCIM circuit of the present application comprises an input preprocessing module (IPM), 32 CIM arrays, a clock control module, a word line (WL) decoder, a bit line (BL) driver, an input output cache SRAM and an input output serial port (SPI). Each CIM array contains 256x4 hybrid SRAM computing-in-memory units (HSCU), a split adder tree (SAT), a result correction model (RCM), an uninterrupted accumulator and 7x4 SRAM units storing the sum of weights. The SAT comprises two split sub-adder trees (ATL and ATR). The word line decoder and the bit line driver control the neural network weight write-in and read-out of the SRAM array, the input SPI writes the serial input neural network input data into the input cache SRAM in parallel, the calculation output is written into the output cache SRAM in parallel, the output SPI serially outputs the calculation result read from the output cache SRAM in parallel, and the clock control module generates a control clock signal for SRAM read-write using an external clock signal. The DCIM circuit of the present application is applied to the multiplication and addition operation of neural network input data and neural network weights, and the weights stored in the SRAM unit are the neural network weights.

[0051] In the calculation mode, 256 groups of double-bit input data are delivered by the input buffer SRAM to the input pre-processing module for sparsification and reorganization, and the low-sparsity input data is bit-inverted and further converted into the left input (INL) and the right input (INR) with lower average inversion rate. The HSCU includes two independent calculation modules for calculating the dot product of INL and weight and the dot product of INR and weight respectively, and two groups of independent partial products are generated after the calculation. The partial product generated by INR is shifted under the control of the shift signal SHIFT of the input reorganization module. When SHIFT = 1, the partial product generated by INR is controlled to be shifted to the left by one bit, and when SHIFT = 0, no shift is needed. Two sub-adder trees, the left adder tree (ATL) and the right adder tree (ATR), sum the two groups of partial products respectively, and output two partial sums (PSUM) to the RCM; the RCM corrects the sign bit of the PSUM generated by ATR and shifts the PSUM generated by ATL to the left by one bit, and then adds the two processed PSUMs to obtain the intermediate PSUM. Finally, the RCM corrects the calculation error caused by input inversion under the control of the input inversion flag signal P, using the sum of weights (3 times the sum of weights in the SRAM storage and calculation array 3∑w i or the sum of weights in the negative SRAM storage and calculation array -∑w i ) of the SRAM storage and calculation array. The sum of weights in the 3 times SRAM storage and calculation array and the sum of weights in the negative SRAM storage and calculation array are calculated in advance and written into the SRAM storage and calculation array when the weight is written, and can be used at any time during the calculation process.

[0052] In an optional embodiment of the present application, the input data sparsification and reorganization principle is as shown in Figure 2 The input data sparsification principle is as follows:

[0053] A group of low-sparsity original input can be converted into a group of full "1" input and inverted input difference; and the multiplication and addition result of the full "1" input and the weight is the sum of weights, so the multiplication and addition result of the inverted input and the weight can be calculated first, and then the sum of weights minus the result can obtain the multiplication and addition result of the original input and the weight. For the non-sign bit of the double-bit input, the sum of weights should be adjusted to 3 times the sum of weights; for the double-bit input containing the sign bit, the negative sum of weights should be used.

[0054] The input recombination principle is as follows: The input recombination module reassembles the original input data into INL and INR through logical operations INL = IN[i] & IN[i+1] and INR = IN[i] | IN[i+1]. The bit weight of INL is 2, and the bit weight of INR is 1. In the bit-serial input mode, standardizing the sparsity characteristics of INL and INR can significantly reduce the average inversion rate of the two sets of inputs. Simultaneously, the relationship between the input inversion rate and DCIM power consumption is logarithmic; therefore, reducing the inversion rate has a significant effect on reducing power consumption. Furthermore, to ensure the accuracy of the calculation after input recombination, when IN[i] = 0 and IN[i+1] = 1, the original input data is 2, while the recombined data is 1. Therefore, the input recombination module generates a shift signal SHIFT = 1 to control the partial product generated by the corresponding INR to shift one bit to the left. This shifting process can be implemented in the shift controller. When IN[i+1] is the sign bit, the encoding method of INL is changed to... In this context, INL has a bit weight of 2, and INR has a bit weight of -1. The & symbol represents the AND operation: the result is 1 only when both bits are 1; the | symbol represents the OR operation: the result is 0 only when both bits are 0.

[0055] In an optional embodiment of the present invention, the circuit structure of the IPM is as follows: Figure 3 As shown, the system includes an input sparsity module and an input recombination module. The input sparsity module includes an input sparsity detection unit and an input inversion control unit. The input sparsity detection unit includes an input control delay link composed of buffer delay units and a reference delay link, which uses timing information to detect whether the sparsity of the input data exceeds a set threshold. Each delay unit on the delay link is controlled by a sampled portion of the input data. The delay chain composed of adjustable buffer delay units has different delays under the control of different input signals; the total delay of the continuously inverted signal DEN in the delay link is negatively correlated with the "1"s in the control data. The delay controlled by the input data is obtained by controlling each delay unit on the delay link with 32-bit input data sampled from the input data. The control signal in the delay link providing the reference delay has 50% "1"s (DEF0, DEF1, ... DEF...). 30 DEF 31 =1,0…1,0). By comparing the magnitudes of the two delays, it can be determined whether the input data delay exceeds the set threshold (50%). When the sparsity of the input data is less than 50%, the inversion control signal P is set to 1, and the input inversion control unit completes the inversion of the input data. As shown in the operation waveform, when the sparsity of the sampled 32-bit input data is greater than 50%, the output signal DREF of the 32nd delay unit in the reference delay link is used. 31 It will be compared to the output signal DOUT of the 32nd delay unit in the input control delay link.31 If P0 is pulled high earlier, the output signal P0 of the input control delay link will be fixed at 0. Conversely, if P0 is pulled high, the output signal PB0 of the reference delay link will be fixed at 0. The enable signal of the output latch is (P0|PB0)&DEN, ensuring that P does not change before the next set of valid input signals arrives.

[0056] The input inversion control unit includes two inverters (two inverters in series) and a 2-to-1 multiplexer. The multiplexer's selection signal is P, and its two input signals are the outputs of the two inverters. When P = 1, the input inversion control unit functions as an inverter; when P = 0, it functions as a buffer. Therefore, when P is 1, the inversion control unit inverts the input data; otherwise, the input data remains unchanged. Finally, the reconstruction module uses AND and OR gates to reconstruct the input data: INL = IN[i] & IN[i+1], INR = IN[i] | IN[i+1], for the sign bit... Simultaneously, the shift control signal SHIFT is output.

[0057] In an optional embodiment of the present invention, the SAT circuit and HSCU circuit structure and the PSUM correction process are as follows: Figure 4 As shown. The HSCU embeds two independent computation modules within an SRAM cell, used to calculate the dot product of the left input and weights, and the right input and weights, respectively, to obtain two sets of partial products. The computation module for processing the left input INL is a 3T structure based on transmission logic, containing a transmission gate and a grounded NMOS transistor. The transmission gate is turned on when the weight is 1, transmitting the input data to the split adder tree; when the weight is 0, the transmission gate is turned off, the NMOS transistor is turned on, and the output signal is 0, to reduce power consumption and area overhead without sacrificing voltage. The computation module for processing the right input INR uses a NOR logic gate, calculated using the formula... Calculate input INR i With weight w i The dot product is used to ensure the driving shift logic.

[0058] The adder tree is divided into two sub-adder trees, ATL and ATR. Both adder trees use 28T and 14T full adders interleaved to reduce power consumption. The partial product generated by INL is summed by ATL, while the partial product generated by INR is summed by ATR, resulting in two partial sums. Since INL and INR have different sparsity and inversion rates, calculating their partial products separately can reduce the energy consumption of the adder tree. The partial product generated by INR is shifted by the shift controller under the control of the shift control signal SHIFT.

[0059] The reversed two-bit input data completes the multiplication and addition operation with the weight to generate an intermediate PSUM. The intermediate PSUM is corrected by the sum of the weights pre-calculated and written into the SRAM array to obtain the accurate multiplication and addition result. For the two-bit input data containing the sign bit, the intermediate PSUM is subtracted by the sum of the negative weights; for the two-bit input data not containing the sign bit, the intermediate PSUM is subtracted by the sum of the weights multiplied by 3.

[0060] Specifically, for the sign bit of the input data (the bit weight of INR is -1), the PSUM calculated by the ATR is first converted into its opposite number in the result correction module, and then added to the shifted PSUM of the ATL to obtain the intermediate sum PSUM, denoted as PS1. Finally, the result correction module RCM obtains the accurate final sum PSUM, denoted as PS2, through the following formula under the control of the sign bit flag signal (Sign):

[0061] PS2 = -P∑w i +(1-2P)PS1

[0062] wherein P is the value of the inversion flag signal P of the input data sparsification module;

[0063] For the remaining non-sign bits of the input data (the bit weight of INR is not -1), the PSUM calculated by the ATR is directly added to the shifted PSUM of the ATL to obtain the intermediate sum PSUM, denoted as PS1. Finally, the result correction module RCM obtains the accurate final sum PSUM, denoted as PS2, through the following formula under the control of the sign bit flag signal (Sign):

[0064] PS2 = 3P∑w i +(1-2P)PS1

[0065] If P is 0, the input data is not inverted, and the PSUM does not need to be corrected by the sum of the weights.

[0066] In an optional embodiment of the present application, the uninterrupted accumulator circuit structure is as follows: Figure 5The accumulator accumulates the PS2 calculated from the multi-bit input data without interruption. First, the accumulator extends the sign bit of the input PS2. When the input double-bit data is the most significant bit (MSB) and the second most significant bit (MSB-1) of a round of multi-bit input data, the calculation completion signal is pulled high. At the next clock rising edge, the accumulator outputs the accumulation result of the last round of multi-bit input data and resets the intermediate accumulation result to zero. In the next clock cycle, the initial accumulation of the PSUM of the current input MSB and MSB-1 data is completed, so, unlike the existing accumulator, after the accumulation of the PSUM result of a round of input data is completed, the accumulator does not need an additional cycle to output the last round of calculation result and reset the intermediate accumulation state. In an optional embodiment of the present application, the CIM array supports 4-bit or 8-bit weight mode, as shown in the figure; in the 4-bit weight mode, the accumulator directly outputs the calculation result after the calculation is completed; in the 8-bit weight mode, the calculation results of the two CIM arrays are shifted and added to obtain the multiplication and addition result in the 8-bit weight mode. Figure 4

[0067] The steps of the parallel calculation method of the double-bit input data stream using the high-energy-efficiency DCIM circuit are as follows:

[0068] 1) A plurality of groups of double-bit data are input from the input buffer SRAM to the IPM for sparse processing, and the processed data are recombined into INL and INR;

[0069] 2) INL and INR are simultaneously input to the HSCU, the point multiplication of INL and the weight is completed based on the 3T calculation module of the transmission gate and the grounded NMOS, and the point multiplication of INR and the weight is completed based on the calculation module of the NOR logic gate; two independent partial products are generated; for the partial product generated by INR, a shift operation is performed according to the shift control signal, and the shift operation is not needed when SHIFT=0.

[0070] 3) The split adder tree located on both sides of the SRAM computing array sums the plurality of groups of partial products generated by INL and the plurality of groups of partial products generated by INR; two independent partial sums, including PSUML and PSUMR, are generated;

[0071] 4) After the RCM corrects the sign bit of PSUMR, PSUML is shifted one bit to the left and added to PSUMR to obtain the intermediate PSUM; then, under the control of the input inversion flag signal P, the intermediate PSUM is corrected using the sum of the weights to obtain the accurate multiplication and addition result;

[0072] ​5) The non-interleaved accumulator accumulates the accurate product-sum result of the multi-bit input data. The next round of the highest bit and the next highest bit of the multi-bit input data are input to the DCIM macro, and at the next clock rising edge, the accumulator outputs the accumulated result of the last round of the multi-bit input data and sets the intermediate accumulated result to zero. The initial accumulation of the PSUM of the highest bit and the next highest bit of the current input is completed in the following clock cycle.

[0073] The foregoing description of the disclosed embodiments enables any person skilled in the art to practice or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit and scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DCIM circuit based on SRAM with dual-bit input feature optimization, wherein the DCIM circuit is applied to the multiply-accumulate operation of neural network input data and neural network weights; Its features are, The DCIM circuit adopts a two-bit data serial computing model: it has an input preprocessing module that supports feature optimization of multiple sets of two-bit data, an SRAM storage array and split adder tree that support two-bit parallel computing, a result correction module, and an uninterrupted accumulator. The input preprocessing module includes an input data sparsification module and an input reconstruction module; The input data sparsification module determines the sparsity of the neural network input data through a delay mechanism, inverts the low-sparse input data bit by bit, leaves the high-sparse input data unchanged, and generates an inversion flag signal; the input recombination module reassembles the two-bit input data processed by the input data sparsification module into left and right inputs with lower average inversion rates, and generates a shift control signal. The SRAM storage array pre-calculates and stores neural network weights and the sum of weights. The hybrid computing unit embedded in each SRAM cell of the SRAM storage array performs dot product of the left input, right input and weights respectively to obtain two sets of partial products. The partial products are shifted according to the shift control signal. The two sets of partial products are summed by a split adder tree that is divided into two parts to obtain two partial sums. The result correction module uses the sum of weights stored in the SRAM storage array to correct the result, calculates the corrected intermediate sum, and then the uninterrupted accumulator completes the accumulation and outputs the final multiplication result.

2. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 1, characterized in that, The input data sparsity module includes an input sparsity detection unit and an input inversion control unit. The input sparsity detection unit includes an input control delay link composed of buffer delay units and a reference delay link. For sampling two-bit input data, a delay controlled by the sampled input data is generated through the input control delay link. The magnitude of the delay is negatively correlated with the number of "1"s in the sampled input data. The input control signal of the reference delay link is set to have 50% "1"s. If the input delay is less than the reference delay, the sparsity of the input data is less than 50%, and a corresponding input inversion flag signal P=1 is generated. The input data is then inverted bit by bit through the input inversion control unit. Otherwise, P=0, and the input data remains unchanged.

3. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 2, characterized in that, The input inversion control unit includes two stages of inverters and a 2-to-1 multiplexer. The selection signal of the multiplexer is P, and the two input signals of the multiplexer are the outputs of the two stages of inverters. When P=1, the logic function of the input inversion control unit is an inverter, and when P=0, the logic function of the input inversion control unit is a buffer.

4. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 1, characterized in that, The calculations of the input recombination module include: When IN[i+1] is a non-sign bit, INL = IN[i] & IN[i+1], INR = IN[i] | IN[i+1], reorganizing the original input data into a sparser left input INL and a denser right input INR; where the bit weight of INL is 2 and the bit weight of INR is 1; and when IN[i] = 0 and IN[i+1] = 1, the input reorganization module generates a shift signal SHIFT = 1, and in other cases SHIFT = 0; When IN[i+1] is the sign bit INR = IN[i]|IN[i+1]; where INL has a bit weight of 2 and INR has a bit weight of -1.

5. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 1, characterized in that, The hybrid computing unit embedded in each SRAM cell of the SRAM storage array includes two independent computing modules, which are used to calculate the dot product of the left input and the weight, and the dot product of the right input and the weight, respectively, to obtain two sets of partial products. The computation module for processing the left input is a 3T structure based on transmission logic, which includes a transmission gate and a grounded NMOS transistor. The transmission gate is turned on when the neural network weight is 1, transmitting the input data to the split adder tree; the transmission gate is turned off when the neural network weight is 0, the NMOS transistor is turned on, and the output signal is 0. The calculation module used to process the input on the right is a NOR logic gate, which is calculated using the formula... Calculate the input INR on the right. i With weight w i The dot product.

6. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 5, characterized in that, The split adder trees are located on both sides of the SRAM in-memory array, including a left adder tree and a right adder tree. The two sets of partial products output by the SRAM in-memory array are connected to the left adder tree and the right adder tree by a cross-wiring method.

7. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 1, characterized in that, The calculations of the result correction module include: (1) The right-hand part of the input data is generated and the sign bit is corrected: When the bit weight of the right input is -1, the right-hand part of the partial product generated by the right input is negative after being summed by the split adder tree to obtain the right-hand part of the data after the sign bit is corrected; when the bit weight of the right input is not -1, the right-hand part of the data does not need to be corrected. (2) Shift the left part one position to the left and add it to the corrected right part to get the middle sum; (3) When the input inversion flag signal P=1, determine whether the two-bit input data contains a sign bit. If yes, subtract the intermediate sum from the sum of weights in the negative SRAM storage array to obtain the final intermediate sum result; if no, subtract the intermediate sum from the sum of weights in the SRAM storage array three times to obtain the final intermediate sum result. When the input inversion flag signal P=0, no intermediate sum needs to be corrected; (4) Output the final intermediate sum as the output of the result correction module.

8. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 7, characterized in that, The sum of weights in the 3x SRAM array and the sum of weights in the negative SRAM array are pre-calculated and stored in the SRAM array.

9. The DCIM circuit based on SRAM dual-bit input feature optimization according to claim 1, characterized in that, The uninterrupted accumulator accumulates the intermediate sum output by the result correction module; when the two-bit input data is the most significant and second most significant bits of a round of multi-bit input data, at the next rising edge of the clock, the accumulator outputs the accumulated result of the previous round of multi-bit input data and sets the intermediate accumulated result to zero; the initial accumulation of the intermediate sum of the most significant and second most significant bits of the current input data is completed in the next clock cycle.

10. A highly parallel two-bit multiply-accumulate calculation method based on the DCIM circuit according to any one of claims 1-9, characterized in that, Includes the following steps: 1) In weighted writing mode, multiple sets of multi-bit weights are written to the SRAM storage array column by column. At the same time, the pre-calculated sum of 3 times the weight and the sum of the negative weights are written to the SRAM cells attached to the SRAM storage array. 2) In the calculation mode, the input data is input in the manner of most significant bit priority and double-bit serial input. The input preprocessing module detects the sparsity of a set of input data containing multiple double-bit data. If the sparsity is higher than 50%, the original input data is reversed and the reverse flag signal P is set to 1; otherwise, P is set to 0. The input data is then reassembled into left and right inputs, and a shift control signal corresponding to the right input is generated. 3) The hybrid computing unit embedded in each SRAM cell of the SRAM memory array calculates the two sets of partial products corresponding to the left input and the right input respectively. According to the shift control signal, the non-partial product corresponding to the right input is shifted. Then, the left and right partial sums are obtained by summing the left and right adder trees respectively. 4) The result correction module calculates two-step corrections: The first step is to negate the sum of the right-hand side when the bit weight of the input on the right is -1; when the bit weight of the input on the right is not -1, the sum of the right-hand side does not need to be corrected. After shifting the left part one position to the left, add it to the corrected right part to get the middle sum; The second step is to calculate the final intermediate sum based on the inversion flag signal P: When the two-bit input data includes the sign bit, PS2 = -P∑w i +(1-2P)PS1; When the two-bit input data does not include a sign bit, PS2 = 3PΣw i +(1-2P)PS1; Where PS1 is the intermediate sum, ∑w i It is the sum of the neural network weights, and PS2 is the corrected intermediate sum; 5) The uninterrupted accumulator accumulates the intermediate and PS2 calculated from the multi-bit input data. After the most significant and second most significant bits of the next round of multi-bit input data are input into the DCIM circuit, the accumulator outputs the result of multiplying and adding the previous round of multi-bit input data and the neural network weights at the rising edge of the clock cycle.

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