Long frame fast convolution system based on FPGA

Abstract

The invention discloses a long-frame fast convolution system based on FPGA, and relates to the field of signal processing technology. The system comprises the following components: a parallel processing architecture design module, a data framing and rate optimization module, a data preprocessing zero-filling module, a frequency domain calculation processing module, and a result processing and output optimization module. The invention realizes long-frame convolution in the frequency domain, thereby significantly reducing the amount of calculation, especially when using 2-base FFT to perform fast Fourier transform, the amount of calculation of multiplication and addition is greatly reduced, which not only greatly improves the calculation efficiency, but also effectively reduces the resource usage scale of FPGA through parallel calculation and optimized algorithm structure, thereby reducing hardware costs, and has significant advantages in processing large-scale data, and can complete convolution operations more quickly and accurately.

Description

Technical Field

[0001] The invention relates to the technical field of signal processing, and in particular to a long-frame fast convolution system based on FPGA. Background Art

[0002] Signal processing technology plays a vital role in modern communications, data analysis, system control and other fields. Especially in application scenarios such as laser communication, audio processing, and image processing, convolution operations, as a basic signal processing technology, are widely used in tasks such as signal filtering, feature extraction, and pattern recognition. With the development of technology, these application scenarios have put forward higher and higher requirements on the real-time and accuracy of signal processing. Field Programmable Gate Array (FPGA), as a high-performance, programmable hardware platform, has become an ideal choice for achieving efficient signal processing with its advantages of parallel processing and pipeline computing.

[0003] Traditional convolution implementation methods are mostly based on direct calculation in the time domain. This method has significant defects when processing long-frame signals. First, time-domain convolution requires the storage of a large amount of signal data, which poses a severe challenge to the memory resources of FPGA. Second, since long-frame signals contain a large number of points, direct calculation will result in a long processing delay and cannot meet real-time requirements. In addition, when the input data stream rate is high, the operating frequency limitation of the FPGA makes it difficult to perform convolution operations directly in the time domain, which not only increases the complexity of hardware design, but also may cause data loss or processing errors. Therefore, traditional time-domain convolution methods are unable to cope with high-speed, long-frame signals and cannot meet the needs of modern signal processing applications.

[0004] In view of the above problems, it is necessary to optimize the existing FPGA-based long-frame fast convolution system. By utilizing the parallel computing and pipeline computing characteristics of FPGA, combining the mathematical equivalence of time domain convolution and frequency domain filtering, through parallel processing architecture design, data framing and rate optimization, data preprocessing innovative zero padding, precise processing of frequency domain calculation, and result processing and output optimization technology, an efficient and stable long-frame convolution function is achieved. Therefore, it is of great significance to develop an FPGA-based long-frame fast convolution system that can comprehensively realize the above characteristics. Summary of the invention

[0005] The purpose of the present invention is to make up for the shortcomings of the prior art and provide a long-frame fast convolution system based on FPGA. It can realize intelligent rate adaptation and precise data framing of data streams by utilizing the parallel processing and pipeline computing characteristics of FPGA and the mathematical equivalence of time-domain convolution and frequency-domain filtering, and by building a dynamic parallel branch control architecture, so as to ensure that data can enter FPGA for processing efficiently and orderly. In the data preprocessing stage, an adaptive zero-padding optimization strategy is adopted to meet the requirements of FFT calculation and optimize the subsequent frequency domain transformation performance. In the frequency domain calculation process, an efficient FFT transformation process and error compensation multiplication operation are used to improve the calculation accuracy and efficiency. Finally, the processed data is optimized through an adaptive result truncation algorithm and an innovative result combination strategy to obtain the final convolution result. The implementation of the present invention not only greatly improves the calculation efficiency and the utilization rate of hardware resources, but also enhances the adaptability and stability of the system, and provides strong technical support for modern signal processing applications.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: a long frame fast convolution system based on FPGA, the system comprises the following components: a parallel processing architecture design module, a data framing and rate optimization module, a data preprocessing zero padding module, a frequency domain calculation processing module and a result processing and output optimization module;

[0007] The parallel processing architecture design module continuously monitors the data stream input speed and the FPGA operating speed, determines the number of parallel branches according to the speed difference between the two, and sets a speed fluctuation threshold, and re-evaluates and adjusts the number of parallel branches within a set time range when the data stream input speed fluctuation exceeds the threshold, thereby adjusting the data stream input speed;

[0008] The data framing and rate optimization module cuts the continuous data stream into frame signals of fixed length according to the FFT calculation requirements and the length of the relevant signal, and distributes them to each parallel frequency domain filtering channel in an orderly manner. By comprehensively considering the frame signal length, the number of parallel branches and the adjusted data stream rate, the data processing time of each frequency domain filtering channel is calculated, and then the adjusted data stream rate is evenly distributed to each channel.

[0009] The data preprocessing zero-padding module predicts the number of zero-padding for the cut frame signal based on the signal type, historical data processing experience, and the difference between the frame signal length and the number of points required by FFT. According to the prediction result, the zero-padding mode is selected and the original frame signal is padded with zeros. Before the data enters the FPGA for convolution processing, the data is encoded, thereby detecting and correcting errors in the transmission process and reducing the amount of transmitted data.

[0010] The frequency domain calculation processing module adopts an FFT transformation function with a pipeline structure to convert the input signal from the time domain to the frequency domain. For a specific signal, an FFT transformation is performed according to a set sampling point length to convert it to the frequency domain. When the input signal is multiplied by the frequency domain result of the specific signal, the system status is monitored in real time, and an error compensation factor is calculated according to the relative change of the frequency domain results before and after, and the multiplication result is dynamically compensated. After completing the frequency domain calculation, the encoded data is decoded, and whether an error occurs in the data during the processing according to the check bit, and the erroneous data is corrected or marked. At the same time, considering that different modules have different requirements for data formats, the data is converted into code before it is output, so that the data can be transmitted smoothly and processed correctly;

[0011] The result processing and output optimization module dynamically adjusts the truncation length of the result after inverse FFT transformation in real time according to application demand information and signal processing feedback information, and takes out the processed data from each parallel frequency domain filtering channel, adopts a multi-threaded parallel combination algorithm, and optimizes the combination order according to the importance and urgency of the data, so as to obtain the final convolution result.

[0012] Furthermore, in the parallel processing architecture design step, the data stream input speed and the FPGA operating speed are continuously monitored, and the number of parallel branches is determined according to the speed difference between the two. The formula for determining the number of branches is: in, is the updated number of parallel branches, is the current number of parallel branches, is the data stream input speed, is the FPGA operating speed, is the adjustment factor, is the proportionality coefficient.

[0013] Furthermore, in the parallel processing architecture design step, when the data stream input speed fluctuation exceeds the threshold, the number of parallel branches is re-evaluated and adjusted within a set time range, thereby adjusting the data stream input speed, and the data stream input speed adjustment formula is: ,in, is the adjusted data flow rate, is the raw rate of the input data stream, is the number of parallel branches, is the buffer capacity, is the rate adjustment influence coefficient.

[0014] Furthermore, in the data framing and rate optimization step, the continuous data stream is cut into frame signals of fixed length according to the FFT calculation requirements and the length of the related signal, and the length determination formula is: , among which, from Indicates the length of each frame signal, is the basic number of data points required for FFT calculation, is a length parameter related to signal characteristics, is an empirical coefficient used to fine-tune the frame length according to signal characteristics.

[0015] Furthermore, in the data framing and rate optimization step, the time for each frequency domain filtering channel to process data is calculated by comprehensively considering the frame signal length, the number of parallel branches and the adjusted data flow rate. The calculation formula is: ,in, Indicates at time The time for each frequency domain filter channel to process data, is the number of parallel branches, is the adjusted data flow rate.

[0016] Furthermore, in the data preprocessing zero-filling step, for the cut frame signal, the number of zero-filling is predicted based on the signal type, historical data processing experience, and the difference between the frame signal length and the number of points required for FFT. The prediction formula is: = + ,in Indicates the number of zeros that need to be filled. Indicates the signal type. Represents historical data processing experience information, is the length of the current frame signal, and is the weighting coefficient, It is the first in historical data processing experience The weights associated with each feature, It is based on the signal type and historical processing experience. The function of feature calculation, is satisfied The smallest integer.

[0017] Furthermore, in the frequency domain calculation processing step, for the input signal, a pipeline structure FFT transformation function is used to transform it from the time domain to the frequency domain, and its function formula is: ,in Indicates at time The frequency domain result of the input signal after pipeline FFT transformation, It is at the moment The input signal after zero padding, It represents the FFT transform function using pipeline structure. For a specific signal, FFT transform is performed according to the set sampling point length to convert it into the frequency domain. The formula is: ,in, It indicates the frequency domain result after FFT transformation of a specific signal. It is a specific signal. is the sampling point length of the FFT transform of a specific signal, It is a function that performs FFT transformation on a specific signal.

[0018] Furthermore, in the frequency domain calculation processing step, when the input signal is multiplied by the frequency domain result of the specific signal, the system state is monitored in real time, and the error compensation factor is calculated according to the relative change of the frequency domain results before and after, and the multiplication result is dynamically compensated. Specifically, when multiplying in the frequency domain, the formula is used Perform dynamic compensation, where represents the frequency domain result after multiplication and error compensation, and are the frequency domain results of the input signal and the specific signal respectively, It depends on the time The error compensation factor is calculated based on the system state, and its calculation formula is: , in, It is at the moment The error compensation factor is and Separate moments and The frequency domain result of the input signal elements, and Separate moments and The frequency domain result of a specific signal elements, is the error adjustment coefficient, is the length of the frequency domain signal.

[0019] Furthermore, in the result processing and output optimization step, the truncation length is dynamically adjusted in real time according to the application requirement information and the signal processing feedback information, and the adjustment formula is: Determine the cutoff length, where Indicates at time The cut-off length of is the base value of the cutoff length, is the adjustment coefficient, It is at the moment Application requirements information, It is at the moment The feedback information of signal processing, Is the starting time to start considering truncation adjustments.

[0020] Furthermore, in the result processing and output optimization step, a multi-threaded parallel combination algorithm is used, and the combination order is optimized according to the importance and urgency of the data, so as to obtain the final convolution result. Specifically, the formula is used Combine the final results, where represents the final convolution result, It is at the moment From The data extracted from the parallel frequency domain filtering channels is It is the importance and urgency of the data. It is at the moment No. The weight of the channel data, It is a multi-threaded parallel combination function.

[0021] Compared with the existing technology, the FPGA-based long-frame fast convolution system has the following beneficial effects:

[0022] 1. The present invention significantly reduces the amount of calculation by realizing long frame convolution in the frequency domain. In particular, when using 2-base FFT for fast Fourier transform, the amount of multiplication and addition calculations is greatly reduced, which not only greatly improves the calculation efficiency, but also effectively reduces the resource usage scale of FPGA through parallel calculation and optimized algorithm structure, thereby reducing hardware costs. It has significant advantages in processing large-scale data and can complete convolution operations more quickly and accurately. In addition, the present invention incorporates encoding, decoding and code conversion technologies, which significantly expands the data processing capability and compatibility of the system.

[0023] 2. The present invention significantly enhances the adaptability of the system by introducing a dynamic parallel branch adjustment mechanism, an adaptive zero-padding mode and an adaptive result truncation algorithm technology, so that it can better cope with the challenges of data rate fluctuations, different signal types and application scenarios. In addition, the error compensation mechanism of frequency domain data multiplication improves the accuracy of the multiplication result, and the innovative result combination algorithm improves the data combination efficiency and the timeliness of the final result, further optimizing the output performance.

[0024] Other advantages, objectives and features of the present invention will be set forth in part in the following description and, in part, will be apparent to those skilled in the art based on an examination of the following or may be taught from the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 This is the process operation diagram of the long frame fast convolution system based on FPGA;

[0027] Figure 2 This is the algorithm structure framework diagram of the long frame fast convolution system based on FPGA;

[0028] Figure 3 This is the data flow timing diagram of the FPGA-based long-frame fast convolution system. DETAILED DESCRIPTION

[0029] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation mode, structure, characteristics and effects of the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments.

[0030] Embodiment 1

[0031] In high-speed laser communication systems, the signal transmission rate can reach several gigabits per second or even higher, and the amount of data is extremely large, which places strict requirements on the real-time and accuracy of signal processing. First, the high-speed data stream input speed in laser communication and the FPGA working speed are monitored and compared in real time. Based on the speed difference between the two, the formula The number of parallel branches is initially set to 4, where is the updated number of parallel branches, is the current number of parallel branches, is the data stream input speed, is the FPGA operating speed, is the adjustment factor, The proportional coefficient is used to deal with possible traffic mutations. The speed fluctuation threshold is set to 10%. At a certain moment, the input speed of the data flow is monitored to suddenly increase by 15%, exceeding the threshold. At this time, the system quickly re-evaluates within 5 seconds and adjusts the number of parallel branches to 6. At the same time, combined with the buffer performance, the formula The input data flow rate is adjusted from 10Gbps to 8Gbps, where: is the adjusted data flow rate, is the raw rate of the input data stream, is the number of parallel branches, is the buffer capacity, The rate adjustment influence coefficient ensures that it is lower than the FPGA's maximum operating rate of 10Gbps, thereby ensuring that the FPGA can process data stably and avoid signal congestion and loss.

[0032] After fully considering the FFT calculation requirements and the characteristics of laser communication signals, the formula , cut the continuous data stream into frames of length 1024 and distribute them to parallel frequency domain filtering channels, where Indicates the length of each frame signal, is the basic number of data points required for FFT calculation, is a length parameter related to signal characteristics, It is an empirical coefficient used to fine-tune the frame length according to the signal characteristics. After precise calculation, it is determined that the time for each frequency domain filter channel to process data is 1 microsecond. The calculation formula is: ,in, Indicates at time The time for each frequency domain filter channel to process data, is the number of parallel branches, It is the adjusted data flow rate, which is then evenly distributed to each channel. The processing rate of each channel is 1.33Gbps. During the data transmission process, if signal interference causes unstable data transmission, the system will adjust the frame strategy and rate allocation in real time to ensure the continuity and accuracy of data processing.

[0033] Since FFT calculation requires the number of input data points to be an integer power of 2, the current frame signal length after cutting is 1024, which needs to be padded with zeros to 2048. Combined with the laser communication signal type and the long-term accumulated historical data processing experience, a non-uniform zero-padding mode based on signal energy distribution is adopted. The number of zero-padding is appropriately increased in the part with lower signal energy to optimize the subsequent frequency domain transformation performance. For example, in some specific communication frequency bands, the signal energy is weak. This zero-padding method can effectively improve the stability and accuracy of the signal in frequency domain processing. The zero-padding data is encoded before entering the FPGA for convolution processing, so as to detect and correct errors in the transmission process and reduce the amount of data.

[0034] The input signal is subjected to a pipelined FFT transformation function to achieve efficient time domain to frequency domain conversion. For a specific signal, an FFT transformation is performed according to the set sampling point length. The formula is: ,in, It indicates the frequency domain result after FFT transformation of a specific signal. It is a specific signal. is the sampling point length of the FFT transform of a specific signal, It is a function that performs FFT transformation on a specific signal. In the frequency domain multiplication link, the system status is monitored in real time, the error compensation factor is calculated based on the relative change of the frequency domain results before and after, and the multiplication result is dynamically compensated. Specifically, when multiplying in the frequency domain, the formula is used Perform dynamic compensation, where represents the frequency domain result after multiplication and error compensation, and are the frequency domain results of the input signal and the specific signal respectively, It depends on the time The error compensation factor is calculated based on the system state, and its calculation formula is: , in, It is at the moment The error compensation factor is and Separate moments and The frequency domain result of the input signal elements, and Separate moments and The frequency domain result of a specific signal elements, is the error adjustment coefficient, It is the length of the frequency domain signal. This operation significantly improves the calculation accuracy, effectively reduces the bit error rate, and ensures the quality of laser communication. When facing complex communication environments, such as atmospheric turbulence and other interference, this method can stably process signals and ensure the reliability of communication. After completing the frequency domain calculation, the encoded data is decoded, and the data is judged whether there is an error in the processing process according to the check bit, and the erroneous data is corrected or marked. At the same time, considering the different requirements of different modules for data formats, the data is converted into code before output to ensure smooth transmission and correct processing of the data.

[0035] For the result after inverse FFT transformation, the truncation length is dynamically adjusted according to the application requirements of laser communication and the feedback information of signal processing. The adjustment formula is: Determine the cutoff length, where Indicates at time The cut-off length of is the base value of the cutoff length, is the adjustment coefficient, It is at the moment Application requirements information, It is at the moment The feedback information of signal processing, It is the starting time to consider truncation adjustment. For example, based on the communication quality feedback, it is found that some data have little effect on communication stability. The truncation length is adjusted from the initial 512 to 384, and the processed data is taken out from each parallel frequency domain filter channel. A multi-threaded parallel combination algorithm is used. At the same time, the importance and urgency of the data are combined to optimize the combination order. During emergency data transmission, key data is given priority, which greatly improves the data combination efficiency and the timeliness of the results, ensuring the stability and accuracy of laser communication.

[0036] Embodiment 2

[0037] In image signal processing scenarios, it is often necessary to process massive amounts of image data, and there are high requirements for processing speed and image quality improvement. First, the input speed of the image data stream is monitored in real time and compared with the FPGA working speed. In the initial stage, the number of parallel branches is determined to be 8 based on the speed difference, and the speed fluctuation threshold is set to 15%. When the input speed fluctuation exceeds the threshold during image data transmission, the system quickly re-evaluates within 3 seconds and adjusts the number of parallel branches to 10. The buffer is used to adjust the input data stream rate from 500Mbps to 400Mbps, which is lower than the FPGA's maximum working rate of 500Mbps, to ensure that the FPGA can stably process image data and avoid image freezes or distortions.

[0038] Taking into account the FFT calculation requirements and image signal characteristics, the continuous image data stream is cut into frame signals with a length of 512 and allocated to parallel frequency domain filtering channels. After calculation, it is determined that the data processing time of each frequency domain filtering channel is 0.5 microseconds and the processing rate of each channel is 40Mbps. When processing high-definition images or video streams, the frame division and rate strategies are dynamically adjusted according to the image resolution and frame rate to adapt to different processing requirements.

[0039] Due to the requirement of FFT calculation on the number of input data points, it is necessary to fill the cut frame signal from 512 to 1024 with zeros. Combined with the image signal type and historical processing experience, a uniform zero-filling mode is adopted to make the data meet the FFT calculation requirements and lay a good foundation for subsequent frequency domain processing. When processing different types of images, such as color images or grayscale images, the zero-filling strategy will be fine-tuned according to the characteristics of the image to improve the processing effect. The zero-filled data will be encoded before entering the FPGA for convolution processing, so as to detect and correct errors in the transmission process and reduce the amount of data.

[0040] The input image signal is efficiently converted to the frequency domain using a pipelined FFT transformation function. The specific signal is subjected to FFT transformation according to the set sampling point length. When multiplying in the frequency domain, the result is dynamically compensated by calculating the error compensation factor, which effectively enhances the details and clarity of the image. When processing blurred or noisy images, this method can significantly improve the image quality and make the image clearer and more recognizable. After completing the frequency domain calculation, the encoded data is decoded, and the check bit is used to determine whether the data has errors during processing, and the erroneous data is corrected or marked. At the same time, considering that different modules have different requirements for data formats, the data is converted into code before output to ensure smooth transmission and correct processing of the data.

[0041] According to the image application requirements and processing feedback information, the truncation length of the result after inverse FFT transformation is dynamically adjusted, for example, from the initial 256 to 192. A multi-threaded parallel combination algorithm is used to extract the processed data from each channel, and the combination order is optimized according to the importance and urgency of the data to the image quality. When processing real-time video streams, key frame data is processed first, which greatly improves the efficiency of image signal processing and the quality of output images, providing users with a better visual experience.

[0042] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. FPGA-based long-frame fast convolution system, characterized in that: The system includes the following components: parallel processing architecture design module, data framing and rate optimization module, data preprocessing zero filling module, frequency domain calculation processing module and result processing and output optimization module; The parallel processing architecture design module continuously monitors the data stream input speed and the FPGA operating speed, determines the number of parallel branches according to the speed difference between the two, and sets a speed fluctuation threshold, and re-evaluates and adjusts the number of parallel branches within a set time range when the data stream input speed fluctuation exceeds the threshold, thereby adjusting the data stream input speed; The data framing and rate optimization module cuts the continuous data stream into frame signals of fixed length according to the FFT calculation requirements and the length of the relevant signal, and distributes them to each parallel frequency domain filtering channel in an orderly manner. By comprehensively considering the frame signal length, the number of parallel branches and the adjusted data stream rate, the data processing time of each frequency domain filtering channel is calculated, and then the adjusted data stream rate is evenly distributed to each channel. The data preprocessing zero-padding module predicts the number of zero-padding for the cut frame signal based on the signal type, historical data processing experience, and the difference between the frame signal length and the number of points required by FFT. According to the prediction result, the zero-padding mode is selected and the original frame signal is padded with zeros. Before the data enters the FPGA for convolution processing, the data is encoded, thereby detecting and correcting errors in the transmission process and reducing the amount of transmitted data. The frequency domain calculation processing module adopts an FFT transformation function with a pipeline structure to convert the input signal from the time domain to the frequency domain. For a specific signal, an FFT transformation is performed according to a set sampling point length to convert it to the frequency domain. When the input signal is multiplied by the frequency domain result of the specific signal, the system status is monitored in real time, and an error compensation factor is calculated according to the relative change of the frequency domain results before and after, and the multiplication result is dynamically compensated. After completing the frequency domain calculation, the encoded data is decoded, and whether an error occurs in the data during the processing according to the check bit, and the erroneous data is corrected or marked. At the same time, considering that different modules have different requirements for data formats, the data is converted into code before it is output, so that the data can be transmitted smoothly and processed correctly; The result processing and output optimization module dynamically adjusts the truncation length of the result after inverse FFT transformation in real time according to application demand information and signal processing feedback information, and takes out the processed data from each parallel frequency domain filtering channel, adopts a multi-threaded parallel combination algorithm, and optimizes the combination order according to the importance and urgency of the data, so as to obtain the final convolution result.

2. The FPGA-based long frame fast convolution system according to claim 1, characterized in that: In the parallel processing architecture design step, the data stream input speed and the FPGA operating speed are continuously monitored, and the number of parallel branches is determined according to the speed difference between the two. The formula for determining the number of branches is: in, is the updated number of parallel branches, is the current number of parallel branches, is the data stream input speed, is the FPGA operating speed, is the adjustment factor, is the proportionality coefficient.

3. The FPGA-based long frame fast convolution system according to claim 2, characterized in that: In the parallel processing architecture design step, when the data stream input speed fluctuation exceeds the threshold, the number of parallel branches is re-evaluated and adjusted within a set time range, thereby adjusting the data stream input speed. The data stream input speed adjustment formula is: ,in, is the adjusted data flow rate, is the raw rate of the input data stream, is the number of parallel branches, is the buffer capacity, is the rate adjustment influence coefficient.

4. The FPGA-based long frame fast convolution system according to claim 1, characterized in that: In the data framing and rate optimization step, the continuous data stream is cut into frame signals of fixed length according to the FFT calculation requirements and the length of the related signal. The length determination formula is: , among which, from Indicates the length of each frame signal, is the basic number of data points required for FFT calculation, is a length parameter related to signal characteristics, is an empirical coefficient used to fine-tune the frame length according to signal characteristics.

5. The FPGA-based long frame fast convolution system according to claim 4, characterized in that: In the data framing and rate optimization step, the time for each frequency domain filtering channel to process data is calculated by comprehensively considering the frame signal length, the number of parallel branches and the adjusted data flow rate. The calculation formula is: ,in, Indicates at time The time for each frequency domain filter channel to process data, is the number of parallel branches, is the adjusted data flow rate.

6. The FPGA-based long frame fast convolution system according to claim 4, characterized in that: In the data preprocessing zero-filling step, for the cut frame signal, the number of zero-filling is predicted based on the signal type, historical data processing experience, and the difference between the frame signal length and the number of points required by FFT. The prediction formula is: = + ,in Indicates the number of zeros that need to be filled. Indicates the signal type. Represents historical data processing experience information, is the length of the current frame signal, and is the weighting coefficient, It is the first in historical data processing experience The weights associated with each feature, It is based on the signal type and historical processing experience. The function of feature calculation, is satisfied The smallest integer.

7. The FPGA-based long frame fast convolution system according to claim 1, characterized in that: In the frequency domain calculation processing step, for the input signal, a pipeline structure FFT transformation function is used to transform it from the time domain to the frequency domain, and its function formula is: ,in Indicates at time The frequency domain result of the input signal after pipeline FFT transformation, It is at the moment The input signal after zero padding, It represents the FFT transform function using pipeline structure. For a specific signal, FFT transform is performed according to the set sampling point length to convert it into the frequency domain. The formula is: ,in, It indicates the frequency domain result after FFT transformation of a specific signal. It is a specific signal. is the sampling point length of the FFT transform of a specific signal, It is a function that performs FFT transformation on a specific signal.

8. The FPGA-based long frame fast convolution system according to claim 7, characterized in that: In the frequency domain calculation processing step, when the input signal is multiplied by the frequency domain result of the specific signal, the system state is monitored in real time, and the error compensation factor is calculated according to the relative change of the frequency domain results before and after, and the multiplication result is dynamically compensated. Specifically, when multiplying in the frequency domain, the formula is used Perform dynamic compensation, where represents the frequency domain result after multiplication and error compensation, and are the frequency domain results of the input signal and the specific signal respectively, It depends on the time The error compensation factor is calculated based on the system state, and its calculation formula is: ,in, It is at the moment The error compensation factor is and Separate moments and The frequency domain result of the input signal elements, and Separate moments and The frequency domain result of a specific signal elements, is the error adjustment coefficient, is the length of the frequency domain signal.

9. The FPGA-based long frame fast convolution system according to claim 1, characterized in that: In the result processing and output optimization step, the truncation length is dynamically adjusted in real time according to the application requirement information and the signal processing feedback information. The adjustment formula is: Determine the cutoff length, where Indicates at time The cut-off length, is the base value of the cutoff length, is the adjustment coefficient, It is at the moment Application requirements information, It is at the moment The feedback information of signal processing, Is the starting time to start considering truncation adjustments.

10. The FPGA-based long frame fast convolution system according to claim 1, characterized in that: In the result processing and output optimization step, a multi-threaded parallel combination algorithm is used, and the combination order is optimized according to the importance and urgency of the data to obtain the final convolution result. Specifically, the formula is used Combine the final results, where represents the final convolution result, It is at the moment From The data extracted from the parallel frequency domain filtering channels is It is the importance and urgency of the data. It is at the moment No. The weight of the channel data, It is a multi-threaded parallel combination function.

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