Signal noise compensation method based on RFSOC digital processing module

Abstract

The invention belongs to the technical field of signal preprocessing and compensation, and particularly relates to a signal noise compensation method based on an RFSOC digital processing module, which comprises the following steps: after configuration of an upper computer, an FPGA end sends specific beginning digital waveform data of L periods to a DAC, the DAC converts a digital waveform signal into an analog waveform signal, and the analog waveform signal is sent to the FPGA end; after passing through the signal conditioning circuit, the signal is received and converted into a digital waveform signal to be detected by the ADC, the digital waveform signal to be detected is sent to the FPGA, the FPGA starts to carry out signal noise detection after receiving L waveform signals transmitted by the ADC, the signal noise detection module intercepts a specific waveform fragment to carry out fast Fourier transform calculation, and a characteristic value of frequency domain data is extracted. And the signal noise compensation module selects a corresponding compensation strategy according to the characteristic value to carry out compensation calculation on the waveform data to obtain new waveform data. Based on the RFSOC digital processing module, an RFSOC chip architecture is adopted to replace a traditional ADC and DAC + FPGA mode, signal generation, acquisition and compensation can be achieved in the same chip, repeated transmission is not needed, the system response speed is high, and the real-time performance is high.

Description

Technical Field

[0001] The invention belongs to the technical field of signal preprocessing and compensation technology, and in particular relates to a signal noise compensation method based on an RFSOC digital processing module. Background Art

[0002] In the field of electronic measuring instruments, digital processing modules based on RFSoC can be applied to baseband signal generation and intermediate frequency signal acquisition. Baseband signal generation and intermediate frequency signal acquisition technology are important components of electronic measuring and testing instruments, and are widely used in a variety of instruments such as signal sources, spectrum analyzers, and vector network analyzers. Baseband signal generation and intermediate frequency signal acquisition are key technologies for improving RF signal quality and improving RF signal measurement accuracy indicators.

[0003] The baseband signal generation technology currently used is mainly implemented through the DAC + FPGA architecture, and the calibration and compensation of the baseband signal are mainly implemented through the host computer software. After the host computer generates the waveform data, it is written into the DDR4 memory on the FPGA board and sent to the DAC through the FPGA. The DAC converts the digital signal into an analog signal and outputs it through the conditioning circuit. The spectrum of the analog signal is measured by measuring instruments such as spectrum analyzers to obtain parameters such as phase noise, harmonic spurs, and non-harmonic spurs of the signal. After noise analysis, the corresponding signal compensation algorithm is written to compensate the waveform generated by the waveform generation algorithm. However, in the traditional FPGA + DAC architecture, the host computer uses the calibration and compensation algorithm to compensate the sent data, which needs to be transmitted twice from the host computer to the FPGA and from the FPGA to the DAC. The transmission path is long, and it is difficult to perform real-time calibration based on the noise of the output signal. Summary of the invention

[0004] In view of the various shortcomings of the prior art, the inventors have designed a signal noise compensation method based on the RFSOC digital processing module through long-term practice. Based on the RFSOC digital processing module, the problem of the prior art that the transmission path is long and it is difficult to perform real-time calibration based on the noise of the output signal is solved.

[0005] The present invention discloses a signal noise compensation method based on an RFSOC digital processing module, which realizes signal noise compensation through a digital processing module. The digital processing module includes an RFSoC chip, a clock module, a DDR storage module, and a signal conditioning circuit. The RFSoC chip has built-in ADC, DAC, and FPGA. The FPGA has built-in signal noise detection module, noise characteristic value matching module, signal noise compensation module, and digital waveform generation module. The specific method of signal noise compensation is as follows:

[0006] Step 1: After configuration by the host computer, the FPGA end of the RFSoC chip generates a digital waveform data with a specific beginning. The FPGA end sends L cycles of digital waveform data, which are transmitted to the DAC through the Input FIFO. The DAC converts the digital waveform signal into an analog waveform signal after digital-to-analog conversion and sends it out. After the signal passes through the signal conditioning circuit, it is received by the ADC and converted into a digital waveform signal to be tested, which is sent to the FPGA through the FIFO gearbox and stored in the DDR storage module after parallel-to-serial conversion.

[0007] Step 2: After the FPGA receives L waveform signals from the ADC, it starts to detect signal noise; the signal noise detection module intercepts a specific waveform segment to perform fast Fourier transform calculation, converts it into frequency domain data and analyzes the frequency domain data to extract the eigenvalue of the frequency domain data; the signal noise compensation module selects the corresponding compensation strategy according to the eigenvalue, performs compensation calculation on the waveform data, and obtains compensated waveform data.

[0008] Furthermore, the signal conditioning circuit includes an output signal conditioning circuit and an input signal conditioning circuit, the output signal conditioning circuit is communicatively connected to the DAC, and the input signal conditioning circuit is communicatively connected to the ADC.

[0009] Furthermore, a loop circuit is provided between the output signal conditioning circuit and the input signal conditioning circuit.

[0010] Furthermore, the RFSoC chip is also communicatively connected to a flash memory and a power supply module, and the power supply module is communicatively connected to a voltage detection module; the RFSoC chip communicates with a host computer via a PCIe interface, an HDMI interface and an optoelectronic interface.

[0011] Furthermore, in step one, the host computer writes the waveform data into the DDR storage module through the PCIe interface, and after the FPGA detects that the data reception is completed, it sends M cycles of waveform data to the DAC; then the FPGA cyclically sends L cycles of waveform data to the DAC, and finally the FPGA sends M cycles of waveform data to the DAC as an end.

[0012] Furthermore, after the ADC receives the first wave of M cycles of waveform data after conversion by the DAC, the waveform data of L cycles received subsequently are stored in the DDR storage module; when the ADC receives the last M cycles of waveform data, the FPGA determines the transmission order and performs signal noise detection on the received waveform data.

[0013] Furthermore, the signal noise detection module reads the waveform data to be tested from the memory, performs fast Fourier transform calculation on the waveform data to be tested, converts it into frequency domain data and analyzes the frequency domain data to obtain the three frequency values ​​with the largest power spectrum density except the target frequency, and calculates the eigenvalue according to the peak frequency value and power. The eigenvalue is a vector composed of three normalized frequencies and powers.

[0014] Furthermore, the noise eigenvalue matching module uses the three peak frequency data extracted by the signal noise detection module as the data to be matched, performs vector dot product with the preset multiple noise model data respectively, finds the noise model whose dot product with the data to be matched is 0, completes the noise eigenvalue matching, and finally, the noise eigenvalue matching module sends the eigenvalue vector corresponding to the matched noise model to the signal compensation module.

[0015] Furthermore, the signal noise compensation module inputs the eigenvalue vector into the signal noise compensation algorithm. The signal compensation algorithm determines the frequency band that needs to be compensated for the signal according to the frequency value in the vector, compensates one or more frequency bands according to the noise frequency value distribution, determines the gain value of the compensation data according to the power spectrum density, and determines the corresponding compensation strategy according to the overall signal-to-noise ratio of the signal. Finally, a set of compensation data is obtained through calculation, the compensation data is added to the waveform data, the waveform data is compensated, and new waveform data is obtained.

[0016] Furthermore, the digital waveform generation module adopts a lookup table method, and the phase accumulator accumulates and generates 48-bit phase waveform data, takes the high 32-bit waveform data in the 48-bit phase waveform data as the address, sends it to the DDR storage module, and then reads the waveform data in the corresponding address in the DDR and sends it to the DAC.

[0017] The beneficial effects of the present invention are:

[0018] 1) Based on the RFSOC digital processing module, the RFSOC chip architecture is used to replace the traditional ADC / DAC+FPGA mode, which can realize signal generation, acquisition and compensation in the same chip without multiple transmissions. The system has fast response speed and high real-time performance.

[0019] 2) Using the eigenvalue recognition method, the sampling accuracy requirement of the ADC is relatively low. At the same time, a preset compensation strategy is adopted to reduce the complexity of the algorithm, which can be implemented in FPGA.

[0020] 3) RFSoC is used to complete most functions, reducing the number of chips and optimizing the overall hardware structure. Compared with existing methods, it has low cost, small size and compact layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1It is a design principle block diagram of the digital processing module of the present invention.

[0022] Figure 2 This is the signal compensation implementation process of the present invention.

[0023] Figure 3 It is a working flow chart of the signal noise detection module of the present invention.

[0024] Figure 4 It is a working flow chart of the signal noise compensation module of the present invention.

[0025] Figure 5 It is the flow chart of FPGA program execution of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and implementation examples. These implementation examples are described in sufficient detail so that those skilled in the art can understand and practice the present invention. Without departing from the spirit and scope of the present invention, logical, achievable and other changes may be made to the implementation. Therefore, the following detailed description should not be construed as limiting, and the scope of the present invention is limited only by the claims.

[0027] See also Figure 1~Figure 5 The present invention proposes a signal noise compensation method based on an RFSOC digital processing module, and realizes signal noise compensation through the digital processing module.

[0028] The digital processing module includes an RFSoC chip, a clock module, a DDR storage module, and a signal conditioning circuit.

[0029] The RFSoC chip has built-in ADC (analog-to-digital converter), DAC (digital-to-analog converter) and FPGA (field programmable gate array). The RFSoC chip is mainly responsible for communicating with the host computer, digital signal processing, and RF signal input and output. The FPGA has built-in signal noise detection module, noise characteristic value matching module, signal noise compensation module and digital waveform generation module. The FPGA is mainly responsible for communication with the instrument end and protocol conversion functions.

[0030] The signal conditioning circuit includes an output signal conditioning circuit and an input signal conditioning circuit, the output signal conditioning circuit is connected to the DAC for communication, and the input signal conditioning circuit is connected to the ADC for communication. A loopback circuit is provided between the output signal conditioning circuit and the input signal conditioning circuit.

[0031] The signal conditioning circuit is mainly used to adjust the power of the waveform signal, filter the waveform signal, etc. The loopback circuit is mainly used to transmit the waveform signal from the DAC end to the ADC end as lossless as possible.

[0032] The clock module is used to supply clock to the FPGA, DAC, and ADC in the RFSoC chip. The DDR storage module is mainly used to store waveform data.

[0033] The RFSoC chip is also connected to the flash memory and power supply module. The flash memory is used to initialize the FPGA. The power supply module is also connected to the voltage detection module. The power supply module is mainly used to output a low-noise ripple voltage and realize the power supply monitoring function.

[0034] The RFSoC chip also communicates with the host computer through PCIe interface, HDMI interface and optoelectronic interface.

[0035] The specific method of signal noise compensation of the present invention is:

[0036] Step 1: After configuration by the host computer, the FPGA side of the RFSoC chip generates a digital waveform data with a specific beginning. The FPGA side sends L cycles of digital waveform data, which are transmitted to the DAC of the RFSoC chip through the Input FIFO. The DAC converts the digital waveform signal into an analog waveform signal after digital-to-analog conversion and sends it out. After the signal passes through the conditioning circuit and the loopback circuit, it is received by the ADC of the RFSoC chip, converted into a digital waveform signal to be tested, and sent to the FPGA through the FIFO gearbox. After parallel-to-serial conversion, it is stored in the DDR storage module.

[0037] Step 2: After receiving the L waveform signals from the ADC, the FPGA starts to detect the signal noise. The signal noise detection module intercepts a specific waveform segment, performs fast Fourier transform calculation, converts it into frequency domain data, analyzes the frequency domain data, and extracts the characteristic value of the frequency domain data; selects the corresponding compensation strategy according to the characteristic value, performs compensation calculation on the waveform data, and obtains the compensated waveform data.

[0038] See also Figure 5 FPGA program is used to generate waveform signals, realize signal noise detection and compensation process, and control peripheral circuits. The main process of FPGA program is as follows:

[0039] The host computer writes the waveform data into the DDR storage module through the PCIe interface. After the FPGA detects that the data reception is completed, it sends M cycles of waveform data (for example, a square wave with a frequency of 100kHz) to the DAC; the FPGA then sends L cycles of waveform data to the DAC in a loop, and finally the FPGA sends M cycles of waveform data to the DAC as the end.

[0040] After the ADC receives the first wave of M cycles of waveform data after DAC conversion, it stores the subsequent L cycles of waveform data received in the DDR storage module. When the ADC receives the last M cycles of waveform data, the FPGA determines the transmission order, performs signal noise detection on the received waveform data, and compensates the waveform data based on the characteristic values ​​calculated by the detection.

[0041] The signal noise detection module reads the waveform data to be tested from the memory, performs fast Fourier transform calculation on the waveform data to be tested, converts it into frequency domain data, analyzes the frequency domain data, obtains the three frequency values ​​with the largest power spectrum density except the target frequency, and calculates the eigenvalue based on the peak frequency value and power. The eigenvalue is a vector composed of three normalized frequencies and powers.

[0042] The noise eigenvalue matching module uses the three peak frequency data extracted by the signal noise detection module as the data to be matched, and performs vector dot product with multiple preset noise model data respectively, and finds the noise model whose dot product with the data to be matched is 0, then the noise eigenvalue matching is completed. After the matching is completed, the noise eigenvalue matching module sends the eigenvalue vector corresponding to the matched noise model to the signal compensation module.

[0043] The signal noise compensation module inputs the eigenvalue vector into the signal noise compensation algorithm. The signal compensation algorithm determines the frequency band that needs to be compensated according to the frequency value in the vector, and compensates one or more frequency bands according to the noise frequency value distribution. The gain value of the compensation data is determined according to the power spectrum density; the corresponding compensation strategy is determined according to the overall signal-to-noise ratio of the signal. Finally, a set of compensation data is obtained after calculation, and the compensation data is added to the waveform data, and the waveform data is compensated to obtain new waveform data.

[0044] The digital waveform generation module is used to generate waveform data, and the amplitude, frequency and phase of the output waveform are adjustable. The digital waveform generation module uses the lookup table method to generate 48-bit phase waveform data by accumulating the phase accumulator, and sends the high 32-bit waveform data in the 48-bit phase waveform data as the address to the DDR storage module, and then reads the waveform data in the corresponding address in the DDR and sends it to the DAC.

[0045] The present invention uses RFSoC for digital signal processing, reduces the supporting circuits related to DAC and ADC, greatly reduces circuit components, circuit board area and connection lines, and improves the performance and stability of the system. The present invention generates, receives and compensates waveform data in one RFSoC chip, shortens the time required for signal transmission, optimizes the compensation path, and improves the compensation efficiency.

[0046] The present invention is a signal noise compensation method with strong real-time performance, high compensation accuracy, fast compensation speed and large compensation range. It can be applied to application scenarios of various instruments, and can perform targeted compensation on baseband signals or modulated signals to improve signal quality.

[0047] The hardware system on which the present invention is based has strong compatibility, adopts standard board card interface and appearance, can be installed in a standard PXIe chassis, supports multiple interfaces such as PCIe3.0, HDMI, optoelectronic interface, etc., has good hardware adaptability, and can be applied to a variety of instruments and equipment.

[0048] It is not possible to describe all possible combinations of components or methods for the purpose of describing the above-described embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is encompassed in a manner similar to the term "including," as explained by "including," used as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or."

Claims

1. A signal noise compensation method based on RFSOC digital processing module, characterized in that: Signal noise compensation is achieved through a digital processing module, which includes an RFSoC chip, a clock module, a DDR storage module, and a signal conditioning circuit. The RFSoC chip has built-in ADC, DAC, and FPGA. The FPGA has built-in signal noise detection module, noise characteristic value matching module, signal noise compensation module, and digital waveform generation module. The specific method of signal noise compensation is as follows: Step 1: After configuration by the host computer, the FPGA end of the RFSoC chip generates a digital waveform data with a specific beginning. The FPGA end sends L cycles of digital waveform data, which are transmitted to the DAC through the Input FIFO. The DAC converts the digital waveform signal into an analog waveform signal after digital-to-analog conversion and sends it out. After the signal passes through the signal conditioning circuit, it is received by the ADC and converted into a digital waveform signal to be tested, which is sent to the FPGA through the FIFO gearbox and stored in the DDR storage module after parallel-to-serial conversion. Step 2: After the FPGA receives the L waveform signals from the ADC, it starts to detect the signal noise; the signal noise detection module intercepts a specific waveform segment to perform fast Fourier transform calculation, converts it into frequency domain data, analyzes the frequency domain data, and extracts the characteristic value of the frequency domain data; The signal noise compensation module selects a corresponding compensation strategy according to the characteristic value, performs compensation calculation on the waveform data, and obtains compensated waveform data.

2. The method according to claim 1, characterized in that The signal conditioning circuit includes an output signal conditioning circuit and an input signal conditioning circuit. The output signal conditioning circuit is connected to the DAC in communication, and the input signal conditioning circuit is connected to the ADC in communication.

3. The method according to claim 2, characterized in that A loop circuit is provided between the output signal conditioning circuit and the input signal conditioning circuit.

4. The method according to claim 1, characterized in that: The RFSoC chip is also communicatively connected to a flash memory and a power supply module, and the power supply module is communicatively connected to a voltage detection module; the RFSoC chip communicates with a host computer via a PCIe interface, an HDMI interface and an optoelectronic interface.

5. The method according to claim 4, characterized in that In step one, the host computer writes the waveform data into the DDR storage module through the PCIe interface. After the FPGA detects that the data reception is completed, it sends M cycles of waveform data to the DAC; then the FPGA sends L cycles of waveform data to the DAC in a loop, and finally the FPGA sends M cycles of waveform data to the DAC as a conclusion.

6. The method according to claim 5, characterized in that After receiving the waveform data of the first wave M cycles converted by the DAC, the ADC stores the waveform data of the subsequently received L cycles into the DDR storage module; After the ADC receives the waveform data of the last M cycles, the FPGA determines the transmission order and performs signal noise detection on the received waveform data.

7. The method according to claim 1, characterized in that The signal noise detection module reads the waveform data to be tested from the memory, performs fast Fourier transform calculation on the waveform data to be tested, converts it into frequency domain data and analyzes the frequency domain data to obtain the three frequency values ​​with the largest power spectrum density except the target frequency, and calculates the eigenvalue according to the peak frequency value and power. The eigenvalue is a vector composed of three normalized frequencies and powers.

8. The method according to claim 7, characterized in that The noise eigenvalue matching module uses the three peak frequency data extracted by the signal noise detection module as the data to be matched, performs vector dot product with the preset multiple noise model data respectively, finds the noise model whose dot product with the data to be matched is 0, completes the noise eigenvalue matching, and finally the noise eigenvalue matching module sends the eigenvalue vector corresponding to the matched noise model to the signal compensation module.

9. The method according to claim 8, characterized in that The signal noise compensation module inputs the eigenvalue vector into the signal noise compensation algorithm. The signal compensation algorithm determines the frequency band that needs to be compensated for the signal according to the frequency value in the vector, compensates one or more frequency bands according to the noise frequency value distribution, determines the gain value of the compensation data according to the power spectrum density, and determines the corresponding compensation strategy according to the overall signal-to-noise ratio of the signal. Finally, a set of compensation data is obtained through calculation, the compensation data is added to the waveform data, the waveform data is compensated, and new waveform data is obtained.

10. The method according to claim 9, characterized in that The digital waveform generation module adopts a lookup table method, and the phase accumulator accumulates and generates 48-bit phase waveform data. The high 32-bit waveform data in the 48-bit phase waveform data is used as the address and sent to the DDR storage module, and then the waveform data in the corresponding address in the DDR is read and sent to the DAC.

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