FPGA-based Timing Generator, Timing Generation Method, Terminal Device, and Readable Storage Medium

Abstract

The present application relates to the field of semiconductors, and discloses a timing generator based on FPGA, a timing generation method, a terminal device, and a readable storage medium, including: a clock source for providing a working frequency; a test cycle buffer for sequentially buffering each test cycle data; a timing data buffer for sequentially buffering each timing data; a test cycle counter for starting counting each time a test cycle is entered; a timing edge generator for determining whether the timing clock is enabled according to the count of the test cycle data and the integer part value of the timing data in the same test cycle, and outputting the fractional part value of the timing clock that is less than an integer multiple; a data generator for generating parallel data with a preset bit width from the received one-bit pattern data when the timing clock is enabled; a converter for converting the parallel data into serial data by using a preset multiple-frequency clock of the working frequency and then outputting it. This solution can improve the time resolution based on the timing generator.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a timing generator based on FPGA, a timing generation method, a terminal device, and a readable storage medium. Background Art

[0002] In a semiconductor test system, a timing generator is an essential module, whose function is to generate test cycles and output required data at fixed moments within each cycle, and remain unchanged at other moments. Among them, the common implementation tools for timing generators currently are FPGA (Field-Programmable Gate Array) and special IC chips for Timing generate. Compared with using FPGA, the IC chips have high costs, require dedicated IC chips, and have a long development cycle.

[0003] Therefore, it is necessary to propose a timing generator implemented based on FPGA. However, FPGA needs to work rhythmically under a clock with a fixed frequency. For example, the operating frequency of common industrial-grade FPGA chips generally does not exceed 200 MHz. The problem brought about by this is that the time resolution of the timing generator is limited by the FPGA clock. Assuming the clock frequency is 200 MHz, the time resolution is the clock cycle T = 5 ns, and it often cannot meet the requirements when higher time resolution is needed. Summary of the Invention

[0004] In view of this, this application provides a timing generator based on FPGA, a timing generation method, a terminal device, and a readable storage medium, which can effectively improve the problem of time resolution based on FPGA.

[0005] In a first aspect, an embodiment of this application provides a timing generator based on FPGA, including:

[0006] A clock source, configured to provide the operating frequency required by other units in the FPGA;

[0007] A test cycle buffer, configured to sequentially buffer each test cycle data, and output the first integer part value and the first decimal part value of each test cycle data calculated based on the operating frequency;

[0008] A timing data buffer, configured to sequentially buffer each timing data, and output the second integer part value and the second decimal part value of each timing data calculated based on the operating frequency;

[0009] A test cycle counter, which is used to start counting each time a test cycle is entered and output the difference between the respective first fractional part values of the current test cycle data and the previous test cycle data;

[0010] A timing edge generator, which is used to determine whether a timing clock is enabled according to the count of the test cycle data and the second integer part value in the same test cycle, and output a third fractional part value of a non-integer multiple of the timing clock according to the difference and the second fractional part value;

[0011] A data generator, which is used to generate parallel data with a preset bit width from the received one-bit pattern data according to the third fractional part value when the timing clock is enabled;

[0012] A converter, which is used to convert the parallel data into serial data by using a preset multiple-frequency clock of the operating frequency and then output it.

[0013] In some embodiments, the test cycle counter is further used to clear when the count reaches zero, where the difference between the first integer part value of the current test cycle data and the test cycle borrow is zero.

[0014] In some embodiments, the test cycle buffer is specifically used to divide the test cycle data by the clock cycle corresponding to the operating frequency, and use the obtained quotient and remainder as the first integer part value and the first fractional part value respectively.

[0015] In some embodiments, the timing data buffer is specifically used to divide the timing data by the clock cycle corresponding to the operating frequency, and use the obtained quotient and remainder as the second integer part value and the second fractional part value respectively.

[0016] In some embodiments, the timing edge generator is specifically used to determine that the timing clock is enabled when the difference between the second integer part value and the timing data borrow in the same test cycle is equal to the count of the test cycle data; and use the difference between the difference and the second fractional part value as the third fractional part value of the non-integer multiple of the timing clock.

[0017] In some embodiments, the data generator is specifically used to determine the holding length of the pattern data according to the magnitude of the third fractional part value when the timing clock is enabled;

[0018] And set all the bits from the highest bit to the bit corresponding to the holding length in the preset bit width to the pattern data, and set the values of the remaining bit width except the holding length to the highest bit value of the pattern data input in the previous test cycle to generate the parallel data with the preset bit width.

[0019] In some embodiments, the value of the test cycle data is not less than the clock cycle corresponding to the operating frequency;

[0020] The value range of the timing data is: test rate ~ T / 8; where test rate is the test cycle and T is the clock cycle.

[0021] In a second aspect, an embodiment of the present application further provides a timing generation method based on FPGA, which is applied to the timing generator; the method includes:

[0022] Obtain the first integer part value and the first decimal part value of each preset test cycle data calculated based on the operating frequency of the FPGA;

[0023] Obtain the second integer part value and the second decimal part value of each preset timing data calculated based on the operating frequency;

[0024] Each time a test cycle is entered, start counting according to the operating frequency, and output the difference between the first decimal part values of the current test cycle data and the previous test cycle data;

[0025] Determine whether the timing clock is enabled according to the count of the test cycle data and the second integer part value in the same test cycle, and output the third decimal part value of the timing clock that is not an integer multiple according to the difference and the second decimal part value;

[0026] When the timing clock is enabled, generate parallel data with a preset bit width from the received one-bit pattern data according to the third decimal part value;

[0027] Convert the parallel data into serial data and output it using a preset multiple-frequency clock of the operating frequency.

[0028] In a third aspect, an embodiment of the present application further provides a terminal device, the terminal device includes an FPGA, and the terminal device is used to implement the timing generation method based on FPGA.

[0029] In a fourth aspect, an embodiment of the present application further provides a readable storage medium, which stores a computer program, and when the computer program is executed, the timing generation method based on FPGA is implemented.

[0030] The embodiments of the present application have the following advantages:

[0031] The present application proposes a timing generator based on FPGA, which includes a clock source for providing an operating frequency, a test cycle buffer for caching test cycle data, a timing data buffer for caching timing data, and a test cycle counter for starting counting each time a test cycle is entered and outputting the difference between the respective first fractional part values of the current test cycle data and the previous test cycle data; a timing edge generator for determining whether the timing clock is enabled according to the count of the test cycle data and the integer part value of the timing data in the same test cycle, and outputting the fractional part value of the non-full integer multiple timing clock; a data generator for generating parallel data with a preset bit width from the received one-bit pattern data when the timing clock is enabled; and a converter for converting the parallel data into serial data using a preset multiple-frequency clock of the operating frequency and then outputting it. Compared with the existing timing generator based on the FPGA platform, this solution can improve the resolution of the timing generator to T / 8 at the same operating frequency of the FPGA, thereby achieving more precise timing control. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1 FIG. shows the structural schematic diagram of the timing generator according to the embodiment of the present application;

[0034] Figure 2 FIG. shows a verification waveform diagram of the timing generator according to the embodiment of the present application;

[0035] Figure 3 FIG. shows a flowchart of a timing generation method according to the embodiment of the present application.

[0036] MAIN ELEMENT SYMBOL DESCRIPTION:

[0037] 10 - Timing generator; 110 - Clock source; 120 - Test cycle buffer; 130 - Timing data buffer; 140 - Test cycle counter; 150 - Timing edge generator; 160 - Data generator; 170 - Converter. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0039] The components of the embodiments of the present application that are generally described and illustrated in the accompanying drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0040] Hereinafter, the terms "including", "having" and their cognates that may be used in various embodiments of the present application are only intended to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or precluding the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0041] In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0042] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in a commonly used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0043] Figure 1 A schematic structural diagram of an FPGA-based timing generator 10 according to an embodiment of the present application is shown. Demonstratively, the timing generator 10 is based on a hardware FPGA platform and combines software logic, which can solve the problem in the prior art that the time resolution of using an FPGA is limited by the FPGA clock. In particular, it can implement a fractional timing signal and achieve the effect of improving the time resolution.

[0044] For the convenience of the input and output signals of these components in the text, the English identifiers and Chinese meanings involved in the present application are uniformly described herein first.

[0045] T: Clock period;

[0046] test rate: Test period data;

[0047] rate_n: The integer part value of the test period data, briefly recorded as the first integer part value;

[0048] rate_m: The fractional part value of the test cycle data, briefly recorded as the first fractional part value;

[0049] timing: Timing data;

[0050] timing_n: The integer part value of the timing data, briefly recorded as the second integer part value;

[0051] timing_m: The fractional part value of the timing data, briefly recorded as the second fractional part value;

[0052] fifo_rd: The read enable signal of the fifo;

[0053] counter: The count value when entering a test cycle, with a bit width of 8 bits, i.e., counter [7:0];

[0054] sum_m: The difference between the fractional part values of the current test cycle data and the previous test cycle data, briefly recorded as the difference of the first fractional part value;

[0055] rate_borrow: The borrow signal of the test cycle;

[0056] period_sop: The start signal of a test cycle;

[0057] clk: The reference signal output by the clock source;

[0058] clk_en: The timing clock enable signal;

[0059] clk_m: The fractional part value of the timing clock that is less than an integer multiple, briefly recorded as the third fractional part value;

[0060] timing_borrow: The borrow signal of the timing data;

[0061] pattern_data: The pattern data used for testing;

[0062] parall_data: Parallel data, with a bit width that can be 8 bits, i.e., parall_data [7:0];

[0063] data_out: The serial data output by the converter.

[0064] Exemplarily, the timing generator 10 includes: a clock source (base_clk) 110, a test cycle buffer (rate_fifo) 120, a timing data buffer (timing_fifo) 130, a test cycle counter (rate_counter) 140, a timing edge generator (timing_edge_generator) 150, a data generator (data_generate) 160, and a converter (oserdes) 170. Among them, the clock source 110 is respectively connected to the test cycle buffer 120, the timing data buffer 130, the test cycle counter 140, the timing edge generator 150, the data generator 160, and the converter 170 to provide the operating frequencies required by each unit. The test cycle buffer 120, the test cycle counter 140, the timing edge generator 150, the data generator 160, and the converter 170 are connected in sequence; the timing data buffer 130 is respectively connected to the test cycle counter 140 and the timing edge generator 150.

[0065] The clock source 110 is used to provide the operating frequencies required by each unit in the FPGA, so that each unit operates rhythmically in the clock cycle (denoted as T) corresponding to the operating frequency. For example, for an industrial-grade FPGA chip, the value range of its operating frequency can be 1 MHz to 200 MHz. Correspondingly, the value range of the clock cycle corresponding to the operating frequency can be 1 us to 5 ns.

[0066] The test cycle buffer 120 is used to cache each test cycle data (denoted as test rate). After the FPGA finishes running one test cycle, the next test cycle data will be stored in the test cycle buffer 120. In this application, the test cycles of the same or different sizes can be set each time. Since the maximum operating frequency of the FPGA does not exceed 2000 MHz and its corresponding time resolution is 5 ns, for example, only one-bit data can be output within a 5-ns time. Therefore, in this application, a test cycle is set, and multiple data can be output within this test cycle. Generally, the test cycle data can be taken according to the time resolution of the FPGA. For example, when the maximum operating frequency of the FPGA is 200 MHz, the value range of the test cycle data can be set to 1 us to 5 ns.

[0067] It should be noted that the timing generator 10 in this application can be a fractional integration type. However, considering that it is not easy to represent fractions in an FPGA, all calculations such as the test period and timing data are converted into integer calculations. To better understand this solution, here, taking the example of improving the resolution of the timing data to T / 8, correspondingly, in the actual addition and subtraction processes, calculations are performed in octal, that is, when the fractional part reaches 8, it advances by 1. It can be understood that assuming the maximum working frequency of the FPGA is 200 MHz, compared with the original resolution (T = 5 ns), after adopting the solution of this application, the resolution can be improved to a maximum of 625 ps (i.e., T / 8). It should be noted that this solution is not limited to improving the resolution to T / 8 and can be adaptively adjusted according to actual needs, which is not specifically limited here.

[0068] As an alternative solution, the test period can be set to a non-integer multiple of the clock period, that is, it does not need to be an integer multiple of T. In this application, the test period buffer 120 is further configured to calculate and output the first integer part value (denoted as rate_n) and the first fractional part value (denoted as rate_m) of each test period data based on the current working frequency of the FPGA. Among them, the meanings represented by the above first integer part value and first fractional part value are respectively: the integer number of Ts included in the test period and the remaining part less than one T.

[0069] For example, in one implementation, the quotient and remainder obtained by dividing the test rate by T can be used as the above first integer part value and first fractional part value respectively. For instance, assuming T = 5 ns and test rate = 8.125 ns, then rate_n = 1 and rate_m = 5. It can be understood that the use of "first" here is mainly for distinguishing from the integer and fractional part values of other data such as timing data mentioned later and for convenient reference.

[0070] The timing data buffer 130 is used to buffer each timing data. After specifying the test period, the timing data is used to control the output timing of the data within that test period. In this application, the timing data should not be less than the minimum time resolution of the test period. In one implementation, the minimum time resolution of the timing generator 10 is 1 / 8 of the clock period corresponding to the working frequency. Therefore, the value range of the timing data can be test rate ~ T / 8. For example, if the current time resolution of the FPGA is 5 ns and the resolution of the timing generator 10 is to be T / 8 (i.e., the resolution is 625 ps), then the timing data can take values between (test rate ~ 625 ps).

[0071] As an alternative, the timing data can also be set to non-integer multiples of the timing values. In this application, the timing data buffer 130 is further configured to calculate and output the second integer part value (denoted as timing_n) and the second fractional part value (denoted as timing_m) of each timing data based on the current operating frequency of the FPGA. The meanings represented by the second integer part value and the second fractional part value are respectively: the integer number of Ts included in the timing and the remaining part less than one T.

[0072] For example, in one implementation, the quotient and remainder obtained by dividing timing by T can be used as the above-mentioned second integer part value and second fractional part value respectively. For instance, assume T = 5 ns and timing = 1.25 ns, then timing_n = 0 and timing_m = 2. It can be understood that the use of "second" here is mainly for distinguishing from the integer and fractional part values of other data mentioned above and for convenient reference.

[0073] In some embodiments, both the above-mentioned test cycle buffer 120 and timing data buffer 130 can be implemented using fifo (First In First Out) units. Further, the fifo units can be made to operate in the FWFT (first_word_fall_through) mode. It can be understood that in the FWFT mode, the data can be read out as the first valid data in the first cycle when the read enable signal (fifo_rd) of the fifo is valid. Compared with the fifo in the Standard (conventional) mode, it can reduce the read latency by one cycle.

[0074] The test cycle counter 140 is configured to start counting (the count value is denoted as counter) each time a test cycle is entered, and output the difference (denoted as sum_m) between the first fractional part values of the current test cycle data and the previous test cycle data. The purpose of the count value counter is to count the number of clock cycles included in the current test cycle. The difference sum_m is used to record the extra fractional part time in the previous test cycle. It can be understood that when entering the first test cycle, since there is no previous test cycle data, the difference sum_m of the first test cycle is 0 at this time. And in the next test cycle, the extra time of the previous test cycle needs to be subtracted.

[0075] Exemplarily, after the test cycle register 120 obtains a test cycle data, the test cycle counter 140 starts counting from 0 according to the beat of the FPGA clock cycle, and is cleared when the count reaches zero where the difference between the integer part value rate_n of the current test cycle data and the test cycle borrow rate_borrow is zero.

[0076] For example, if described by an expression, there is: when the count counter = rate_n - rate_borrow, counter is reset to 0. Wherein, rate_borrow is the borrow of the test cycle, indicating whether the part of the current test cycle less than T is enough to deduct the extra time of the previous test cycle, that is, whether there is a borrow when rate_m - sum_m, if there is a borrow rate_borrow = 1, so the integer part of the count counter of the current test cycle is decremented by 1.

[0077] As an alternative solution, after the count is cleared, when the next test cycle data arrives, the test cycle counter 140 will start counting again. At the same time, when entering each new test cycle, the test cycle counter 140 sets the signal fifo_rd of the test cycle register 120 and the timing data register 130 to 1 (that is, sets the read enable signal of the fifo to be valid). And, the start signal period_sop indicating the start of a test cycle is valid.

[0078] Furthermore, when the read enable of the fifo is valid, the test cycle counter 140 starts to perform a subtraction operation on the difference between the current test cycle data and the difference of the first decimal part value of the previous test cycle data. For example, in one implementation, the subtraction rule of the difference is as follows:

[0079] If the first decimal part value rate_m of the current test cycle is less than the difference sum_m of the previous test cycle, then borrow one bit from the integer part value of the current test cycle to update the new difference of the current test cycle, and at this time a valid count borrow rate_borrow (that is, rate_borrow is 1) will be generated. Otherwise, directly use the difference between the first decimal part value rate_m of the current test cycle and the difference sum_m of the previous test cycle as the updated difference.

[0080] The timing edge generator 150 is used to determine whether the timing clock (denoted as clk_en) is enabled according to the count and the second integer part value of the test cycle data in the same test cycle, and output the third decimal part value (denoted as clk_m) of the timing clock less than an integer multiple according to the difference and the second decimal part value.

[0081] Among them, the timing clock enable (i.e., clk_en = 1) indicates that in each test cycle, the time of an integer number of clock cycles T of the timing data has been reached. And the value of the third decimal part of the non-integer multiple timing clock is used to represent how much non-integer T time remains when an integer number of Ts of timing is reached in the current test cycle. Among them, the initial value of clk_m is 0.

[0082] For the determination method of the timing clock, exemplarily, in the same test cycle, when the difference between the value of the second integer part of the timing data and the timing data borrow is equal to the count of the test cycle data, described by an expression, that is, counter = timing_n - timing_borrow, then the timing clock enable is determined.

[0083] Specifically, it can be divided into two cases, namely no timing data borrow occurs (i.e., timing_borrow = 0) and timing data borrow occurs (i.e., timing_borrow = 1).

[0084] In one case, when timing_borrow = 0, if the value of the second integer part of the timing data is equal to the count of the current test cycle data (such as equal to 0), then the timing clock enable is determined. For example, as Figure 2 shown, in the first test cycle, timing = 1.25ns, timing_n = 0, timing_m = 2, sum_m = 0, timing_m - sum_m does not produce a carry (i.e., timing_borrow = 0), when counter = timing_n - timing_borrow = 0 - 0 = 0, clk_en = 1.

[0085] In another case, when timing_borrow = 1, if the difference between the value of the second integer part of the timing data and the timing data borrow is equal to the count of the current test cycle data, then the timing clock enable can also be determined. For example, as Figure 2 shown, in the second test cycle, timing = 5.625ns, timing_n = 1, timing_m = 1, sum_m = 3, timing_m - sum_m produces a carry (i.e., timing_borrow = 1), when counter = timing_n - timing_borrow = 1 - 1 = 0, clk_en = 1.

[0086] For the value of the third fractional part, it is related to the difference between the value of the first fractional part calculated in the current test period and the value of the second fractional part of the timing data in the same test period. When entering each test period, the fractional part value of the remaining fractional part of the integer timing clock starts to perform subtraction. For example, in one implementation, the subtraction operation rule of the third fractional part value is as follows:

[0087] In the same test period, when the value of the second fractional part of the timing data is greater than or equal to the difference between the first fractional part values, since no borrowing is required for subtraction, the value of the third fractional part is equal to the difference between the value of the second fractional part and the difference. Conversely, borrowing is required from the integer part value of the timing data for subtraction. Therefore, the value of the third fractional part is equal to the value of the second fractional part plus 8 and then subtracted by the difference.

[0088] For example, in the first test period, clk_m = timing_m - sum_m = 2 - 0 = 2; in the second test period, clk_m = timing_m - sum_m = 1 - 3, which is not enough to subtract. After borrowing, there is clk_m = timing_m + 8 - sum_m = 1 + 8 - 3 = 6, and so on.

[0089] It can be understood that when the timing clock within the custom test period is enabled, it means that data reading or output can be achieved.

[0090] The data generator 160 is used to generate parallel data with a preset bit width from the received one-bit pattern data according to the value of the third fractional part when the integer timing clock is enabled.

[0091] Among them, the parallel data (i.e., parall_data) can be described by bits with multiple bit widths. For example, it can be set to 2 bits to 8 bits, and the specific value can be set according to actual requirements. Taking 8 bits as an example, the parallel data can be described as [7:0], where 7 represents the highest bit and 0 represents the lowest bit.

[0092] In some implementations, when the timing clock is enabled, the data generator 160 determines the holding length of the pattern data (pattern_data) according to the size of the value of the third fractional part. Then, after determining the holding length, the bits from the highest bit to the corresponding bit of the holding length in the preset bit width are set to the pattern data, and the values of the remaining bit widths except the holding length are set to the highest bit value of the pattern data input in the previous test period, thereby generating parallel data with a preset bit width.

[0093] Taking 8-bit preset bit width as an example, when clk_en is 1, according to the value of clk_m, pattern_data is placed on bits [7:clk_m] of the parallel (parall_data) data; the remaining bits maintain the 7th bit data of the previous parall_data data. For example, when the value of clk_m is 2 and pattern_data = 1, and the previous parall_data data is 8’b0000_0000 in binary, then for the current test cycle, bits 3 to 8 of the parallel data are: parall_data[7:2]=6’b111111, and bits 1 to 2 of the parallel data are: parall_data[1:0]=2’b00. Thus, the 8-bit wide parallel data can be combined to be 8’b1111_1100, and correspondingly, its corresponding hexadecimal is 8’hfc.

[0094] The converter 170 is used to convert the parallel data into serial data and output it using a preset multiple-frequency clock of the working frequency of the FPGA. It can be understood that by converting the generated parallel data into serial output through this converter 170, continuous output of multiple-bit data can be achieved within one test cycle.

[0095] For example, in one implementation, the preset multiple-frequency clock can be adaptively set according to the bit width of the parallel data, etc. For example, when the bit width of the parallel data is 8 bits, it can be set as a quadruple-frequency clock of the reference signal (denoted as clk) at this time (such as Figure 1 the clk quadruple-frequency signal shown), so that one bit of data (denoted as data_out) is output at each rising edge and falling edge of each clk, thus completing the output of 8-bit data under a quadruple-frequency clock.

[0096] To verify the feasibility of the moment generator of the present application, as Figure 2 shown, by selecting a working frequency of 2000 MHz, the clock period T is 5 ns, as the clk signal, and 4 test cycles and timing data are set, which are respectively: the data of the first test cycle is 8.125 ns, and the first timing data is 1.25 ns; the second test cycle is 10.625 ns, the second timing data is 5.625 ns, the third test cycle is 7.5 ns, the third timing data is 5 ns, the fourth test cycle is 12.5 ns, and the fourth timing data is 8.125 ns. Within each test cycle, from the waveform of the generated parallel data, it can be seen that 8-bit data can be output within each 5 ns. Therefore, it can be shown that the minimum time resolution of this timing generator 10 can be improved to 1 / 8 of the clock period T of the FPGA.

[0097] The FPGA-based timing generator 10 of the present application collaborates by utilizing the test cycle buffer 120, the timing data buffer 130, the test cycle counter 140, the timing edge generator 150, the data generator 160, and the converter 170. On the premise of using fewer Look-Up Table (LUT) resources and storage resources, it can achieve improving the time resolution of the timing generator 10 to 1 / 8 of the FPGA working cycle T at the same frequency, thereby enabling more precise timing control. Moreover, by adopting the fifo unit in the FWFT mode, the delay from reading data from the fifo to generating the timing clock enable signal and accumulating the fractional part of the timing information is only one clock cycle, achieving the effect of low latency.

[0098] Figure 3 FIG. shows a flowchart of an FPGA-based timing generation method according to an embodiment of the present application. Exemplarily, the FPGA-based timing generation method includes:

[0099] S100, obtaining the first integer part value and the first fractional part value of each preset test cycle data calculated based on the working frequency of the FPGA. Among them, this step is mainly stored and output by the above-mentioned test cycle buffer 120 for the first integer part value and the first fractional part value.

[0100] S200, obtaining the second integer part value and the second fractional part value of each preset timing data calculated based on the working frequency. Among them, this step is mainly stored and output by the above-mentioned timing data buffer 130 for the second integer part value and the second fractional part value.

[0101] S300, each time entering a test cycle, starting to count according to the working frequency, and outputting the difference between the first fractional part values of the current test cycle data and the previous test cycle data. Among them, this step is mainly implemented by the above-mentioned test cycle counter 140.

[0102] S400, determining whether the integer timing clock is enabled according to the count and the second integer part value of the test cycle data in the same test cycle, and outputting the third fractional part value of the unfilled integer timing clock according to the difference and the second fractional part value. Among them, this step is mainly implemented by the above-mentioned timing edge generator 150.

[0103] S500, when the timing clock is enabled, generating parallel data with a preset bit width according to the third fractional part value for the received one-bit pattern data. Among them, this step is mainly implemented by the above-mentioned data generator 160.

[0104] The S600 converts the parallel data into serial data and outputs the serial data by using a preset frequency - multiplied clock of the working frequency. Among them, this step is mainly implemented by the above - mentioned converter 170.

[0105] It can be understood that the timing generation method of this embodiment is implemented by each module in the timing generator 10 of the above - mentioned embodiment. Therefore, for the specific implementation details of each step, reference can be made to the corresponding records in the above - mentioned embodiment, and they will not be repeated here. In addition, the optional items in the above - mentioned embodiment are also applicable to this embodiment, so they will not be repeated here.

[0106] This application also provides a terminal device. Exemplarily, an FPGA is included in the terminal device. The terminal device is used to implement the timing generation method of the embodiment of this application by using the FPGA.

[0107] This application also provides a computer - readable storage medium for storing the computer program used in the above - mentioned terminal device. For example, the computer - readable storage medium may include, but is not limited to: USB flash drives, mobile hard disks, read - only memories (ROM, Read - Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs and other media that can store program codes.

[0108] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and structure diagrams in the drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of this application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code. A module, a program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the blocks may occur in a different order from that marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the structure diagram and / or flowchart, and the combination of blocks in the structure diagram and / or flowchart, can be implemented by a dedicated hardware - based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0109] In addition, in each embodiment of this application, each functional module or unit may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0110] If a function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of this application.

[0111] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application.

Claims

1. A timing generator based on FPGA, characterized in that Including: A clock source for providing the operating frequencies required by other units in the FPGA; A test cycle buffer for sequentially buffering each test cycle data and outputting the first integer part value and the first fractional part value of each of the test cycle data calculated based on the operating frequency; A timing data buffer for sequentially buffering each timing data and outputting the second integer part value and the second fractional part value of each of the timing data calculated based on the operating frequency; A test cycle counter for starting to count each time a test cycle is entered, and when the read enable signal of the test cycle buffer is valid, performing a subtraction operation on the difference between the fractional part values of the current test cycle data and the previous test cycle data and outputting the result, including: determining whether to borrow a bit from the integer part value of the current test cycle for the subtraction operation according to the magnitude of the difference between the fractional part value of the current test cycle and the previous test cycle; A timing edge generator for determining whether the timing clock is enabled according to the count and the second integer part value of the test cycle data in the same test cycle, and outputting the third fractional part value of the timing clock that is not an integer multiple based on the difference and the second fractional part value; A data generator for generating parallel data with a preset bit width from the received one-bit pattern data according to the third fractional part value when the timing clock is enabled; A converter for converting the parallel data into serial data and outputting it using a preset multiple-frequency clock of the operating frequency; 2. The timing generator according to claim 1, wherein The test cycle counter is further configured to clear when the count reaches zero, where the difference between the integer part value of the current test cycle data and the test cycle borrow; 3. The timing generator according to claim 2, characterized in that, The test cycle counter is further configured to, after the count is cleared, restart counting when the next test cycle data arrives; meanwhile, when each new test cycle is entered, making the read enable signals of the test cycle buffer and the timing data buffer valid, and making the start signal indicating the start of a test cycle valid; 4. The timing generator according to claim 3, wherein The test cycle counter is further configured to determine whether to borrow a bit from the integer part value of the current test cycle for the subtraction operation according to the magnitude of the difference between the fractional part value of the current test cycle and the previous test cycle, specifically including: If the fractional part value of the current test cycle is less than the difference of the previous test cycle, then updating the difference of the current test cycle by borrowing one bit from the integer part value of the current test cycle; otherwise, directly using the difference between the fractional part value of the current test cycle and the difference of the previous test cycle as the updated difference; 5. The timing generator according to claim 1, characterized in that, The test cycle buffer is specifically configured to divide the test cycle data by the clock cycle corresponding to the operating frequency, and use the obtained quotient and remainder as the first integer part value and the first fractional part value respectively.

6. The timing generator according to claim 1, wherein The timing data buffer is specifically configured to divide the timing data by the clock cycle corresponding to the operating frequency, and use the quotient and the remainder obtained as the second integer part value and the second fractional part value respectively.

7. The timing generator according to claim 1, wherein The timing edge generator is specifically configured to determine the timing clock enable when the difference between the value of the second integer part and the borrow of the timing data in the same test cycle is equal to the count of the test cycle data. And use the difference between the difference value and the second fractional part value as the third fractional part value of the timing clock that is less than an integer multiple.

8. The timing generator according to claim 1, wherein The data generator is specifically configured to determine the holding length of the pattern data according to the magnitude of the third fractional part value when the timing clock is enabled. And set the bits from the highest bit to the bit corresponding to the holding length in the preset bit width to the pattern data, and set the values of the remaining bit width except the holding length to the highest bit value of the pattern data input in the previous test cycle, so as to generate the parallel data with the preset bit width.

9. The timing generator according to claim 1, wherein The value of the test cycle data is not less than the clock cycle corresponding to the operating frequency. The value range of the timing data is: test rate ~ T / 8; where test rate is the test cycle and T is the clock cycle.

10. A timing generation method based on FPGA, characterized in that, Applied to the timing generator according to any one of claims 1 to 9; the method includes: Obtain the first integer part value and the first fractional part value of each preset test cycle data calculated based on the operating frequency of the FPGA. Obtain the second integer part value and the second fractional part value of each preset timing data calculated based on the operating frequency. Each time a test cycle is entered, start counting according to the operating frequency, and when the read enable signal of the test cycle buffer is valid, perform a subtraction operation on the difference between the first fractional part values of the current test cycle data and the previous test cycle data and output it, including: determining whether to borrow from the first integer part value of the current test cycle for subtraction according to the magnitude of the difference between the first fractional part value of the current test cycle and the previous test cycle. Determine whether the timing clock is enabled according to the count of the test cycle data and the second integer part value in the same test cycle, and output the third fractional part value of the timing clock that is less than an integer multiple according to the difference value and the second fractional part value. When the timing clock is enabled, generate parallel data with a preset bit width from the received one-bit pattern data according to the third fractional part value. Convert the parallel data into serial data and output it using the preset multiple-frequency clock of the operating frequency.

11. A terminal device, characterized in that, The terminal device includes an FPGA, and the terminal device is used to implement the FPGA-based timing generation method according to claim 10.

12. A computer-readable storage medium, characterized in that, It stores a computer program, and when the computer program is executed, it implements the FPGA-based timing generation method according to claim 10.

Images