NAND graph optimization method, device, computer device and readable storage medium

Abstract

The present application relates to a NAND graph optimization method, apparatus, computer device, and readable storage medium. The method includes: obtaining a NAND graph to be optimized and each optimization method sequence; extracting a feature matrix corresponding to the NAND graph to be optimized based on a graph neural network, and determining a group of feature transformation models corresponding to each optimization method sequence; performing feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix, and determining a quality parameter set of each optimized feature matrix according to a multi-layer perceptron; determining a target optimization method sequence from each optimization method sequence according to each quality parameter set, and optimizing the NAND graph to be optimized according to the target optimization method sequence to obtain a target optimized NAND graph; the target optimized NAND graph is used to determine the logical relationship of an electronic device. Using this method can improve the efficiency of the NAND graph optimization method.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, and in particular, to a NAND graph optimization method, device, computer device, and computer-readable storage medium. Background Art

[0002] In the field of electronic design automation technology, by optimizing a NAND graph and performing process mapping based on the optimized NAND graph to obtain an electronic device, it is possible to optimize the electronic device corresponding to the NAND graph and improve the performance of the electronic device.

[0003] The current NAND graph optimization method optimizes the NAND graph to be optimized according to each optimization method sequence to obtain each candidate NAND graph. Each candidate NAND graph is split based on the process mapping process, and the process database is traversed to query each target process element corresponding to each candidate NAND sub-graph after splitting. A quality parameter set of the candidate NAND graph is determined according to each target process element, and the target optimized NAND graph with the best quality is determined based on each quality parameter set.

[0004] However, the current NAND graph optimization method requires a lot of time to determine the target candidate NAND graph with the best quality in the case of multiple optimization method sequences. Therefore, the efficiency of the current NAND graph optimization method is low. Summary of the Invention

[0005] Based on this, it is necessary to provide a NAND graph optimization method, device, computer device, and computer-readable storage medium for solving the above technical problems.

[0006] In a first aspect, this application provides a NAND graph optimization method, including:

[0007] Obtain the NAND graph to be optimized and each optimization method sequence;

[0008] Extract the feature matrix corresponding to the NAND graph to be optimized based on a graph neural network, and determine a group of feature transformation models corresponding to each optimization method sequence;

[0009] Perform feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix, and determine the quality parameter set of each optimized feature matrix according to a multi-layer perceptron;

[0010] Determine a target optimization method sequence from each optimization method sequence according to each quality parameter set, and optimize the NAND graph to be optimized according to the target optimization method sequence to obtain a target optimized NAND graph; the target optimized NAND graph is used to determine the logical relationship of the electronic device.

[0011] In one embodiment, before extracting the feature matrix corresponding to the NAND graph to be optimized based on the graph neural network, the method further includes:

[0012] Obtain an initial sample and a non-graph data set, and based on a logic synthesis tool and the initial sample and the non-graph data set, determine a set of sample quality parameters corresponding to each optimization method;

[0013] Label the initial sample and the non-graph data set based on each set of sample quality parameters to obtain each sample and non-graph data set;

[0014] Train an initial graph neural network, an initial feature transformation model corresponding to each optimization method, and an initial multi-layer perceptron based on each sample and non-graph data set to obtain a graph neural network, each feature transformation model, and a multi-layer perceptron.

[0015] In one embodiment, the extracting the feature matrix corresponding to the to-be-optimized and non-graph based on the graph neural network includes:

[0016] Extract the logical structure of the to-be-optimized and non-graph through a standard logic synthesis tool to obtain an initial logical relationship set of the to-be-optimized and non-graph;

[0017] Update the node set in the initial logical relationship set based on the logical feature vector to obtain a logical relationship set of the to-be-optimized and non-graph;

[0018] Extract features from the logical relationship set based on the graph neural network to obtain the feature matrix of the to-be-optimized and non-graph.

[0019] In one embodiment, the determining the set of feature transformation models corresponding to each sequence of optimization methods includes:

[0020] For each sequence of optimization methods, in the feature transformation models of each optimization method, determine the initial target feature transformation models corresponding to each initial target optimization method in the sequence of optimization methods;

[0021] Combine the initial target feature transformation models in the order of each initial target optimization method in the sequence of optimization methods to obtain a set of feature transformation models.

[0022] In one embodiment, the performing feature transformation on the feature matrix based on each set of feature transformation models to obtain each optimized feature matrix includes:

[0023] For each set of feature transformation models, perform feature transformation on the feature matrix in the order of each initial target feature transformation model in the set of feature transformation models to obtain an optimized feature matrix.

[0024] In one embodiment, the determining the target optimization method sequence in each sequence of optimization methods according to each set of quality parameters includes:

[0025] Input each of the optimized feature matrices into a multi-layer perceptron, and perform prediction processing on the optimized feature matrices through the multi-layer perceptron to obtain a set of quality parameters for the optimized feature matrices.

[0026] In one embodiment, the determining the target optimization mode sequence from each of the optimization mode sequences according to each set of quality parameters includes:

[0027] Determine the quality score corresponding to each set of quality parameters based on a preset evaluation criterion;

[0028] Determine the highest quality score among each of the quality scores as the target quality score, and determine the optimization mode sequence corresponding to the quality score as the target optimization mode sequence.

[0029] In a second aspect, the present application also provides a NAND optimization device, including:

[0030] An acquisition module, configured to acquire a NAND to be optimized and each optimization mode sequence;

[0031] An extraction module, configured to extract a feature matrix corresponding to the NAND to be optimized based on a graph neural network, and determine a group of feature transformation models corresponding to each optimization mode sequence;

[0032] An optimization module, configured to perform feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix, and determine a set of quality parameters for each optimized feature matrix according to a multi-layer perceptron;

[0033] A determination module, configured to determine a target optimization mode sequence from each of the optimization mode sequences according to each set of quality parameters, and optimize the NAND to be optimized according to the target optimization mode sequence to obtain a target optimized NAND; the target optimized NAND is used to determine the logical relationship of an electronic device.

[0034] In a third aspect, the present application also provides a computer device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0035] Acquire a NAND to be optimized and each optimization mode sequence;

[0036] Extract a feature matrix corresponding to the NAND to be optimized based on a graph neural network, and determine a group of feature transformation models corresponding to each optimization mode sequence;

[0037] Perform feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix, and determine a set of quality parameters for each optimized feature matrix according to a multi-layer perceptron;

[0038] Determine a target optimization mode sequence in each of the optimization mode sequences according to each set of quality parameters, and optimize the to-be-optimized NAND graph according to the target optimization mode sequence to obtain a target optimized NAND graph; the target optimized NAND graph is used to determine the logical relationship of the electronic device.

[0039] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0040] Obtain the to-be-optimized NAND graph and each optimization mode sequence;

[0041] Extract the feature matrix corresponding to the to-be-optimized NAND graph based on a graph neural network, and determine a set of feature transformation models corresponding to each optimization mode sequence;

[0042] Perform feature transformation on the feature matrix based on each set of feature transformation models to obtain each optimized feature matrix, and determine the set of quality parameters of each optimized feature matrix according to a multi-layer perceptron;

[0043] Determine a target optimization mode sequence in each of the optimization mode sequences according to each set of quality parameters, and optimize the to-be-optimized NAND graph according to the target optimization mode sequence to obtain a target optimized NAND graph; the target optimized NAND graph is used to determine the logical relationship of the electronic device.

[0044] In a fifth aspect, the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, the following steps are implemented:

[0045] Obtain the to-be-optimized NAND graph and each optimization mode sequence;

[0046] Extract the feature matrix corresponding to the to-be-optimized NAND graph based on a graph neural network, and determine a set of feature transformation models corresponding to each optimization mode sequence;

[0047] Perform feature transformation on the feature matrix based on each set of feature transformation models to obtain each optimized feature matrix, and determine the set of quality parameters of each optimized feature matrix according to a multi-layer perceptron;

[0048] Determine a target optimization mode sequence in each of the optimization mode sequences according to each set of quality parameters, and optimize the to-be-optimized NAND graph according to the target optimization mode sequence to obtain a target optimized NAND graph; the target optimized NAND graph is used to determine the logical relationship of the electronic device.

[0049] The above NAND graph optimization method, device, computer device, computer-readable storage medium, and computer program product obtain a NAND graph to be optimized and each optimization method sequence; extract a feature matrix corresponding to the NAND graph to be optimized based on a graph neural network, and determine a group of feature transformation models corresponding to each optimization method sequence; perform feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix, and determine a quality parameter set of each optimized feature matrix according to a multi-layer perceptron; determine a target optimization method sequence from each optimization method sequence according to each quality parameter set, and optimize the NAND graph to be optimized according to the target optimization method sequence to obtain a target optimized NAND graph; the target optimized NAND graph is used to determine the logical relationship of an electronic device. By using this method, by directly optimizing the feature matrix corresponding to the NAND graph to be optimized and determining the quality parameter set of each optimized feature matrix, the optimization effect of each optimized feature matrix can be quickly determined only by transforming the feature matrix corresponding to the NAND graph to be optimized once, avoiding traversing the process database multiple times and reducing the time for determining each target process component. Then, based on each quality parameter set, a target optimization method sequence is determined, and the NAND graph to be optimized is optimized according to the target optimization method sequence, realizing the rapid optimization of the NAND graph to be optimized and improving the efficiency of the NAND graph optimization method. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other related drawings can be obtained without creative efforts based on these drawings.

[0051] Figure 1 It is a schematic flowchart of the NAND graph optimization method in an embodiment;

[0052] Figure 2 It is a schematic diagram of the NAND graph to be optimized in an exemplary embodiment;

[0053] Figure 3 It is a schematic flowchart of training an initial graph neural network, each initial feature transformation model, and an initial multi-layer perceptron in an embodiment;

[0054] Figure 4 It is an exemplary diagram of rewriting or restructuring in an exemplary embodiment;

[0055] Figure 5 It is a schematic diagram of balance in an exemplary embodiment;

[0056] Figure 6 It is a schematic diagram of re-replacement in an exemplary embodiment;

[0057] Figure 7 Schematic diagram of redundancy removal in an exemplary embodiment;

[0058] Figure 8 Flow schematic diagram of extracting a feature matrix in an embodiment;

[0059] Figure 9 Schematic diagram of an attention mechanism in an exemplary embodiment;

[0060] Figure 10 Flow schematic diagram of determining a group of feature transformation models in an embodiment;

[0061] Figure 11 Schematic diagram of the structure of a transformer module in an initial target feature transformation model in an exemplary embodiment;

[0062] Figure 12 Flow schematic diagram of determining a sequence of target optimization methods in an embodiment;

[0063] Figure 13 Flow schematic diagram of a NAND graph optimization method in another embodiment;

[0064] Figure 14 Structure block diagram of a NAND graph optimization device in an embodiment;

[0065] Figure 15 Internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0066] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0067] In electronic design automation, the process of logic synthesis includes logic transformation, logic optimization, and technology mapping. Logic transformation is to convert logical expressions in other forms into logical expressions convenient for processing. Logic optimization is to convert logical expressions into "optimal implementations", considering the best in terms of parameters such as complexity, area, and delay. In order to obtain these indicators and parameters, technology mapping can be used to convert gate circuits into a standard cell netlist of a specified process, and physical design analysis can be used to obtain parameters such as delay and area based on the cell library. Logic optimization is to simplify existing logical expressions and optimize the depth, activity, and number of nodes of logical functions on the premise of consistent logical functions, which respectively correspond to the performance, power consumption, and area of the circuit.

[0068] In the field of electronic design automation technology, a NAND graph is a common way of logical expression. By optimizing the NAND graph, the logical optimization of electronic devices can be achieved. Specifically, by optimizing the NAND graph and performing process mapping based on the optimized NAND graph, an electronic device is obtained, improving the performance of the electronic device.

[0069] Current NAND graph optimization methods optimize the NAND graph to be optimized based on each optimization method sequence to obtain each candidate NAND graph. According to the process mapping process, each candidate NAND graph is split to obtain each candidate NAND sub-graph corresponding to the candidate NAND graph. Then, for each candidate NAND sub-graph, each process element in the process database is traversed to query the target process element that matches the candidate NAND sub-graph. According to the target process elements corresponding to the candidate NAND graph, the netlist corresponding to the candidate NAND graph is determined, and the quality parameter set corresponding to the candidate NAND graph is determined according to the netlist.

[0070] However, current NAND graph optimization methods require a large amount of time to split the candidate NAND graph and determine the target process elements of each candidate NAND sub-graph in the case of multiple optimization method sequences, so as to determine each quality parameter set. Therefore, the efficiency of current NAND graph optimization methods is low.

[0071] Based on the above traditional technology, the embodiments of the present application provide a NAND graph optimization method. By directly optimizing the feature matrix corresponding to the NAND graph to be optimized and determining the quality parameter sets of each optimized feature matrix, only by converting the feature matrix corresponding to the NAND graph to be optimized once, the optimization effects of each optimized feature matrix can be quickly clarified, avoiding traversing the process database multiple times and reducing the time for determining each target process element. Then, based on each quality parameter set, the target optimization method sequence is determined, and the NAND graph to be optimized is optimized by the target optimization method sequence, realizing the rapid optimization of the NAND graph to be optimized and improving the efficiency of the NAND graph optimization method.

[0072] Moreover, by directly optimizing the feature matrix and being able to quickly determine the quality parameter sets of the optimized feature matrix based on the neural network with a simple structure of the multi-layer perceptron, clarifying the optimization effects of each optimization method sequence, the target optimization method sequence can be quickly determined, realizing the rapid optimization of the NAND graph to be optimized and improving the efficiency of the NAND graph optimization method.

[0073] In one embodiment, as Figure 1 shown, a NAND graph optimization method is provided. In the embodiments of the present application, this method is described by taking its application to a computer device as an example. The embodiments of the present application do not limit the execution device of the NAND graph optimization method, including the following steps 102 to step 108:

[0074] Step 102, obtain the NAND graph to be optimized and each optimization method sequence.

[0075] In implementation, the computer device obtains the AND-NOT graph to be optimized corresponding to the electronic device. This AND-NOT graph to be optimized represents the initial logical relationship of the electronic device. Since manual design takes into account various factors, it may cause the AND-NOT graph to be optimized not to meet the requirements of process mapping. Therefore, it is necessary to optimize the AND-NOT graph to be optimized. The computer device obtains each sequence of optimization methods. The sequence of optimization methods provides optimization methods for the AND-NOT graph to be optimized.

[0076] Specifically, when the AND-NOT graph to be optimized corresponding to the electronic device needs to be optimized, the computer device obtains the AND-NOT graph to be optimized corresponding to the electronic device. Then, in response to the optimization request of the AND-NOT graph to be optimized, the computer device obtains the full set of undetermined optimization method sequences from the database and determines each sequence of optimization methods among the undetermined optimization method sequences.

[0077] In an alternative embodiment, the computer device displays each undetermined optimization method sequence. In response to the triggering operation of the undetermined optimization method sequence, the computer device determines the triggered undetermined optimization method sequence as the sequence of optimization methods.

[0078] In an exemplary embodiment, the target user needs to produce an electronic device. The target user designs the AND-NOT graph to be optimized corresponding to the electronic device. The computer device obtains the AND-NOT graph to be optimized, as Figure 2 shown. Figure 2 is a schematic diagram of the AND-NOT graph to be optimized in an exemplary embodiment. Then, in response to the optimization request of the AND-NOT graph to be optimized, the computer device obtains all the optimization methods and displays each optimization method. The target user determines each initial target optimization method among the optimization methods and combines each initial target optimization method to obtain a sequence of optimization methods. Then, the target user repeats the above operations to generate each sequence of optimization methods and submits each sequence of optimization methods to the computer device. The computer device obtains each sequence of optimization methods.

[0079] Step 104, extract the feature matrix corresponding to the AND-NOT graph to be optimized based on the graph neural network, and determine the group of feature transformation models corresponding to each sequence of optimization methods.

[0080] In implementation, the computer device preprocesses the AND-NOT graph to be optimized to obtain the logical relationship set of the AND-NOT graph to be optimized. Then, the computer device extracts the feature matrix of the AND-NOT graph to be optimized in the logical relationship set based on the graph neural network. For each sequence of optimization methods, the computer device combines the feature transformation models corresponding to the sequence of optimization methods according to each feature transformation model, so as to perform feature transformation on the feature matrix based on the group of feature transformation models.

[0081] In an exemplary embodiment, an initial graph neural network, each initial feature transformation model, and an initial multi-layer perceptron are pre-set in a computer device. The computer device obtains each sample and non-graph data set, and trains the initial graph neural network, each initial feature transformation model, and the initial multi-layer perceptron based on each sample and non-graph data set to obtain a graph neural network, each feature transformation model, and a multi-layer perceptron. Then, the computer device extracts the logical results of the to-be-optimized and non-graph to obtain an initial logical relationship set, and updates the initial logical relationship set based on the logical feature vectors to obtain a logical relationship set. The computer device extracts features of the to-be-optimized and non-graph based on the graph neural network to obtain a feature matrix of the to-be-optimized and non-graph.

[0082] Step 106: Perform feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix, and determine a quality parameter set of each optimized feature matrix according to the multi-layer perceptron.

[0083] In implementation, the computer device performs feature transformation on the feature matrix based on each group of feature transformation models, so as to optimize the feature matrix and obtain an optimized feature matrix. Then, the computer device inputs each optimized feature matrix into the multi-layer perceptron, and determines a quality parameter set of the optimized feature matrix through the multi-layer perceptron.

[0084] Step 108: Determine a target optimization method sequence from each optimization method sequence according to each quality parameter set, and optimize the to-be-optimized and non-graph according to the target optimization method sequence to obtain a target optimized and non-graph.

[0085] Among them, the target optimized and non-graph is used to determine the logical relationship of the electronic device. Each target optimization method is included in the target optimization method sequence. The quality parameter set characterizes the quality of the optimization method sequence for optimizing the feature matrix.

[0086] In implementation, the computer device determines the quality scores of each optimization method sequence based on each quality parameter set. Then, the computer device determines the target optimization method sequence from each optimization method sequence based on each quality score. The computer device optimizes the to-be-optimized and non-graph through each target optimization method according to the order of the target optimization method sequence to obtain a target optimized and non-graph. The target user can produce an electronic device based on the target optimized and non-graph, so as to achieve the purpose of optimizing the electronic device.

[0087] In an exemplary embodiment, evaluation criteria are preset in the computer device. The computer device processes the quality parameter set corresponding to each optimization method sequence based on the evaluation criteria to obtain the quality score corresponding to the optimization method sequence. Then, the computer device determines the highest quality score among the quality scores as the target quality score and determines the optimization method sequence corresponding to the target quality score as the target optimization method sequence. The computer device optimizes the to-be-optimized NAND graph through a logic synthesis tool and the target optimization method sequence to obtain the target optimized NAND graph. Then, the computer device performs process mapping on the target optimized NAND graph according to the logic synthesis tool to manufacture the electronic device corresponding to the target optimized NAND graph.

[0088] In the above NAND graph optimization method, by directly optimizing the feature matrix corresponding to the to-be-optimized NAND graph and determining the quality parameter set of each optimized feature matrix, it is only necessary to transform the feature matrix corresponding to the to-be-optimized NAND graph once, and the optimization effects of each optimized feature matrix can be quickly determined, avoiding traversing the process database multiple times and reducing the time for determining each target process element. Then, based on each quality parameter set, the target optimization method sequence is determined, and the to-be-optimized NAND graph is optimized by the target optimization method sequence, realizing the rapid optimization of the to-be-optimized NAND graph and improving the efficiency of the NAND graph optimization method.

[0089] In an exemplary embodiment, before extracting the feature matrix based on the graph neural network, it is necessary to first train the initial graph neural network, the initial feature transformation models corresponding to each optimization method, and the initial multi-layer perceptron to obtain the graph neural network, each feature transformation model, and the multi-layer perceptron. As Figure 3 shown, before step 104 is executed, the specific processing procedure of this NAND graph optimization method further includes steps 302 to 306. Among them:

[0090] Step 302, obtain the initial sample NAND graph data set, and based on the logic synthesis tool and the initial sample NAND graph data set, determine the sample quality parameter set corresponding to each optimization method.

[0091] In implementation, the computer device obtains each initial sample NAND graph from the database to obtain the initial sample NAND graph data set. Then, for each optimization method, the computer device optimizes the initial sample NAND graph data set through the logic synthesis tool and this optimization method to obtain the initial optimized sample NAND graph data set corresponding to this optimization method. For each initial optimized sample NAND graph data set corresponding to each optimization method, the computer device determines the sample quality parameter set of each initial sample NAND graph in this initial optimized sample NAND graph data set according to a preset logic synthesis tool (standard logic synthesis tool).

[0092] In an exemplary embodiment, the optimization methods include rewriting, balancing, restructuring, re - substitution, and redundancy removal. Rewriting is a method of simplifying or transforming a logical expression by applying equivalent transformations. Restructuring refers to making major adjustments to the structure of the NAND graph to meet different design requirements or optimization goals. Figure 4 It is an example graph for rewriting or restructuring in an exemplary embodiment. For example, Figure 4 as shown, by rewriting the NAND graph, the number of input lines of the NAND graph is reduced. Balancing means adjusting the workload or delay of each part in the NAND graph so that the performance of the entire circuit is more uniform. Figure 5 It is a schematic diagram of balancing in an exemplary embodiment. As Figure 5 shown, by adjusting the structure of the NAND graph, the logical structure of the NAND graph becomes more uniform. Figure 5 The cover cone in [reference] is a set that starts from a node and covers all input paths and related nodes of that node. Re - substitution is an optimization technique that simplifies the circuit by replacing an existing sub - graph with an equivalent, more concise, or more efficient sub - graph. Figure 6 It is a schematic diagram of re - substitution in an exemplary embodiment. Redundancy removal means identifying and deleting redundant parts in the NAND graph that do not contribute to the final output. Redundant parts may be due to extra logic gates or sub - graphs generated during the design process. Figure 7 It is a schematic diagram of re - substitution in an exemplary embodiment.

[0093] The computer device obtains each initial sample NAND graph from the database to get an initial sample NAND graph dataset. Then, based on a logic synthesis tool, the computer device performs rewriting processing on each initial sample NAND graph in the initial sample NAND graph dataset to obtain each rewritten initial optimized sample NAND graph. The computer device performs restructuring processing on each initial sample NAND graph in the initial sample NAND graph dataset based on a logic synthesis tool to obtain each restructured initial optimized sample NAND graph. Then, based on a logic synthesis tool, the computer device performs balancing processing on each initial sample NAND graph in the initial sample NAND graph dataset to obtain each balanced initial optimized sample NAND graph. The computer device performs re - substitution processing on each initial sample NAND graph in the initial sample NAND graph dataset based on a logic synthesis tool to obtain each re - substituted initial optimized sample NAND graph. Then, based on a logic synthesis tool, the computer device performs redundancy removal processing on each initial sample NAND graph in the initial sample NAND graph dataset to obtain each initial optimized sample NAND graph after redundancy removal.

[0094] The computer device determines the rewritten quality parameter sets of each initial optimization sample and non-graph rewritten samples based on the logic synthesis tool. Then, the computer device determines the reconstructed quality parameter sets of each initial optimization sample and non-graph reconstructed samples based on the logic synthesis tool. The computer device determines the balanced quality parameter sets of each initial optimization sample and non-graph balanced samples based on the logic synthesis tool. Then, the computer device determines the re-replaced quality parameter sets of each initial optimization sample and non-graph re-replaced samples based on the logic synthesis tool. The computer device determines the redundancy-removed quality parameter sets of each initial optimization sample and non-graph redundancy-removed samples based on the logic synthesis tool.

[0095] Step 304: Label the initial samples and non-graph data sets based on each sample quality parameter set to obtain each sample and non-graph data set.

[0096] In implementation, the computer device copies the initial samples and non-graph data sets according to the number of optimization methods to obtain each initial sample and non-graph data set. Then, the computer device labels each initial sample and non-graph data set according to the sample quality parameter set corresponding to each optimization method to obtain the sample and non-graph data set.

[0097] In an exemplary embodiment, since the optimization methods include rewriting, balancing, reconstruction, re-replacement, and redundancy removal. Therefore, the computer device copies five sets of initial samples and non-graph data sets to obtain each sample and non-graph data set. Each sample quality parameter set is the rewritten sample quality parameter set, the reconstructed sample quality parameter set, the balanced quality parameter set, the re-replaced sample quality parameter set, and the redundancy-removed sample quality parameter set respectively. The computer device labels the first set of initial samples and non-graph data sets based on the rewritten sample quality parameter set to obtain the rewritten sample and non-graph data set. Specifically, the rewritten sample quality parameter set contains the rewritten sample quality parameter subsets of each initial sample and non-graph. The computer device labels each initial sample and non-graph based on the rewritten sample quality parameter subset corresponding to each initial sample and non-graph to obtain the rewritten sample and non-graph.

[0098] Then, the computer device labels the second set of initial samples and non-graph data sets based on the reconstructed sample quality parameter set to obtain the reconstructed sample and non-graph data set. The computer device labels the third set of initial samples and non-graph data sets based on the balanced sample quality parameter set to obtain the balanced sample and non-graph data set. The computer device labels the fourth set of initial samples and non-graph data sets based on the re-replaced sample quality parameter set to obtain the re-replaced sample and non-graph data set. The computer device labels the fifth set of initial samples and non-graph data sets based on the redundancy-removed sample quality parameter set to obtain the redundancy-removed sample and non-graph data set.

[0099] Step 306: Train the initial graph neural network, the initial feature transformation models corresponding to each optimization method, and the initial multi-layer perceptron based on each sample and the non-graph dataset to obtain the graph neural network, each feature transformation model, and the multi-layer perceptron.

[0100] In implementation, the computer device trains the initial graph neural network, the initial feature transformation model corresponding to this optimization method, and the initial multi-layer perceptron based on the sample corresponding to each optimization method and the non-graph dataset to obtain the graph neural network, the feature transformation model corresponding to this optimization method, and the multi-layer perceptron.

[0101] Specifically, the optimization methods include five types: rewriting, balancing, restructuring, re-replacement, and redundancy removal. Therefore, each sample and the non-graph dataset also include the rewriting sample and the non-graph dataset, the balancing sample and the non-graph dataset, the restructuring sample and the non-graph dataset, the re-replacement sample and the non-graph dataset, and the redundancy removal sample and the non-graph dataset. The initial graph neural network, the initial feature transformation model, and the initial multi-layer perceptron are pre-set in the computer device. The computer device copies the initial feature transformation model according to the number of optimization methods to obtain the initial feature transformation models corresponding to each optimization method. Then, the computer device trains the initial graph neural network, the initial feature transformation model corresponding to rewriting, and the initial multi-layer perceptron based on the rewriting sample and the non-graph dataset to obtain the trained initial graph neural network, the feature transformation model corresponding to rewriting, and the trained initial multi-layer perceptron. The computer device trains the initial graph neural network, the initial feature transformation model corresponding to restructuring, and the initial multi-layer perceptron based on the restructuring sample and the non-graph dataset to obtain the trained initial graph neural network, the feature transformation model corresponding to restructuring, and the trained initial multi-layer perceptron. The computer device trains the initial graph neural network, the initial feature transformation model corresponding to balancing, and the initial multi-layer perceptron based on the balancing sample and the non-graph dataset to obtain the trained initial graph neural network, the feature transformation model corresponding to balancing, and the trained initial multi-layer perceptron. The computer device trains the initial graph neural network, the initial feature transformation model corresponding to re-replacement, and the initial multi-layer perceptron based on the re-replacement sample and the non-graph dataset to obtain the trained initial graph neural network, the feature transformation model corresponding to re-replacement, and the trained initial multi-layer perceptron. The computer device trains the initial graph neural network, the feature transformation model corresponding to redundancy removal, and the initial multi-layer perceptron based on the redundancy removal sample and the non-graph dataset to obtain the graph neural network, the redundancy removal feature transformation model, and the initial multi-layer perceptron.

[0102] In an exemplary embodiment, taking the initial feature transformation model corresponding to training in an optimized manner as an example: the initial feature transformation model is to rewrite the corresponding initial feature transformation model. The computer device inputs the rewritten samples and the non-graph dataset into the initial graph neural network, and extracts the sample feature matrices of each rewritten sample and non-graph sample in the rewritten samples and the non-graph dataset through the initial graph neural network. Then, the computer device performs feature transformation on the sample feature matrix corresponding to each rewritten sample and non-graph based on the initial feature transformation model corresponding to the rewrite, to obtain the sample optimized feature matrix. Then, the computer device performs prediction processing on each sample optimized feature matrix based on the initial multi-layer perceptron, to obtain the sample prediction quality parameter. The computer device performs data processing on each set of sample prediction quality parameters and each set of sample quality parameters based on the loss function algorithm, to obtain the loss value. Then, the computer device determines whether the loss value reaches the loss threshold. If the loss value reaches the loss threshold, the computer device determines that the initial feature transformation model corresponding to the rewrite is the feature transformation model corresponding to the rewrite. If the loss value does not reach the loss threshold, the computer device updates the parameters of the initial feature transformation model corresponding to the rewrite, the initial graph neural network, and the initial multi-layer perceptron according to the loss value, and executes the step of performing feature transformation on the sample feature matrix corresponding to each rewritten sample and non-graph based on the initial feature transformation model corresponding to the rewrite, until the loss value reaches the loss threshold.

[0103] During the training process, a multi-objective joint optimization method can be used. Specifically, during the training process of the initial graph neural network, the initial feature transformation model, and the initial multi-layer perceptron, a multi-objective loss function is designed. Physical meaning indicators such as area, delay, and power consumption, functional indicators such as the model truth table and node functions, sub-structure similarity structure indicators, and other indicators such as testability and security are comprehensively considered as the labels and the output targets of the multi-layer perceptron for model training. At the same time, multiple objectives such as area, delay, and power consumption are used to select the optimal logical structure in the feature space, which involves the balance between multiple optimization objectives. The loss function weights are dynamically adjusted during the training process to meet specific design requirements. It is also possible to regard the non-graph optimization as a sequential decision-making problem, and use reinforcement learning algorithms (such as deep Q network or proximal policy optimization algorithm, etc.) to explore the optimal optimization operation sequence. By introducing a multi-modal feature representation mechanism and combining physical layer information (such as wire length, congestion), a multi-objective optimization model is constructed. The joint optimization of functional and non-functional indicators is achieved. The adaptability of the non-graph optimization method in the subsequent stages of electronic design automation is improved.

[0104] In addition, during the training process, the deep learning framework PyTorch (an open-source machine learning framework) and PyTorch Geometric (an extension library of PyTorch) are used to implement the deep learning model and its training, and the reinforcement learning algorithm library OpenAI Gym (OpenAI Gym) is used to explore the optimal sequence.

[0105] Optionally, the loss threshold is determined according to the training requirements, and the embodiments of the present application do not limit the loss threshold.

[0106] In this embodiment, by training the initial graph neural network, the initial feature transformation models corresponding to each optimization method, and the initial multi-layer perceptron, the graph neural network, each feature transformation model, and the multi-layer perceptron are obtained, improving the accuracy of the graph neural network, each feature transformation model, and the multi-layer perceptron, and providing a model basis for subsequent optimization of the to-be-optimized AND / OR / NOT graph.

[0107] In an exemplary embodiment, as Figure 8 shown, the specific processing process of extracting the feature matrix corresponding to the to-be-optimized AND / OR / NOT graph in step 104 includes steps 802 to 806. Among them:

[0108] Step 802, extract the logical structure of the to-be-optimized AND / OR / NOT graph through a standard logic synthesis tool to obtain the initial logical relationship set of the to-be-optimized AND / OR / NOT graph.

[0109] In implementation, the computer device extracts each logic gate of the to-be-optimized AND / OR / NOT graph and the logical relationship between each logic gate based on the standard synthesis logic tool to obtain the initial logical relationship set of the to-be-optimized AND / OR / NOT graph.

[0110] Specifically, the computer device extracts each logic gate of the to-be-optimized AND / OR / NOT graph and the logical relationship between each logic gate from the to-be-optimized AND / OR / NOT graph through a standard logic synthesis tool to obtain the initial logical relationship set of the to-be-optimized AND / OR / NOT graph. Optionally, the computer device can also directly extract the AND / OR / NOT graph structure from the Boolean logic expression or the existing logic circuit to obtain the initial logical relationship set of the to-be-optimized AND / OR / NOT graph. The initial logical relationship set G=(V,E) includes a node set V and an edge set E. The node set contains each node, and each node represents a logic gate, and the logic gate is AND / OR / NOT. The edge set contains each edge, and each edge represents the logical relationship between two logic gates.

[0111] Optionally, the standard synthesis logic tool can be but is not limited to the ABC tool (an open-source synthesis logic tool), and the embodiments of the present application do not limit the standard synthesis logic tool.

[0112] Step 804, update the node set in the initial logical relationship set based on the logical feature vector to obtain the logical relationship set of the to-be-optimized AND / OR / NOT graph.

[0113] Among them, the initial logical relationship set contains a node set, and the node set contains each node.

[0114] In implementation, the computer device adds the logical feature vector to each node in the initial logical relationship set to obtain a logical relationship set of the to-be-optimized AND-NOT graph.

[0115] In an exemplary embodiment, the logical feature vector is , and the node set is , where n is the number of nodes, represents the first node. The computer device adds the logical feature vector to each node in the node set to obtain an updated node set. Then, the computer device constructs a logical relationship set based on the updated node set and the edge set.

[0116] Step 806: Extract features from the logical relationship set based on the graph neural network to obtain a feature matrix of the to-be-optimized AND-NOT graph.

[0117] In implementation, the computer device inputs the logical relationship set into the graph neural network, and the graph neural network extracts features from the logical relationship set of the to-be-optimized AND-NOT graph to obtain a feature matrix of the to-be-optimized AND-NOT graph.

[0118] Specifically, the graph neural network is a Transformer model based on a directed acyclic graph. This Transformer model uses a transitive fan-in attention mechanism combined with the AND-NOT graph attributes for message passing. The process of message passing is shown in the following formula (1):

[0119] (1)

[0120] In the above formula (1), , indicates that this is the feature vector of node at the th layer, which represents the learning representation of the node at the current layer. is the set of fan-in nodes of node , and is also the set of neighbor nodes of node . represents a fan-in node or neighbor node of node . is an aggregation function used to combine the hidden state of the node itself and the information of its neighbor nodes to generate the hidden state of the next layer.

[0121] The attention calculation formula of the attention mechanism is shown in the following formula (2):

[0122] (2)

[0123] In the above formula (2), represents the attention of the feature vector of node . represents the transformation of the hidden state of node is the set of fan-in nodes of node , and is also the set of neighbor nodes of node . represents the weight matrix of values, which is also a transformation matrix, and is used to transform the hidden states of neighbor nodes into the value space. is the weight matrix of queries, which is also a query matrix, and is used to transform the hidden states of nodes into the query space. represents the weight matrix of keys, which is also a key matrix, and is used to transform the hidden states of nodes into the key space. is the healing power weight, indicating that node is the attention weight for neighbor node , measuring the correlation between node and neighbor node . represents the sum of for all neighbor nodes , playing a role in normalization, so that the sum of all attentions is 1. is the similarity function, are the representations of query (Query) and key (Key) respectively. represents the dot product, is the scaling factor, is the dimension of the key, which is used to prevent the gradient from vanishing due to the too large dot product.

[0124] The computer device calculates the attention weights through the above formula (2), and calculates the embedding features of each node based on the attention weights to obtain the feature matrix. By calculating the attention weights representing the importance of the fan-in nodes of the nodes, the understanding degree of the graph neural network for the structural features to be optimized and non-graph can be deepened. Figure 9 is a schematic diagram of the attention mechanism in an exemplary embodiment. In Figure 9 , the numbers in the left circle represent nodes 1 to node 9 respectively. On the right represents the feature vector of node 1, represents the feature vector of node 9.

[0125] In this embodiment, the embedding features to be optimized and non-graph are extracted through a unique attention model to obtain the feature matrix, which provides a data basis for subsequent feature transformation, and the embedding features in the feature matrix are suitable for feature transformation.

[0126] In an exemplary embodiment, as Figure 10 shown, the specific processing procedure for determining the feature transformation model group corresponding to each optimization method sequence in step 104 includes steps 1002 to 1004. Among them:

[0127] Step 1002, for each optimization method sequence, among the feature transformation models of each optimization method, determine the initial target feature transformation model corresponding to each initial target optimization method in the optimization method sequence.

[0128] Among them, the optimization method sequence includes each initial target optimization method.

[0129] In implementation, for each optimization method sequence, the computer device determines, among the feature transformation models of each optimization method, the feature transformation model corresponding to each initial target optimization method in the optimization method sequence as the initial target feature transformation model.

[0130] In an exemplary embodiment, taking the determination of the initial target feature transformation models corresponding to an optimization method sequence as an example: the optimization method sequence is rewrite, balance, reconstruction, and re-replacement. The computer device determines the feature transformation model corresponding to rewrite among the feature transformation models of each optimization method as the initial target feature transformation model. At the same time, the computer device determines the feature transformation model corresponding to balance as the initial target feature transformation model. The computer device determines the feature transformation models corresponding to reconstruction and re-replacement as the initial target feature transformation models.

[0131] Step 1004, according to the order of each initial target optimization method in the optimization method sequence, combine the initial target feature transformation models to obtain a feature transformation model group.

[0132] In implementation, the computer device sorts the initial target feature transformation models according to the order corresponding to each initial target optimization method in the optimization method sequence, and combines the sorted initial target feature transformation models to obtain a feature transformation model group.

[0133] In an exemplary embodiment, taking the combination of a feature transformation model group corresponding to an optimization method sequence as an example: the optimization method sequence is rewrite, balance, reconstruction, and re-replacement. The computer device sorts the initial target feature transformation models in the order of rewrite, balance, reconstruction, and re-replacement, and combines the sorted initial target feature transformation models into a feature transformation model group. Therefore, the feature transformation model group includes the initial target feature transformation model corresponding to rewrite, the initial target feature transformation model corresponding to balance, the initial target feature transformation model corresponding to reconstruction, and the initial target feature transformation model corresponding to re-replacement.

[0134] In this embodiment, by combining the feature transformation model groups corresponding to each optimization method sequence, a model basis is provided for continuously optimizing the feature matrix subsequently. Moreover, by continuously optimizing the feature matrix in the same feature space, the problem that the discrete optimization processes of traditional and non-graph optimization algorithms are difficult to capture the continuous spatial features in the logical graph optimization process and lack the support of graph embedding features is solved, and the continuity of the feature space and the continuity of the feature matrix optimization are realized.

[0135] In an exemplary embodiment, the specific process of performing feature transformation on the feature matrix based on each feature transformation model group in step 106 includes:

[0136] For each feature transformation model group, perform feature transformation on the feature matrix in the order of the initial target feature transformation models in the feature transformation model group to obtain an optimized feature matrix.

[0137] In implementation, for each feature transformation model group, the computer device inputs the feature matrix into the first initial target feature transformation model in the feature transformation model group, and performs feature transformation on the feature matrix through the initial target feature transformation model to obtain an initial optimized feature matrix. Then, the computer device continues to input the initial optimized feature matrix into the next initial target feature transformation model in the feature transformation model group, and based on the step of performing feature transformation on the feature matrix through the initial target feature transformation model, until the initial target feature transformation model is the last initial target feature transformation model, an optimized and completed optimized feature matrix is obtained.

[0138] In an exemplary embodiment, the initial target feature transformation model is a transformer model. There is a feature transformation function in this transformer model. This feature transformation function is shown in the following formula (3):

[0139] (3)

[0140] In the above formula (3), is the node feature in the feature matrix, the embedding vector in the initial optimized feature matrix after being optimized by the initial target feature transformation model, is the parameter of the initial target feature transformation model. is the feature transformation function.

[0141] Since the initial target feature transformation models corresponding to different optimization methods are different, the feature transformation functions and parameters of each initial target feature transformation model are also different, and the obtained embedding features are also different.

[0142] The computer device optimizes the feature matrix through each initial target feature transformation model in the feature transformation model group, enabling logical optimization operations on the feature matrix in a continuous feature space, thereby obtaining an optimized feature matrix. For example, the possibility of node merging, decomposition, or replacement is predicted by embedding the similarity between feature vectors. In addition, it is necessary to perform equivalent replacement on the logical structure in the feature space to ensure that the logical functions are consistent on the basis of structural transformation before and after conversion. Figure 11 It is a schematic structural diagram of the converter module in the initial target feature transformation model in an exemplary embodiment.

[0143] In this embodiment, by mapping the NAND graph to a continuous feature space and combining the global representation ability of the graph neural network, the global features of the entire NAND graph are optimized. Moreover, by using the gradient optimization algorithm in the feature space, the exploration ability for the global optimum is improved, and the probability of occurrence of the local optimum problem is reduced. Furthermore, the generated electronic device has higher performance. In addition, through the update mechanism of the embedded features, the adjustment of the embedding of specific sub-graph regions is realized, rather than the re-optimization of the entire graph, significantly improving the incremental optimization efficiency and avoiding the high computational cost of the re-optimization of the entire graph. For small-scale incremental modifications, the optimization speed is increased and the resource occupancy is reduced.

[0144] In an exemplary embodiment, the specific processing procedure for determining the target optimization mode sequence according to each quality parameter set in each optimization mode sequence in step 106 includes:

[0145] Each optimized feature matrix is input into a multi-layer perceptron, and the multi-layer perceptron performs prediction processing on the optimized feature matrix to obtain the quality parameter set of the optimized feature matrix.

[0146] In practice, the computer device inputs each optimized feature matrix into a multi-layer perceptron, and the multi-layer perceptron performs prediction processing on the optimized feature matrix to obtain the quality parameter set of the optimized feature matrix.

[0147] Optionally, the quality parameter set of the optimized feature matrix includes the predicted input quantity, the predicted output quantity, the predicted logical level, and the predicted area delay, which are determined according to the prediction requirements. The embodiments of the present application do not limit the quality parameter set.

[0148] In this embodiment, by directly optimizing the feature matrix corresponding to the NAND graph to be optimized and determining the quality parameter set of each optimized feature matrix, the optimization effect of each optimized feature matrix can be quickly determined by only transforming the feature matrix corresponding to the NAND graph to be optimized once, avoiding multiple image recognitions of each undetermined NAND graph and reducing the recognition time for images.

[0149] In an exemplary embodiment, as Figure 12As shown, the specific processing procedure for determining the target optimization mode sequence in each optimization mode sequence according to each set of quality parameters in step 108 includes steps 1202 to 1204. Among them:

[0150] Step 1202, determine the quality score corresponding to each set of quality parameters based on a preset evaluation criterion.

[0151] Among them, the evaluation criterion includes the evaluation rules corresponding to each quality parameter.

[0152] In implementation, the evaluation criterion is pre-set in the computer device. For each set of quality parameters, the computer device determines the initial quality score corresponding to the quality parameter according to the evaluation rules corresponding to each quality parameter. Then, the computer device performs a summation process on the initial quality scores to obtain the quality score corresponding to the set of quality parameters.

[0153] In an exemplary embodiment, the evaluation criterion is pre-set in the computer device. The evaluation criterion includes the scoring rules for area and the scoring rules for latency. The set of quality parameters includes a reference area and a reference latency. The computer device determines the initial quality score of the reference area in the set of quality parameters according to the scoring rules for area. Then, the computer device determines the initial quality score corresponding to the reference latency in the set of quality parameters according to the scoring rules for latency. The computer device performs a summation process on the initial quality score corresponding to the reference area and the initial quality score corresponding to the reference latency to obtain the quality score corresponding to the set of quality parameters.

[0154] In an alternative embodiment, the scoring rules include key indicators and the weights corresponding to the key indicators. For each set of quality parameters, the computer device determines the evaluation rules corresponding to the quality parameter according to the key indicators of each quality parameter in the set of quality parameters. Then, the computer device determines the initial quality score corresponding to the quality parameter according to the scoring rules. The computer device performs a weighting process on the initial quality scores according to the weights corresponding to the key indicators to obtain the quality score of the set of quality parameters.

[0155] Optionally, the evaluation rules are determined according to the quality parameters in the set of quality parameters and the optimization requirements, and the evaluation rules in the embodiments of the present application are not limited.

[0156] Step 1204, determine the highest quality score among the quality scores as the target quality score, and determine the optimization mode sequence corresponding to the quality score as the target optimization mode sequence.

[0157] In implementation, the computer device determines the highest quality score among the quality scores corresponding to each optimization mode sequence as the target quality score. Then, the computer device determines the optimization mode sequence corresponding to the target quality score as the target optimization mode sequence.

[0158] In this embodiment, by determining the quality score of each quality parameter set through the evaluation criteria, the target optimization method sequence can be quickly determined. Moreover, the evaluation criteria can be customized according to requirements, expanding the scope of use of non-graph optimization methods.

[0159] In one exemplary embodiment, Figure 13 is a flowchart of a non-graph optimization method in another embodiment. As Figure 13 shown, the process of this non-graph optimization method includes: The computer device extracts the logical relationship of the non-graph to be optimized on the left side to obtain a set of logical relationships of the non-graph to be optimized. The computer device inputs the set of logical relationships into a representation learning model (graph neural network) for feature extraction to obtain a feature matrix. Then, each feature transformation model group of the computer device performs feature transformation on the feature matrix to obtain each optimized feature matrix. The computer device determines the quality parameter set (prediction target) of each optimized feature matrix according to a multi-layer perceptron. The computer device determines the target optimization method sequence according to each quality parameter set.

[0160] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0161] Based on the same inventive concept, the embodiments of the present application also provide a non-graph optimization device for implementing the above-mentioned non-graph optimization method. The solution provided by this device for solving problems is similar to the solution described in the above method. Therefore, the specific limitations in one or more of the following non-graph optimization device embodiments can refer to the limitations on the non-graph optimization method in the above text, and will not be repeated here.

[0162] In one exemplary embodiment, as Figure 14 shown, a non-graph optimization device 1400 is provided, including: an acquisition module 1401, an extraction module 1402, an optimization module 1403, and a determination module 1404, where:

[0163] The acquisition module 1401 is configured to acquire the non-graph to be optimized and each optimization method sequence.

[0164] An extraction module 1402, configured to extract a feature matrix corresponding to the non-graph to be optimized based on a graph neural network, and determine a set of feature transformation models corresponding to each optimization method sequence.

[0165] An optimization module 1403, configured to perform feature transformation on the feature matrix based on each set of feature transformation models to obtain each optimized feature matrix, and determine a set of quality parameters for each optimized feature matrix according to a multi-layer perceptron.

[0166] A determination module 1404, configured to determine a target optimization method sequence from each set of quality parameters in each optimization method sequence, and optimize the non-graph to be optimized according to the target optimization method sequence to obtain a target optimized non-graph; the target optimized non-graph is used to determine the logical relationship of the electronic device.

[0167] In an exemplary embodiment, the NAND graph optimization device 1400 further includes:

[0168] A second acquisition module, configured to acquire an initial sample NAND graph dataset, and determine a set of sample quality parameters corresponding to each optimization method based on a logic synthesis tool and the initial sample NAND graph dataset.

[0169] A labeling module, configured to label the initial sample NAND graph dataset based on each set of sample quality parameters to obtain each sample NAND graph dataset.

[0170] A training module, configured to train an initial graph neural network, initial feature transformation models corresponding to each optimization method, and an initial multi-layer perceptron simultaneously based on each sample NAND graph dataset to obtain a graph neural network, each feature transformation model, and a multi-layer perceptron.

[0171] In an exemplary embodiment, the extraction module includes a first extraction sub-module and a first determination sub-module. Among them, the first extraction sub-module includes:

[0172] A second extraction sub-module, configured to extract the logical structure of the non-graph to be optimized through a standard logic synthesis tool to obtain an initial logical relationship set of the non-graph to be optimized.

[0173] An update sub-module, configured to update the node set in the initial logical relationship set based on a logical feature vector to obtain a logical relationship set of the non-graph to be optimized.

[0174] A third extraction sub-module, configured to perform feature extraction on the logical relationship set based on a graph neural network to obtain a feature matrix of the non-graph to be optimized.

[0175] In an exemplary embodiment, the extraction module includes a first extraction sub-module and a first determination sub-module. Among them, the first determination sub-module includes:

[0176] A second determination sub-module, configured to determine, for each optimization mode sequence, in the feature transformation models of each optimization mode, the initial target feature transformation models corresponding to the respective initial target optimization modes in the optimization mode sequence.

[0177] A combination sub-module, configured to combine the respective initial target feature transformation models in the order of the respective initial target optimization modes in the optimization mode sequence to obtain a set of feature transformation models.

[0178] In an exemplary embodiment, the optimization module includes a first optimization sub-module and a third determination sub-module. Specifically, the first optimization sub-module is configured to perform feature transformation on the feature matrix in the order of the respective initial target feature transformation models in the set of feature transformation models for each set of feature transformation models to obtain an optimized feature matrix.

[0179] In an exemplary embodiment, the optimization module includes a first optimization sub-module and a third determination sub-module. Specifically, the third determination sub-module is configured to input each optimized feature matrix into a multi-layer perceptron, and perform prediction processing on the optimized feature matrix through the multi-layer perceptron to obtain a set of quality parameters of the optimized feature matrix.

[0180] In an exemplary embodiment, the determination module includes a fourth determination sub-module and a second optimization sub-module. The fourth determination sub-module includes:

[0181] A fifth determination sub-module, configured to determine a quality score corresponding to each set of quality parameters based on a preset evaluation criterion.

[0182] A sixth determination sub-module, configured to determine the highest quality score among the respective quality scores as the target quality score, and determine the optimization mode sequence corresponding to the quality score as the target optimization mode sequence.

[0183] Each module in the above NAND graph optimization device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to the above respective modules.

[0184] In an exemplary embodiment, a computer device is provided. The computer device can be a terminal, and its internal structural diagram can be as Figure 15As shown in the figure. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a non-graph optimization method. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the outer shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0185] Those skilled in the art can understand that Figure 15 the structure shown in the figure is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0186] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0187] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0188] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0189] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0190] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0191] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A NAND graph optimization method, characterized in that, The method includes: Obtaining the to-be-optimized non-graph and each optimization method sequence; Extracting the feature matrix corresponding to the to-be-optimized non-graph based on a graph neural network, and determining a group of feature transformation models corresponding to each optimization method sequence; Performing feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix, and determining a quality parameter set for each optimized feature matrix according to a multi-layer perceptron; Determining a target optimization method sequence from each optimization method sequence according to each quality parameter set, and optimizing the to-be-optimized non-graph according to the target optimization method sequence to obtain a target optimized non-graph; the target optimized non-graph is used to determine the logical relationship of an electronic device; The determining a group of feature transformation models corresponding to each optimization method sequence includes: For each optimization method sequence, in the feature transformation models of each optimization method, determining an initial target feature transformation model corresponding to each initial target optimization method in the optimization method sequence; Combining each initial target feature transformation model in the order of each initial target optimization method in the optimization method sequence to obtain a group of feature transformation models; The performing feature transformation on the feature matrix based on each group of feature transformation models to obtain each optimized feature matrix includes: For each group of feature transformation models, performing feature transformation on the feature matrix in the order of each initial target feature transformation model in the group of feature transformation models to obtain an optimized feature matrix.

2. The method according to claim 1, wherein Before the extracting the feature matrix corresponding to the to-be-optimized non-graph based on a graph neural network, the method further includes: Obtaining an initial sample and non-graph data set, and determining a sample quality parameter set corresponding to each optimization method based on a logic synthesis tool and the initial sample and non-graph data set; Labeling the initial sample and non-graph data set based on each sample quality parameter set to obtain each sample and non-graph data set; Training an initial graph neural network, initial feature transformation models corresponding to each optimization method, and an initial multi-layer perceptron simultaneously based on each sample and non-graph data set to obtain a graph neural network, each feature transformation model, and a multi-layer perceptron.

3. The method according to claim 1, wherein The extracting the feature matrix corresponding to the to-be-optimized non-graph based on a graph neural network includes: Extracting the logical structure of the to-be-optimized non-graph through a standard logic synthesis tool to obtain an initial logical relationship set of the to-be-optimized non-graph; Updating the node set in the initial logical relationship set based on a logical feature vector to obtain a logical relationship set of the to-be-optimized non-graph; Performing feature extraction on the logical relationship set based on a graph neural network to obtain the feature matrix of the to-be-optimized non-graph.

4. The method according to claim 1, wherein The determining a quality parameter set for each optimized feature matrix according to a multi-layer perceptron includes: Inputting each optimized feature matrix into a multi-layer perceptron, and performing prediction processing on the optimized feature matrix through the multi-layer perceptron to obtain a quality parameter set for the optimized feature matrix.

5. The method according to claim 1, wherein The determining a target optimization method sequence from each optimization method sequence according to each quality parameter set includes: Determining a quality score corresponding to each quality parameter set based on a preset evaluation criterion; Among the quality scores, determine the highest quality score as the target quality score, and determine the sequence of optimization methods corresponding to the quality score as the target sequence of optimization methods.

6. A NAND graph optimization device, characterized in that, The device includes: An acquisition module, configured to acquire the object to be optimized and non-graphs and sequences of various optimization methods; An extraction module, configured to extract a feature matrix corresponding to the object to be optimized and non-graphs based on a graph neural network, and determine a group of feature transformation models corresponding to each sequence of optimization methods; An optimization module, configured to perform feature transformation on the feature matrix based on each group of feature transformation models to obtain optimized feature matrices, and determine a set of quality parameters for each optimized feature matrix according to a multi-layer perceptron; A determination module, configured to determine a target sequence of optimization methods from each sequence of optimization methods according to each set of quality parameters, and optimize the object to be optimized and non-graphs according to the target sequence of optimization methods to obtain a target optimized object and non-graphs; the target optimized object and non-graphs are used to determine the logical relationship of an electronic device; The first determination sub-module in the extraction module is specifically configured to, for each sequence of optimization methods, determine an initial target feature transformation model corresponding to each initial target optimization method in the sequence of optimization methods among the feature transformation models of various optimization methods; combine the initial target feature transformation models in the order of each initial target optimization method in the sequence of optimization methods to obtain a group of feature transformation models; The first optimization sub-module in the optimization module is specifically configured to, for each group of feature transformation models, perform feature transformation on the feature matrix in the order of each initial target feature transformation model in the group of feature transformation models to obtain an optimized feature matrix.

7. The device according to claim 6, characterized in that, The device further includes: A second acquisition module, configured to acquire an initial sample and non-graph data set, and determine a set of sample quality parameters corresponding to each optimization method based on a logic synthesis tool and the initial sample and non-graph data set; A labeling module, configured to label the initial sample and non-graph data set based on each set of sample quality parameters to obtain each sample and non-graph data set; A training module, configured to train an initial graph neural network, initial feature transformation models corresponding to various optimization methods, and an initial multi-layer perceptron simultaneously based on each sample and non-graph data set to obtain a graph neural network, various feature transformation models, and a multi-layer perceptron.

8. The device according to claim 6, characterized in that The determination module includes a fourth determination sub-module and a second optimization sub-module, and the fourth determination sub-module includes: A fifth determination sub-module, configured to determine a quality score corresponding to each set of quality parameters based on a preset evaluation criterion; A sixth determination sub-module, configured to determine the highest quality score among the quality scores as the target quality score, and determine the sequence of optimization methods corresponding to the quality score as the target sequence of optimization methods.

9. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 5 are implemented.

Images