Static hiding method of Latch PUF unit circuit in chip and electronic equipment

Abstract

The invention discloses a static hiding method of a Latch PUF (Physical Unclonable Function) unit circuit in a chip and electronic equipment. The method comprises the following steps of: instantiating standard units corresponding to a phase inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate and a second NAND gate by using Verilog language; generating a circuit netlist of the Latch PUF unit circuit according to the standard unit; based on the circuit netlist, placing each standard unit, carrying out interconnection wiring among the standard units, and carrying out instruction adjustment after interconnection wiring, so as to obtain a Latch PUF unit circuit; and randomly placing a plurality of Latch PUF unit circuits in the chip layout according to the random coordinates. According to the method provided by the invention, the circuit features and the image features of the Latch PUF can be effectively eliminated, so that the possibility that the Latch PUF is identified or positioned by an attacker is reduced, and the security of a chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a static hiding method of a Latch PUF (Physical Unclonable Functions) unit circuit in a chip, a computer-readable storage medium and an electronic device. Background Art

[0002] Physically Unclonable Function (PUF) generates keys by utilizing the inherent random process variations that occur during the manufacturing process of integrated circuits. This uncontrollable variation gives PUF security properties such as unpredictability and non-replicability, making it a promising hardware-based chip-level secure key generation solution.

[0003] In the related art, the current PUF circuit design requires highly symmetrical placement and wiring to achieve good bias characteristics, which makes it show significant layout features and image features in the chip image. The significant layout features and image features make the chip's PUF circuit vulnerable to attackers, posing a major security risk. Specifically, after obtaining the chip, the attacker can use reverse engineering techniques such as chip de-layering and circuit extraction to obtain the complete layout and circuit of the chip, making it easy to locate the PUF circuit. Subsequently, semi-invasive techniques such as focused ion beam or fault injection can be used to obtain the PUF key, making the chip less secure. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, the first purpose of the present invention is to propose a static hiding method for a Latch PUF unit circuit in a chip, by randomizing the position of a featureless Latch PUF unit circuit, and randomly distributing multiple Latch PUF unit circuits in a large number of standard digital units, effectively eliminating the circuit characteristics and image characteristics of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reducing the possibility of being identified or located by attackers, and improving the security of the chip.

[0005] A second object of the present invention is to provide a computer-readable storage medium.

[0006] A third objective of the present invention is to provide an electronic device.

[0007] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a static hiding method for a Latch PUF unit circuit in a chip, wherein the chip includes a plurality of the Latch PUF unit circuits, and the Latch PUF unit circuit includes an inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate and a second NAND gate, wherein the transmission path from the buffer to the first multiplexer is a first path, the transmission path from the buffer to the second multiplexer is a second path, the transmission path from the first multiplexer to the first NAND gate is a third path, the transmission path from the second multiplexer to the second NAND gate is a fourth path, the transmission path from the output end of the second NAND gate to the input end of the first NAND gate is a fifth path, and the transmission path from the output end of the first NAND gate to the input end of the second NAND gate is a sixth path; the method includes: using Verilog language to respectively instantiate standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate and the second NAND gate; generating the Latch according to each of the standard cells. A circuit netlist of a PUF unit circuit; based on the circuit netlist, placing each of the standard cells, interconnecting and routing each of the standard cells, and adjusting instructions after the interconnection and routing to obtain the Latch PUF unit circuit, wherein the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; and randomly placing a plurality of the Latch PUF unit circuits in a chip layout according to random coordinates.

[0008] According to the static hiding method of the Latch PUF unit circuit in the chip of the embodiment of the present invention, firstly, the standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate and the second NAND gate are respectively instantiated using the Verilog language; then, a circuit netlist of the Latch PUF unit circuit is generated according to the standard cells, and based on the circuit netlist, each standard cell is placed, and interconnection routing is performed between each standard cell, and instruction adjustment is performed after the interconnection routing to obtain the Latch PUF unit circuit, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; finally, a plurality of Latch PUF unit circuits are randomly placed in the chip layout according to random coordinates. Therefore, this method randomizes the position of the featureless Latch PUF unit circuit, and randomly distributes multiple Latch PUF unit circuits in a large number of standard digital units, effectively eliminating the circuit characteristics and image characteristics of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reducing the possibility of being identified or located by attackers, and improving the security of the chip.

[0009] In addition, the static hiding method of the Latch PUF unit circuit in the chip according to the above embodiment of the present invention may also have the following additional technical features:

[0010] According to an embodiment of the present invention, placing each of the standard cells includes: placing each of the standard cells symmetrically.

[0011] According to one embodiment of the present invention, the standard cells are symmetrically placed, including: placing the standard cell of the first NAND gate and the standard cell of the second NAND gate in mirror symmetry, and determining the axis of symmetry; placing the standard cell of the first multiplexer below the standard cell of the first NAND gate along the axis of symmetry, and mirroring the standard cell of the second multiplexer below the standard cell of the second NAND gate along the axis of symmetry, and the standard cell of the first multiplexer and the standard cell of the second multiplexer are mirror symmetric; placing the standard cell of the buffer below the standard cell of the second multiplexer along the axis of symmetry.

[0012] According to one embodiment of the present invention, interconnection routing is performed between each of the standard cells and instruction adjustment is performed after the interconnection routing, including: automatic layout and routing between each of the standard cells; and instruction adjustment of each path according to the length of each path after automatic layout and routing, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0013] According to one embodiment of the present invention, a plurality of LatchPUF unit circuits are randomly placed in a chip layout according to random coordinates, including: obtaining a unit height of a standard unit in a process library file, an area of ​​a NAND gate, an area of ​​a multiplexer, and an area of ​​a buffer; determining a width of the NAND gate according to the area of ​​the NAND gate and the unit height; determining a width of the multiplexer according to the area of ​​the multiplexer and the unit height; determining a width of the buffer according to the area of ​​the buffer and the unit height; obtaining a placement spacing and a width of a WellTap unit in a chip, and boundary coordinates of the WellTap unit; inputting the unit height, the width of the NAND gate, the width of the multiplexer, the width of the buffer, the placement spacing and the width of the WellTap unit, and the boundary coordinates of the WellTap unit into a preset algorithm to randomly generate a plurality of the random coordinates; and placing a plurality of Latch PUF unit circuits in a chip layout according to the plurality of the random coordinates.

[0014] According to one embodiment of the present invention, the width of the NAND gate is determined by the following formula:

[0015]

[0016] Among them, W ND is the width of the NAND gate, A ND is the area of ​​the NAND gate, H cell is the unit height.

[0017] According to one embodiment of the present invention, the width of the multiplexer is determined by the following formula:

[0018]

[0019] Among them, W MUX is the width of the multiplexer, A MUX is the area of ​​the multiplexer, H cell is the unit height.

[0020] According to one embodiment of the present invention, the width of the buffer is determined by the following formula:

[0021]

[0022] Among them, W BUF is the width of the buffer, A BUF is the area of ​​the buffer, H cell is the unit height.

[0023] To achieve the above-mentioned purpose, a second aspect of the present invention proposes a computer-readable storage medium on which a static hiding program of the Latch PUF unit circuit in a chip is stored. When the static hiding program of the Latch PUF unit circuit in the chip is executed by a processor, the static hiding method of the Latch PUF unit circuit in the chip is implemented.

[0024] According to the computer-readable storage medium of the embodiment of the present invention, through the static hiding method of the Latch PUF unit circuit in the above-mentioned chip, the circuit characteristics and image characteristics of the Latch PUF can be effectively eliminated, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, thereby reducing the possibility of being identified or located by attackers and improving the security of the chip.

[0025] To achieve the above-mentioned purpose, an embodiment of the third aspect of the present invention proposes an electronic device, comprising: a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the processor executes the program, a static hiding method of the Latch PUF unit circuit in the above-mentioned chip is implemented.

[0026] According to the electronic device of the embodiment of the present invention, the circuit characteristics and image characteristics of the Latch PUF can be effectively eliminated through the static hiding method of the Latch PUF unit circuit in the chip, making it difficult for an attacker to locate the Latch PUF unit circuit through the image characteristics, thereby reducing the possibility of being identified or located by the attacker and improving the security of the chip.

[0027] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flow chart of a static hiding method of a Latch PUF unit circuit in a chip according to an embodiment of the present invention;

[0029] Figure 2 A Latch PUF unit circuit according to an embodiment of the present invention and an equivalent circuit in different modes;

[0030] Figure 3 is a schematic diagram of a transmission path of a Latch PUF unit circuit according to an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a placement method of a Latch PUF unit circuit according to an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of a Latch PUF unit circuit after automatic wiring according to an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of a Latch PUF unit circuit after optimized wiring according to an embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of a WellTap unit in a chip according to an embodiment of the present invention;

[0035] Figure 8 The Latch PUF unit circuit according to one embodiment of the present invention effectively places an area

[0036] Fig. 9 It is a schematic diagram of the overall layout of the chip layout after the Latch PUF unit circuits are randomly placed according to an embodiment of the present invention;

[0037] Fig.10 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0039] The following describes a static hiding method of a Latch PUF unit circuit in a chip, a computer-readable storage medium, and an electronic device proposed in an embodiment of the present invention with reference to the accompanying drawings.

[0040] Physically unclonable functions (PUFs) use inherent random process variations that occur during the manufacturing process of integrated circuits to generate keys. This uncontrollable variation gives PUF security features such as unpredictability and non-replicability, making it a promising hardware-based chip-level secure key generation solution. The current PUF circuit design requires highly symmetrical placement and routing to achieve good bias characteristics, which makes it exhibit significant layout features and image features in the chip image. The significant layout features and image features make the chip's PUF circuit vulnerable to attackers, posing a major security risk. Specifically, after obtaining the chip, the attacker can use reverse engineering techniques such as chip de-layering and circuit extraction to obtain the complete layout and circuit of the chip, making it easy to locate the PUF circuit. Subsequently, semi-invasive techniques such as focused ion beam or fault injection can be used to obtain the PUF key. Therefore, to achieve comprehensive concealment of PUF, the key is not only to obfuscate the use of PUF keys, but also to hide the PUF circuit.

[0041] After obtaining the chip, the attacker can use reverse engineering techniques such as chip de-layering and circuit extraction to obtain the complete layout and circuit of the chip, making it easy to locate the PUF circuit. Subsequently, semi-invasive techniques such as focused ion beam or fault injection can be used to obtain the PUF key. In order to mitigate these defects, various protection strategies have been proposed. For example, a collaborative fuzzification scheme is adopted, which uses virtual hole technology to implement fuzzy logic gates for logical fuzzification. However, this scheme still distributes channel-based PUFs on the chip in an orderly manner. Compared with standard logic gates, virtual visual holes have a larger area, allowing attackers to locate them through computer vision technology; another example is an obfuscation cell (OC) composed of inverters and multiplexers. The chip-dependent license is generated by the PUF response based on the OC configuration to prevent image processing-based reverse engineering and protect third-party IP cores. However, this scheme only performs multi-layer obfuscation on the PUF key without hiding the PUF circuit. Therefore, the PUF circuit still has unique characteristics, allowing attackers to easily locate them, thereby obtaining the PUF key and subsequently tracing it to the license; another example is the use of combining the response of the PUF with a finite state machine (finite state This method integrates the inherent PUF response into the FSM, restricts the execution of the hardware IP on a specific FPGA, and enforces the paid device license, thereby protecting the IP core. However, attackers can still locate the PUF based on its unique characteristics, and then obtain the key through physical attacks, and use the obtained PUF key to make the FSM work properly, thereby cracking the entire security chip. Therefore, to achieve comprehensive concealment of the PUF, the key is not only to obfuscate the use of the PUF key, but also to hide the PUF circuit.

[0042] In order to achieve the concealment of PUF circuits, they must be implemented using standard cells, and then they should be randomly distributed on the chip, so that the PUF cells are hidden in a large number of standard cells and have no obvious image features. However, some existing PUFs cannot eliminate their obvious image features even if they are implemented using standard cells, such as Arbiter PUF, RO PUF, and SRAM PUF. Arbiter PUF requires a large number of multiplexers for channel switching and D flip-flops at the end of the circuit for arbitration, which produces obvious features in the chip, making it easy to be identified by attacks; similarly, the ring oscillator in RO PUF is composed of neatly arranged inverters, which also has significant features; although SRAM PUF can be reused with SRAM, the unique features of SRAM and its bus structure make it easy for attackers to locate it. Once the attacker successfully locates the PUF circuit, the attacker can extract the key at a lower cost through invasive attacks. Therefore, the fundamental reason why the above-mentioned PUF implemented using standard cells cannot be concealed is that many identical standard cells are clustered together. Therefore, in order to achieve the concealment of PUF circuits, PUF units must be composed of a small number of standard units, and their aggregation should be avoided.

[0043] To address this problem, the present invention proposes a static hiding method based on Latch PUF. First, the featureless LatchPUF unit circuit is composed of only 6 standard units to eliminate the circuit characteristics of PUF. Second, the featureless LatchPUF units are randomly distributed in the layout of the entire digital chip instead of being clustered together to eliminate the image characteristics of PUF.

[0044] Figure 1 4 is a flow chart of a static concealment method of a Latch PUF unit circuit in a chip according to an embodiment of the present invention.

[0045] like Figure 2As shown, in one embodiment of the present invention, the chip includes a plurality of Latch PUF unit circuits, and the Latch PUF unit circuit includes an inverter, a buffer BUFFER, a first multiplexer MUX1, a second multiplexer MUX2, a first NAND gate NAND1, and a second NAND gate NAND2. Both the first multiplexer MUX1 and the second multiplexer MUX2 are controlled by a mode control signal MODE, which enables the Latch PUF unit circuit to switch between two working modes: the Latch unit and the Latch PUF. When the mode is "1", OUT is equal to the input signal IN. Subsequently, when MODE is "0" and PUF_EN is "1", the featureless Latch PUF acts as a Latch unit to store the previous input signal IN. When MODE is "0" and PUF_EN is "0", the OUT output is not latched before the output, and the data becomes a constant "1" and prepares for the key generation of the Latch PUF. Subsequently, when MODE is "0" and PUF_EN is "1", the circuit works as a Latch PUF, and OUT is determined by the driving capability of the first NAND gate NAND1 and the second NAND gate NAND2. If the first NAND gate NAND1 has a stronger driving capability, OUT is "1", otherwise, OUT outputs "0".

[0046] Among them, Figure 3 As shown, the transmission path from the buffer BUFFER to the first multiplexer MUX1 is the first path Path1, the transmission path from the buffer BUFFER to the second multiplexer MUX2 is the second path Path2, the transmission path from the first multiplexer MUX1 to the first NAND gate NAND1 is the third path Path3, the transmission path from the second multiplexer MUX2 to the second NAND gate NAND2 is the fourth path Path4, the transmission path from the output end of the second NAND gate NAND2 to the input end of the first NAND gate NAND1 is the fifth path Path5, and the transmission path from the output end of the first NAND gate NAND1 to the input end of the second NAND gate NAND2 is the sixth path Path6.

[0047] like Figure 1 As shown, the static hiding method of the Latch PUF unit circuit in the chip of the embodiment of the present invention may include the following steps:

[0048] S1, using Verilog language to respectively instantiate standard cells corresponding to an inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate, and a second NAND gate.

[0049] S2, generating a circuit netlist of the Latch PUF unit circuit according to each standard unit.

[0050] S3, based on the circuit netlist, placing each standard cell, interconnecting and routing each standard cell, and adjusting instructions after interconnecting and routing, so as to obtain a Latch PUF unit circuit, wherein the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0051] S4, randomly placing multiple Latch PUF unit circuits in the chip layout according to random coordinates.

[0052] Specifically, in order to accurately place the digital circuit of the featureless Latch PUF unit, the inverter, buffer (BUFFER), multiplexer (MUX) and NAND standard cells in the HJ 180nm standard cell library are first instantiated using the Verilog hardware description language. Then the register transfer level (RTL) code is synthesized by Design Compile to generate a circuit netlist. Finally, based on the obtained circuit netlist, each standard cell is placed in Innovus, and interconnection routing is performed between each standard cell. After the interconnection routing, according to the results of the interconnection routing, that is, the length of each path, the instructions of each path are adjusted so that the length of the first path Path1 is equal to the length of the second path Path2, the length of the third path Path3 is equal to the length of the fourth path Path4, and the length of the fifth path Path5 is equal to the length of the sixth path Path6, thereby obtaining the Latch PUF unit circuit. This alignment helps to prevent additional and predictable differences due to the mismatch of the length of the interconnection routing within the featureless Latch PUF unit circuit, thereby realizing the placement and routing of the featureless Latch PUF circuit. In the same way, multiple LatchPUF unit circuits are obtained, and then the multiple Latch PUF unit circuits are randomly placed in the chip layout according to the random coordinates in the chip.

[0053] Therefore, the static hiding method of the Latch PUF unit circuit in the embodiment of the present invention randomizes the position of the featureless Latch PUF unit circuit, and randomly distributes multiple Latch PUF unit circuits in a large number of standard digital units, thereby effectively eliminating the circuit characteristics and image characteristics of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reducing the possibility of being identified or located by attackers, and improving the security of the chip.

[0054] According to an embodiment of the present invention, placing each standard cell includes: placing each standard cell symmetrically.

[0055] Further, according to an embodiment of the present invention, each standard cell is placed symmetrically, including: placing the standard cell of the first NAND gate and the standard cell of the second NAND gate in a mirror-symmetrical manner, and determining the axis of symmetry; placing the standard cell of the first multiplexer below the standard cell of the first NAND gate along the axis of symmetry, and mirror-placing the standard cell of the second multiplexer below the standard cell of the second NAND gate along the axis of symmetry, and the standard cell of the first multiplexer and the standard cell of the second multiplexer are mirror-symmetrical; placing the standard cell of the buffer below the standard cell of the second multiplexer along the axis of symmetry.

[0056] Specifically, if Figure 3 As shown, when the featureless Latch PUF unit circuit is used as a Latch PUF, it is necessary to ensure that the length of the first path Path1 is equal to the length of the second path Path2, the length of the third path Path3 is equal to the length of the fourth path Path4, and the length of the fifth path Path5 is equal to the length of the sixth path Path6. This alignment helps prevent additional, predictable differences due to the mismatch of the length of the interconnection traces within the featureless Latch PUF unit. To achieve this, the standard cells in the Latch PUF unit circuit should be placed symmetrically. Figure 4 As shown, the standard cell of the first NAND gate NAND1 and the standard cell of the second NAND gate NAND2 are placed in mirror symmetry. Similarly, the standard cell of the first multiplexer MUX1 is placed below the standard cell of the first NAND gate NAND1 along the symmetry axis, and the standard cell of the second multiplexer MUX2 is placed below the standard cell of the second NAND gate NAND2 along the symmetry axis, and the standard cell of the first multiplexer MUX1 and the standard cell of the second multiplexer MUX2 are mirror symmetric. Due to the limitation of the placement grid, the buffer BUFFER cannot be placed symmetrically below along the same symmetry axis, so the buffer BUFFER is placed below MUX2, close to the right side of the symmetry axis. Figure 4 The placement shown ensures that the interconnect trace lengths between standard cells are as consistent as possible, minimizing the impact of path differences on the key.

[0057] According to one embodiment of the present invention, interconnection routing is performed between various standard cells and instruction adjustment is performed after the interconnection routing, including: automatic layout and routing between various standard cells; according to the length of each path after the automatic layout and routing, instruction adjustment is performed on each path, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0058] For example, after the standard cells in the featureless Latch PUF unit circuit are placed, automatic layout and routing will be performed between the standard cells. Figure 5 As shown in the figure, only the path lengths of the third path Path3 and the fourth path Path4 are equal, while the path lengths of the first path Path1 and the second path Path2, as well as the fifth path Path5 and the sixth path Path6 are inconsistent. In order to solve the difference in path length between the first path Path1 and the second path Path2, first use the deleteNet command to delete the second path Path2 routing between the buffer BUFFER and the second multiplexer MUX2; then use the editSelectVia command to select the via Via in the second multiplexer MUX2, and then apply the editMove command to move the via Via upward to make up for the difference in path length between the first path Path1 and the second path Path2; finally, use the editAddRoute command to reroute the second path Path2, changing the path lengths of the first path Path1 and the second path Path2 from 5.78μm and 5.16μm to a uniform 5.78μm, so that their lengths are equal. In order to solve the difference in path length between the fifth path Path5 and the sixth path Path6, the deleteNet command is initially used to delete the existing routing of the fifth path Path5; then the editAddRoute command is used to mirror the path direction of the sixth path Path6 to reroute the fifth path Path5, thereby modifying the path lengths of the fifth path Path5 and the sixth path Path6 from 3.04μm and 5.28μm respectively to the same 5.28μm, thereby achieving equal path lengths. The optimized routing results are shown in Figure 1. Figure 6 The same steps are applied to other featureless Latch PUF units to ensure that the length of the first path Path1 of all units is equal to the length of the second path Path2, the length of the third path Path3 is equal to the length of the fourth path Path4, and the length of the fifth path Path5 is equal to the length of the sixth path Path6.

[0059] It should be understood that there may be certain differences in the interconnection routing between the standard cells of different Latch PUF units. After automatic layout and routing between the standard cells, the instructions for each path are adjusted according to the length of each path after automatic layout and routing, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0060] According to one embodiment of the present invention, a plurality of Latch PUF unit circuits are randomly placed in a chip layout according to random coordinates, including: obtaining a unit height of a standard unit in a process library file, an area of ​​a NAND gate, an area of ​​a multiplexer, and an area of ​​a buffer; determining a width of the NAND gate according to the area and unit height of the NAND gate; determining a width of the multiplexer according to the area and unit height of the multiplexer; determining a width of the buffer according to the area and unit height of the buffer; obtaining a placement spacing and a width of a WellTap unit in a chip, and boundary coordinates of the WellTap unit; inputting the unit height, the width of the NAND gate, the width of the multiplexer, the width of the buffer, the placement spacing and the width of the WellTap unit, and the boundary coordinates of the WellTap unit into a preset algorithm to randomly generate a plurality of random coordinates; and placing a plurality of Latch PUF unit circuits in a chip layout according to the plurality of random coordinates.

[0061] According to one embodiment of the present invention, the width of the NAND gate is determined by the following formula:

[0062]

[0063] Among them, W ND is the width of the NAND gate, A ND is the area of ​​the NAND gate, H cell is the unit height.

[0064] According to one embodiment of the present invention, the width of the multiplexer is determined by the following formula:

[0065]

[0066] Among them, W MUX is the width of the multiplexer, A MUX is the area of ​​the multiplexer, H cell is the unit height.

[0067] According to one embodiment of the present invention, the width of the buffer is determined by the following formula:

[0068]

[0069] Among them, W BUF is the width of the buffer, A BUF is the area of ​​the buffer, H cell is the unit height.

[0070] Specifically, during the chip planning process, WellTap units are first placed at fixed intervals to prevent latching effects. Therefore, when randomly placing featureless Latch PUF units, they should be avoided in places with WellTap units. To this end, the PUF unit circuit placement problem is transformed into a mathematical problem of finding the coordinates of the maximum reachable area under given boundary constraints.

[0071] Specifically, based on the process library file, the unit height H of the standard unit can be obtained: cell , and the area sizes of the NAND gate, the multiplexer MUX and the buffer BUFFER are A ND , A MUX and A BUF , from which the width W of the NAND gate can be derived respectively ND , the width W of the multiplexer MUX MUX and the width W of BUFFER BUF .

[0072] Furthermore, if Figure 7 As shown, WellTap units are staggered in the chip layout, with a spacing of S WT , width W WT To facilitate layout, the featureless Latch PUF unit circuit is randomly placed in the space between any two WellTap units, such as Figure 8 As shown. Set the unit height H cell , the width of the NAND gate W ND , the width of the multiplexer W MUX , buffer width W BUF 、WellTap unit placement spacing S WT , Width W WT The boundary coordinates of the WellTap unit are input into the preset algorithm to randomly generate multiple random coordinates, wherein the boundary coordinates of the WellTap unit can be the coordinates (X1, Y1) of the lower left WellTap unit and the coordinates (X2, Y2) of the upper right WellTap unit; the coordinates (X1, Y1) of the first NAND gate NAND1 can be obtained by calculating through the preset algorithm. ND1 , Y ND1 ), the coordinate of the second NAND gate NAND2 (X ND2 , Y ND2 ), the coordinates (X MUX1 , Y MUX1 ), the coordinates of the second multiplexer MUX2 (X MUX2 , Y MUX2 ), the coordinates of the buffer BUFFER (X BUF， YBUF ).

[0073] Exemplarily, the code of the preset algorithm is specifically shown in Table 1.

[0074] Table 1

[0075]

[0076]

[0077] The following is a text description of the code:

[0078] for loop i=0, ..., N means looping the following content N times to generate N coordinates that meet the standards;

[0079] First, for i=1; for the coordinates (X ND1 , Y ND1 ), (X ND2 , Y ND2 ), (X MUX1 , Y MUX1 ), (X MUX2 , Y MUX2 ), (X BUF， Y BUF ) is initialized to 0, 0;

[0080] Then perform while judgment, (X ND1 , X ND2 , X MUX1 , X MUX2 , X BUF <X1 or> X2)or(Y ND1 , Y ND2 , Y MUX1 , Y MUX2 , Y BUF <Y1 or> Y2) Only when the X coordinates of these coordinates are less than X1 or greater than X2, or the Y coordinates are less than Y1 or greater than Y2, perform the following operations, and then divide them into three cases to judge W ND , W MUX , W MUX Which one is the largest? In different situations, different formulas can be used to generate coordinates. The largest one is W. ND For example, use the int(rand(a, b)) function to generate random integers in the range (a, b) to generate the required N and A; then according to rand(X1+N*W WT +(N-1)*S WT , X1+N*W WT +N*S WT -2*W ND) Generate the X coordinate of MUX1;

[0081] Then, the corresponding coordinates of NAND1, NAND2, MUX1, MUX2, and BUFFER are generated according to the following formulas. ND1 , Y ND1 ), (X ND2 , Y ND2 ), (X MUX1 , Y MUX1 ), (X MUX2 , Y MUX2 ), (X BUF， Y BUF ) are all within the range of (X1, X2) and the Y coordinates are all within the range of (Y1, Y2), the coordinates X that meet the requirements will be obtained. ND1 , Y ND1 ), (X ND2 , Y ND2 ), (X MUX1 , Y MUX1 ), (X MUX2 , Y MUX2 ), (X BUF， Y BUF ), and then enter the next cycle i=i+1; when i=N cycles are completed, N groups of coordinates that meet the requirements can be obtained.

[0082] Use this algorithm to randomly generate N sets of coordinates for N featureless Latch PUF cell circuits. Then, use the placeInstance command to place the cells accordingly, and use the set_dont_touch command to ensure that these cells remain unchanged during the placement and routing optimization process.

[0083] Fig. 9 The overall layout after all digital cells are placed is shown, with the featureless Latch PUF cell circuit highlighted in red. It can be observed that the placement of standard cells in each featureless Latch PUF cell circuit is the same as Figure 4 By randomizing the locations of featureless Latch PUF cells, they are distributed among a large number of standard digital cells, effectively eliminating their layout features and reducing the likelihood of being identified or located by an attacker.

[0084] By adopting a symmetrical placement strategy for standard cells within the featureless Latch PUF unit circuit, optimizing the routing between standard cells, and randomly placing the featureless Latch PUF unit circuit, the Latch PUF can be hidden in a large number of digital standard cells, eliminating the circuit characteristics and image characteristics of the Latch PUF.

[0085] The embodiment of the present invention integrates the proposed featureless Latch PUF and uses the HJ standard 0.18μm CMOS process to implement chip tape-out and testing, wherein each chip contains 32 featureless Latch PUF units. It can be found that the image features of the Latch PUF are successfully eliminated, making it difficult for attackers to locate the Latch PUF unit through the image features.

[0086] In summary, according to the static hiding method of the Latch PUF unit circuit in the chip of the embodiment of the present invention, first, the standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate and the second NAND gate are respectively instantiated using the Verilog language; then, a circuit netlist of the Latch PUF unit circuit is generated according to the standard cells, and based on the circuit netlist, each standard cell is placed, and interconnection routing is performed between each standard cell, and instruction adjustment is performed after the interconnection routing to obtain the Latch PUF unit circuit, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; finally, multiple Latch PUF unit circuits are randomly placed in the chip layout according to random coordinates. Therefore, this method randomizes the position of the featureless Latch PUF unit circuit, and randomly distributes multiple Latch PUF unit circuits in a large number of standard digital units, effectively eliminating the circuit characteristics and image characteristics of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reducing the possibility of being identified or located by attackers, and improving the security of the chip.

[0087] Corresponding to the above embodiment, the present invention also proposes a computer-readable storage medium.

[0088] The computer-readable storage medium of the embodiment of the present invention stores a static hiding program of the Latch PUF unit circuit in the chip. When the static hiding program of the Latch PUF unit circuit in the chip is executed by the processor, the static hiding method of the Latch PUF unit circuit in the chip is implemented.

[0089] According to the computer-readable storage medium of the embodiment of the present invention, through the static hiding method of the Latch PUF unit circuit in the above-mentioned chip, the circuit characteristics and image characteristics of the Latch PUF can be effectively eliminated, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, thereby reducing the possibility of being identified or located by attackers and improving the security of the chip.

[0090] Corresponding to the above embodiment, the present invention further provides an electronic device.

[0091] Fig.10 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention.

[0092] like Fig.10 As shown, the electronic device 100 of an embodiment of the present invention includes: a memory 110 and a processor 120, wherein the memory 110 stores a program that can be run on the processor 120, and when the processor 120 executes the program, the static hiding method of the Latch PUF unit circuit in the above-mentioned chip is implemented.

[0093] According to the electronic device of the embodiment of the present invention, the circuit characteristics and image characteristics of the Latch PUF can be effectively eliminated through the static hiding method of the Latch PUF unit circuit in the chip, making it difficult for an attacker to locate the Latch PUF unit circuit through the image characteristics, thereby reducing the possibility of being identified or located by the attacker and improving the security of the chip.

[0094] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0095] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0097] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0098] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0099] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A static hiding method for a Latch PUF unit circuit in a chip, characterized in that: The chip includes a plurality of Latch PUF unit circuits, and the Latch PUF unit circuit includes an inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate, and a second NAND gate, wherein a transmission path from the buffer to the first multiplexer is a first path, a transmission path from the buffer to the second multiplexer is a second path, a transmission path from the first multiplexer to the first NAND gate is a third path, a transmission path from the second multiplexer to the second NAND gate is a fourth path, a transmission path from the output end of the second NAND gate to the input end of the first NAND gate is a fifth path, and a transmission path from the output end of the first NAND gate to the input end of the second NAND gate is a sixth path; the method includes: Instantiate standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate, and the second NAND gate respectively using Verilog language; Generating a circuit netlist of the Latch PUF unit circuit according to each of the standard cells; Based on the circuit netlist, each of the standard cells is placed, interconnection routing is performed between each of the standard cells, and instruction adjustment is performed after the interconnection routing, so as to obtain the Latch PUF unit circuit, wherein the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; A plurality of Latch PUF unit circuits are randomly placed in a chip layout according to random coordinates.

2. The static hiding method of the Latch PUF unit circuit in the chip according to claim 1, characterized in that: Placing each of the standard cells includes: The standard cells are placed symmetrically.

3. The static hiding method of the Latch PUF unit circuit in the chip according to claim 2, characterized in that: The standard units are placed symmetrically, including: Placing the standard unit of the first NAND gate and the standard unit of the second NAND gate in mirror-image symmetry, and determining an axis of symmetry; Placing the standard cell of the first multiplexer below the standard cell of the first NAND gate along the symmetry axis, and placing the mirror image of the standard cell of the second multiplexer below the standard cell of the second NAND gate along the symmetry axis, and the standard cell of the first multiplexer and the standard cell of the second multiplexer are mirror-symmetric; The standard cell of the buffer is placed below the standard cell of the second multiplexer along the symmetry axis.

4. The static hiding method of the Latch PUF unit circuit in the chip according to claim 3, characterized in that: Performing interconnection routing between the standard cells and adjusting instructions after the interconnection routing, including: Automatically placing and routing each of the standard cells; According to the length of each path after automatic layout and routing, instructions are adjusted for each path so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

5. The static hiding method of the Latch PUF unit circuit in the chip according to claim 1, characterized in that: A plurality of Latch PUF unit circuits are randomly placed in a chip layout according to random coordinates, including: Get the unit height, NAND gate area, multiplexer area, and buffer area of ​​the standard cell in the process library file; Determining a width of the NAND gate according to the area of ​​the NAND gate and the unit height; determining a width of the multiplexer according to an area of ​​the multiplexer and the unit height; determining a width of the buffer according to an area of ​​the buffer and the unit height; Obtaining the placement spacing and width of the WellTap units in the chip and the boundary coordinates of the WellTap units; Inputting the unit height, the width of the NAND gate, the width of the multiplexer, the width of the buffer, the placement spacing and width of the WellTap unit, and the boundary coordinates of the WellTap unit into a preset algorithm, and randomly generating a plurality of random coordinates; A plurality of Latch PUF unit circuits are placed in a chip layout according to the plurality of random coordinates.

6. The static hiding method of the Latch PUF unit circuit in the chip according to claim 5, characterized in that: The width of the NAND gate is determined by the following formula: Among them, W ND is the width of the NAND gate, A ND is the area of ​​the NAND gate, H cell is the unit height.

7. The static hiding method of the Latch PUF unit circuit in the chip according to claim 5, characterized in that: The width of the multiplexer is determined by the following formula: Among them, W MUX is the width of the multiplexer, A MUX is the area of ​​the multiplexer, H cell is the unit height.

8. The static hiding method of the Latch PUF unit circuit in the chip according to claim 5, characterized in that: The width of the buffer is determined by the following formula: Among them, W BUF is the width of the buffer, A BUF is the area of ​​the buffer, H cell is the unit height.

9. A computer-readable storage medium, characterized in that: A static hiding program of the Latch PUF unit circuit in the chip is stored thereon. When the static hiding program of the Latch PUF unit circuit in the chip is executed by the processor, the static hiding method of the Latch PUF unit circuit in the chip according to any one of claims 1 to 8 is implemented.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the memory stores a program that can be run on the processor, and when the processor executes the program, the static hiding method of the Latch PUF unit circuit in the chip according to any one of claims 1 to 8 is implemented.

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