A data cache remodeling method, device, equipment and storage medium

Abstract

The present application discloses a data cache remodeling method, device, equipment and storage medium, which relates to the field of cache design of general-purpose graphics processors, including: obtaining the number of thread blocks corresponding to a computing task in a stream multiprocessor located in a general-purpose graphics processor, and determining the corresponding target logical tag control word based on the number of thread blocks; the target logical tag control word is a logical tag control word used for data cache; obtaining the access address of the data cache set of the computing task, and determining the target physical tag control word using the target logical tag control word; remodeling the data cache set in a mapping manner and remodeling the capacity based on the target logical tag control word, the target physical tag control word and the access address, so as to determine the target data cache set of the computing task and the target access address of the target data cache set, so that the stream multiprocessor uses the target data cache set and the target access address to perform the computing task. The present application can effectively realize the dynamic adjustment of the cache resources of the computing task.

Description

Technical Field

[0001] The present invention relates to the field of general graphics processor cache design, and in particular to a data cache remodeling method, device, equipment and storage medium. Background Art

[0002] Due to their significant computing power, accelerators such as GPGPU (General-Purpose computing on Graphics Processing Units) are widely used for different workloads. GPGPU contains a large number of computing tasks, and the size of each computing task is different. Some computing tasks are relatively small and require relatively small storage resources, while some computing tasks are relatively large and require relatively large storage resources. Therefore, if all computing tasks use the same capacity cache, it will inevitably cause a waste of cache resources, such as space waste, performance waste, and energy waste. At the same time, if the associativity is set to a fixed mode, when the associativity is set too high, too many cache lines may be wasted waiting for reuse, especially when the cache miss rate is high. If the associativity is set too low, it may cause an increase in cache conflicts, which also affects the performance of data access during task execution. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide a data cache remodeling method, device, equipment and storage medium, which can effectively realize the dynamic adjustment of computing task cache resources, thereby reducing the waste of cache resources and improving data access performance. The specific scheme is as follows:

[0004] In a first aspect, the present application provides a data cache reshaping method, comprising:

[0005] Acquire the number of thread blocks corresponding to the computing task in the streaming multiprocessor in the general-purpose graphics processor, and determine the target logical tag control word corresponding to the computing task based on the number of thread blocks; the target logical tag control word is a logical tag control word used for data cache;

[0006] Acquire a memory access address of a data cache set corresponding to the computing task, and determine a corresponding target physical label control word using the target logical label control word;

[0007] The data cache set is reshaped in mapping mode and capacity based on the target logical tag control word, the target physical tag control word and the memory access address, so as to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the stream multiprocessor can use the target data cache set and the target memory access address to perform the computing task.

[0008] Optionally, the acquiring the memory access address of the data cache set corresponding to the computing task and determining the corresponding target physical tag control word by using the target logical tag control word includes:

[0009] Acquire, through a data loading component, a memory access address of a data cache set corresponding to the computing task;

[0010] The target logical tag control word is inverted to determine a target physical tag control word corresponding to the computing task.

[0011] Optionally, determining the target logical tag control word corresponding to the computing task based on the number of thread blocks includes:

[0012] After logical capacity is split based on the data cache capacity corresponding to the computing task, the size of the number of thread blocks is judged to trigger corresponding logical capacity allocation operations and logical tag control word generation operations based on the obtained judgment result and the logical capacity split result.

[0013] Optionally, the determining the size of the number of thread blocks to trigger corresponding logical capacity allocation operations and logical label control word generation operations based on the determination result and the logical capacity splitting result includes:

[0014] Determine the size of the number of thread blocks by presetting data level information to obtain a determination result;

[0015] If the judgment result indicates that the number of thread blocks belongs to a first preset value level, a first preset amount of logical capacity is allocated to the computing task based on the obtained logical capacity splitting result, and a corresponding first target logical label control word is determined;

[0016] If the judgment result indicates that the size of the number of thread blocks belongs to the second preset value level, a second preset amount of the logical capacity is allocated to the computing task based on the logical capacity splitting result, and a corresponding second target logical label control word is determined;

[0017] If the judgment result indicates that the number of thread blocks belongs to a third preset value level, a third preset amount of the logical capacity is allocated to the computing task based on the logical capacity splitting result, and a corresponding third target logical label control word is determined;

[0018] If the determination result indicates that the number of thread blocks belongs to a fourth preset value level, a fourth preset amount of the logical capacity is allocated to the computing task based on the logical capacity splitting result, and a corresponding fourth target logical label control word is determined.

[0019] Optionally, reshaping the data cache set in a mapping manner based on the target logical tag control word includes:

[0020] If the judgment result indicates that the size of the number of thread blocks belongs to the first preset numerical level, the cache mapping mode of the computing task is configured as direct mapping based on the first target logical tag control word to complete the corresponding first mapping mode reshaping operation;

[0021] If the judgment result indicates that the size of the number of thread blocks belongs to the second preset numerical level, the cache mapping mode of the computing task is configured as a two-way set-associative mapping mode based on the second target logical tag control word to complete the corresponding second mapping mode reshaping operation;

[0022] If the judgment result indicates that the size of the number of thread blocks belongs to the third preset numerical level, the cache mapping mode of the computing task is configured as a four-way set associative mapping mode based on the third target logical tag control word to complete the corresponding third mapping mode reshaping operation;

[0023] If the judgment result indicates that the size of the number of thread blocks belongs to the fourth preset numerical level, the cache mapping mode of the computing task is configured as an eight-way set-associative mapping mode based on the fourth target logical tag control word to complete the corresponding fourth mapping mode reshaping operation.

[0024] Optionally, reshaping the capacity of the data cache set based on the target logical tag control word, the target physical tag control word, and the memory access address includes:

[0025] Based on the cache mapping mode and the first preset number of the logical capacity, the data cache set is reshaped in quantity and capacity respectively to determine a first target data cache set of the computing task, and an AND operation is performed with the first target logical tag control word and the target data bit in the memory access address to determine a first target memory access address corresponding to the first target data cache set using the first AND operation result and the target physical tag control word;

[0026] Or, based on the cache mapping mode and the second preset number of logical capacities, the data cache set is reshaped in quantity and capacity respectively to determine a second target data cache set of the computing task, and an AND operation is performed with the second target logical tag control word and the target data bit in the memory access address to determine a second target memory access address corresponding to the second target data cache set using the second AND operation result and the target physical tag control word;

[0027] Or, based on the cache mapping mode and the third preset number of logical capacities, the data cache set is reshaped in quantity and capacity respectively to determine a third target data cache set of the computing task, and an AND operation is performed with the third target logical tag control word and the target data bit in the memory access address to determine a third target memory access address corresponding to the third target data cache set using the third AND operation result and the target physical tag control word;

[0028] Or, based on the cache mapping method and the fourth preset number of logical capacities, the data cache set is reshaped in quantity and capacity to determine a fourth target data cache set of the computing task, and an AND operation is performed with the target data bits in the memory access address through the fourth target logical tag control word to determine the fourth target memory access address corresponding to the fourth target data cache set using the fourth AND operation result and the target physical tag control word.

[0029] Optionally, after determining the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, the method further includes:

[0030] The cache mapping mode based on the computing task triggers a corresponding cache set clock enable start operation.

[0031] In a second aspect, the present application provides a data cache remodeling device, comprising:

[0032] A control word generation module, used to obtain the number of thread blocks corresponding to the computing task in the stream multiprocessor in the general graphics processor, and determine the target logical label control word corresponding to the computing task based on the number of thread blocks; the target logical label control word is a logical label control word used for data cache;

[0033] A memory access address acquisition module, used to acquire the memory access address of the data cache set corresponding to the computing task, and determine the corresponding target physical label control word using the target logical label control word;

[0034] A cache set reshaping module is used to reshape the mapping mode and capacity of the data cache set based on the target logical tag control word, the target physical tag control word and the memory access address, so as to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the stream multiprocessor can use the target data cache set and the target memory access address to perform the computing task.

[0035] In a third aspect, the present application provides an electronic device, including:

[0036] Memory, used to store computer programs;

[0037] A processor is used to execute the computer program to implement the steps of the aforementioned data cache reshaping method.

[0038] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the steps of the aforementioned data cache remodeling method.

[0039] It can be seen that in the present application, the number of thread blocks corresponding to the computing task in the streaming multiprocessor located in the general-purpose graphics processor is obtained, and the target logical tag control word corresponding to the computing task is determined based on the number of thread blocks; the target logical tag control word is a logical tag control word used for data cache; the memory access address of the data cache set corresponding to the computing task is obtained, and the corresponding target physical tag control word is determined using the target logical tag control word; based on the target logical tag control word, the target physical tag control word and the memory access address, the data cache set is respectively reshaped in mapping mode and capacity to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the streaming multiprocessor uses the target data cache set and the target memory access address to perform the computing task. That is, in this application, the target logical tag control word for data cache is first determined based on the number of thread blocks corresponding to the computing task, and then the corresponding target physical tag control word is determined using the target logical tag control word, and the data cache set is reshaped in mapping mode and capacity through the target logical tag control word, the target physical tag control word and the memory access address, so that the stream multiprocessor uses the reshaped target data cache set and the target memory access address to perform computing tasks. In this way, the dynamic adjustment of the computing task cache resources can be effectively realized, thereby reducing the waste of cache resources and improving the performance of data access. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0041] Figure 1 A flow chart of a data cache reshaping method provided in this application;

[0042] Figure 2 A schematic diagram of a general graphics processor architecture provided for this application;

[0043] Figure 3 A schematic diagram of a specific flow chart of generating a logical tag control word provided in this application;

[0044] Figure 4 A schematic diagram of cache remodeling provided for this application;

[0045] Figure 5 A data cache set control schematic diagram provided for this application;

[0046] Figure 6 A schematic diagram of the structure of a data cache remodeling device provided in this application;

[0047] Figure 7 A structural diagram of an electronic device provided for this application. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Due to the significant computing power, accelerators such as GPGPU are widely used for different workloads. GPGPU contains a large number of computing tasks, and the size of each computing task is different. Some computing tasks are relatively small and require relatively small storage resources. Some computing tasks are relatively large and require more storage resources. Therefore, if all computing tasks use the same capacity cache, it will inevitably cause a waste of cache resources, such as space waste, performance waste, and energy waste. At the same time, if the association is set to a fixed mode, when the association is set too high, too many cache lines may be wasted waiting for reuse, especially when the cache miss rate is high. If the association is set too low, it may cause an increase in cache conflicts, which also affects the performance of data access during task execution. To this end, the present application provides a data cache reshaping scheme that can effectively realize the dynamic adjustment of computing task cache resources, thereby reducing the waste of cache resources and improving the performance of data access.

[0050] See also Figure 1 As shown, an embodiment of the present invention discloses a data cache remodeling method, comprising:

[0051] Step S11, obtaining the number of thread blocks corresponding to the computing task in the streaming multiprocessor in the general graphics processor, and determining the target logical tag control word corresponding to the computing task based on the number of thread blocks; the target logical tag control word is a logical tag control word used for data cache.

[0052] Specific, combined Figure 2 As shown in the schematic diagram of the architecture, in this embodiment, a general-purpose graphics processor architecture capable of data cache remodeling is provided. In the general-purpose graphics processor of this architecture, a thread block scheduler and a stream multiprocessor are included. The thread block scheduler is used to send the number of thread blocks (i.e., Blocks) required to execute this computing task to the control word generation unit. The stream multiprocessor further includes a pre-stage pipeline, a control word generation component, a cache remodeling component, and a data cache set, of which the latter three constitute a data path. The front-stage pipeline is the instruction execution path of the front-stage pipeline in the stream multiprocessor, which usually includes instruction fetch, decoding, thread bundle scheduling, scoreboard, emission, data loading, execution and other stages. In the data loading stage, the memory access address to be loaded will be sent to the control word generation component; the control word generation component is used to generate the logical tag control word of the data cache according to the number of thread blocks sent by the thread block scheduler, and send it to the cache reshaping component; the cache reshaping component is used to receive the logical tag control word, and dynamically reshape the size of the data cache set, and turn off the clock of the unused cache set to reduce energy consumption; the data cache set can receive the reshaped memory access address and clock enable, and respond.

[0053] It can be understood that in this embodiment, the number of thread blocks corresponding to the computing task is first obtained through the thread block scheduler. Then, in the process of determining the target logical tag control word corresponding to the computing task based on the number of thread blocks, after performing logical capacity splitting based on the data cache capacity corresponding to the computing task, the size of the number of thread blocks is judged to trigger the corresponding logical capacity allocation operation and logical tag control word generation operation based on the obtained judgment result and the logical capacity splitting result.

[0054] Further, regarding the process of allocating logical capacity and generating logical label control words by judging the size of the number of thread blocks, first, the size of the number of thread blocks is judged by preset data level information to obtain a judgment result. Then, the judgment result is analyzed. If the judgment result shows that the size of the number of thread blocks belongs to the first preset numerical level, the first preset amount of logical capacity is allocated to the computing task based on the obtained logical capacity splitting result, and the corresponding first target logical label control word is determined; if the judgment result shows that the size of the number of thread blocks belongs to the second preset numerical level, the second preset amount of logical capacity is allocated to the computing task based on the logical capacity splitting result, and the corresponding second target logical label control word is determined; if the judgment result shows that the size of the number of thread blocks belongs to the third preset numerical level, the third preset amount of logical capacity is allocated to the computing task based on the logical capacity splitting result, and the corresponding third target logical label control word is determined; if the judgment result shows that the size of the number of thread blocks belongs to the fourth preset numerical level, the fourth preset amount of logical capacity is allocated to the computing task based on the logical capacity splitting result, and the corresponding fourth target logical label control word is determined.

[0055] Combination Figure 3 As shown, in a specific implementation, if the data cache capacity is 128KB at most, a maximum of 8 thread blocks can be assigned to a stream multiprocessor to work, and the entire 128KB physical cache is divided into 8 16KB logical cache sets, where each cache set size is 16KB. When the control word generation component receives the number of thread blocks, it will split the 128KB data cache into logical capacities for use. When it is determined to be 1 thread block (i.e., the first preset numerical level), a logical capacity of 16KB is allocated to it, and the first target logical label control word, i.e., 000000, is output; when it is determined to be 2 thread blocks (i.e., the second preset numerical level), in order to improve the cache hit rate of each thread block, a logical capacity of 32KB is allocated to it, and the second target logical label control word, i.e., 000001, is output; when it is determined to be 3~4 thread blocks (i.e., the third preset numerical level), a logical capacity of 64KB is allocated to it, and the third target logical label control word, i.e., 000011, is output; when it is determined to be 5~8 thread blocks (i.e., the fourth preset numerical level), a logical capacity of 128KB is allocated to it, and the logical capacity is also equal to the physical capacity at this time, and the fourth target logical label control word, i.e., 000111, is output.

[0056] Step S12: Obtain a memory access address of a data cache set corresponding to the computing task, and use the target logical tag control word to determine a corresponding target physical tag control word.

[0057] In this embodiment, the access address of the data cache set corresponding to the computing task is obtained through the data loading component, and the target physical tag control word corresponding to the computing task can be determined by inverting the target logical tag control word.

[0058] Step S13, based on the target logical tag control word, the target physical tag control word and the memory access address, the data cache set is respectively reshaped in mapping mode and capacity to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the stream multiprocessor can use the target data cache set and the target memory access address to perform the computing task.

[0059] It should be understood that, regarding the mapping mode reshaping, in this embodiment, by analyzing the judgment results, if the judgment result shows that the size of the number of thread blocks belongs to the first preset numerical level, the cache mapping mode of the operation task is configured as direct mapping based on the first target logical label control word to complete the corresponding first mapping mode reshaping operation; if the judgment result shows that the size of the number of thread blocks belongs to the second preset numerical level, the cache mapping mode of the operation task is configured as a two-way group-associated mapping mode based on the second target logical label control word to complete the corresponding second mapping mode reshaping operation; if the judgment result shows that the size of the number of thread blocks belongs to the third preset numerical level, the cache mapping mode of the operation task is configured as a four-way group-associated mapping mode based on the third target logical label control word to complete the corresponding third mapping mode reshaping operation; if the judgment result shows that the size of the number of thread blocks belongs to the fourth preset numerical level, the cache mapping mode of the operation task is configured as an eight-way group-associated mapping mode based on the fourth target logical label control word to complete the corresponding fourth mapping mode reshaping operation.

[0060] Combination Figure 3 As shown, in a specific implementation, if the data cache capacity is 128KB at most, a maximum of 8 thread blocks can be assigned to a stream multiprocessor to work. When the control word generation component receives the number of thread blocks, it will split the 128KB data cache into logical capacity for use. When it is determined to be 1 (i.e., the first preset numerical level) thread block, its mapping mode is configured as direct mapping; when it is determined to be 2 (i.e., the second preset numerical level) thread blocks, in order to improve the cache hit rate of each thread block, its mapping mode is configured as a two-way set-associative mode (i.e., 2WAY); when it is determined to be 3~4 (i.e., the third preset numerical level) thread blocks, its mapping mode is configured as a four-way set-associative mode (i.e., 4WAY); when it is determined to be 5~8 (i.e., the fourth preset numerical level) thread blocks, its mapping mode is configured as an eight-way set-associative mode (i.e., 8WAY).

[0061] Further, regarding the reshaping of the memory access address, in this embodiment, the data cache set is reshaped in quantity and capacity based on the cache mapping method and the first preset number of logical capacities to determine the first target data cache set of the computing task, and the first target logical tag control word is used to perform an AND operation with the target data bit in the memory access address, so as to determine the first target memory access address corresponding to the first target data cache set using the first AND operation result and the target physical tag control word. Or, the data cache set is reshaped in quantity and capacity based on the cache mapping method and the second preset number of logical capacities to determine the second target data cache set of the computing task, and the second target logical tag control word is used to perform an AND operation with the target data bit in the memory access address, so as to determine the second target memory access address corresponding to the second target data cache set using the second AND operation result and the target physical tag control word. Or, the data cache set is reshaped in quantity and capacity based on the cache mapping method and the third preset number of logical capacities to determine the third target data cache set of the computing task, and the third target logical tag control word is used to perform an AND operation with the target data bit in the memory access address, so as to determine the third target memory access address corresponding to the third target data cache set using the third AND operation result and the target physical tag control word. Or, based on the cache mapping mode and the fourth preset number of logical capacities, the data cache set is reshaped in quantity and capacity respectively to determine the fourth target data cache set of the computing task, and the fourth target logical tag control word is used to perform an AND operation with the target data bit in the memory access address, so as to determine the fourth target memory access address corresponding to the fourth target data cache set using the fourth AND operation result and the target physical tag control word. And, then, the corresponding cache set clock enable start operation is triggered based on the cache mapping mode of the computing task.

[0062] Combination Figure 4 As shown, in a specific implementation, when reshaping the memory access address, (1) if the logic tag control word L is 000000, then its difference from the original memory access address A is After the bit phase and the bits are all 0, the physical tag control word P is all 1, indicating that the original memory address All bits are used as physical tags, and after ANDing, they form a physical tag index. At this time, the target memory access address of the reshaped cache (that is, the data cache set) is composed of: the original memory access address bit as a physical tag, the original memory address bit as the cache line index, the original access address bits as byte offset, and only 16KB of logical capacity is used in the cache set, based on the enable control component, only one cache set clock enable is turned on. (2) If the logical tag control word is 000001, then it is the same as the original memory address. After the bit phase and, the 14th bit is used as the logical tag address. At this time, the physical tag control word is 111110, indicating that the original memory address The final reshaped target memory access address is composed of: The 14th bit of the original memory address is used as the logical label. bit as the cache line index, the original access address bits as byte offset, and the cache set used is 32KB, and the clock enable of the two cache sets is turned on. Similarly, (3) if the logic control word is 000011, the composition of the target memory access address obtained at this time is: bit as a physical tag, the original memory address bit as a logical label, the original memory address The [3,0] bits of the original memory access address are used as the cache line index, and the clock enable of the four cache sets is turned on. The cache set used is 64KB. (4) If the logic control word is 000111, the composition of the reshaped target memory access address is: bit as a physical tag, the original memory address bit as a logical label, the original memory address bit as the cache line index, the original access address bits as byte offsets to turn on the clock enables for 8 cache sets, and the cache set used is 128KB.

[0063] like Figure 5 As shown in the figure, the working status of the cache set under the above four mapping modes is shown. The entire 128KB physical cache is divided into 8 16KB logical cache sets, where the size of each cache set is 16KB. According to the reshaped target memory access address and clock control signal passed in, when the logical capacity is 16KB and direct mapping is used, there is only one cache set (i.e. Figure 5 The data cache set 0 marked in red works; when the logical capacity is 32KB and 2WAY mapping is adopted (one cache set is used as a WAY), there are only 2 cache sets (i.e. Figure 5 The data cache sets 0 and 1 marked in red are working; when the logical capacity is 64KB and 4WAY mapping is used, there are only 4 cache sets (i.e. Figure 5 The data cache sets marked in red (0, 1, 2, and 3) work; when the logical capacity is 128KB and 8WAY mapping is used, 8 cache sets (i.e. Figure 5 The data cache sets marked in red (0, 1, 2, ..., 7) are all working.

[0064] In summary, a method for data cache reshaping based on GPGPU is proposed in this embodiment. Since the locality of data between each block in GPGPU is poor, this method can dynamically reshape the cache capacity and mapping method according to the number of blocks allocated to the SM core (Stream Multi-processor) in the current GPGPU, and close the unused cache, thereby effectively improving performance and reducing power consumption.

[0065] It can be seen that in an embodiment of the present application, the number of thread blocks corresponding to the computing task in the streaming multiprocessor located in the general-purpose graphics processor is obtained, and the target logical tag control word corresponding to the computing task is determined based on the number of thread blocks; the target logical tag control word is a logical tag control word used for data caching; the memory access address of the data cache set corresponding to the computing task is obtained, and the corresponding target physical tag control word is determined using the target logical tag control word; based on the target logical tag control word, the target physical tag control word and the memory access address, the data cache set is respectively reshaped in mapping mode and capacity to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the streaming multiprocessor uses the target data cache set and the target memory access address to perform the computing task. That is, in this application, the target logical tag control word for data cache is first determined based on the number of thread blocks corresponding to the computing task, and then the corresponding target physical tag control word is determined using the target logical tag control word, and the data cache set is reshaped in mapping mode and capacity through the target logical tag control word, the target physical tag control word and the memory access address, so that the stream multiprocessor uses the reshaped target data cache set and the target memory access address to perform computing tasks. In this way, the dynamic adjustment of the computing task cache resources can be effectively realized, thereby reducing the waste of cache resources and improving the performance of data access.

[0066] See also Figure 6 As shown, the embodiment of the present application also discloses a data cache reshaping device, including:

[0067] The control word generation module 11 is used to obtain the number of thread blocks corresponding to the computing task in the stream multiprocessor in the general graphics processor, and determine the target logical label control word corresponding to the computing task based on the number of thread blocks; the target logical label control word is a logical label control word used for data cache;

[0068] A memory access address acquisition module 12, used to acquire the memory access address of the data cache set corresponding to the computing task, and determine the corresponding target physical label control word using the target logical label control word;

[0069] The cache set reshaping module 13 is used to reshape the mapping mode and capacity of the data cache set based on the target logical tag control word, the target physical tag control word and the memory access address, so as to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the stream multiprocessor can use the target data cache set and the target memory access address to perform the computing task.

[0070] Among them, for more specific working processes of the above-mentioned modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0071] It can be seen that in this application, the target logical tag control word for data cache is first determined based on the number of thread blocks corresponding to the computing task, and then the corresponding target physical tag control word is determined using the target logical tag control word, and the data cache set is reshaped in mapping mode and capacity through the target logical tag control word, the target physical tag control word and the memory access address, so that the stream multiprocessor can use the target data cache set and target memory access address determined after the reshaping to perform computing tasks. In this way, the dynamic adjustment of the computing task cache resources can be effectively realized, thereby reducing the waste of cache resources and improving the performance of data access.

[0072] In some specific embodiments, the memory access address acquisition module 12 may specifically include:

[0073] An address acquisition unit, used for acquiring a memory access address of a data cache set corresponding to the computing task through a data loading component;

[0074] The physical label control word acquisition unit is used to invert the target logical label control word to determine the target physical label control word corresponding to the computing task.

[0075] In some specific embodiments, the control word generation module 11 may specifically include:

[0076] The control word generation submodule is used to trigger corresponding logical capacity allocation operations and logical label control word generation operations based on the obtained judgment result and the logical capacity splitting result by judging the size of the number of thread blocks after performing logical capacity splitting based on the data cache capacity corresponding to the computing task.

[0077] In some specific embodiments, the control word generation submodule may specifically include:

[0078] A size determination unit, used for determining the size of the number of thread blocks by preset data level information to obtain a determination result;

[0079] A first capacity reshaping unit is configured to allocate a first preset amount of logical capacity to the computing task based on the obtained logical capacity splitting result if the judgment result indicates that the number of thread blocks belongs to a first preset value level, and determine a corresponding first target logical label control word;

[0080] A second capacity reshaping unit is configured to allocate a second preset amount of the logical capacity to the computing task based on the logical capacity splitting result if the judgment result indicates that the number of thread blocks belongs to a second preset value level, and determine a corresponding second target logical label control word;

[0081] A third capacity reshaping unit is configured to allocate a third preset amount of the logical capacity to the computing task based on the logical capacity splitting result if the judgment result indicates that the size of the number of thread blocks belongs to a third preset value level, and determine a corresponding third target logical label control word;

[0082] The fourth capacity reshaping unit is used to allocate a fourth preset number of the logical capacity to the computing task based on the logical capacity splitting result if the judgment result indicates that the size of the number of thread blocks belongs to a fourth preset numerical level, and determine the corresponding fourth target logical label control word.

[0083] In some specific embodiments, the data cache remodeling device may specifically include:

[0084] A first mapping mode reshaping unit is configured to configure the cache mapping mode of the computing task to direct mapping based on the first target logical tag control word if the judgment result indicates that the size of the number of thread blocks belongs to the first preset numerical level, so as to complete the corresponding first mapping mode reshaping operation;

[0085] A second mapping mode reshaping unit is configured to configure the cache mapping mode of the computing task as a two-way set-associative mapping mode based on the second target logical tag control word if the judgment result indicates that the size of the number of thread blocks belongs to the second preset numerical level, so as to complete a corresponding second mapping mode reshaping operation;

[0086] A third mapping mode reshaping unit is configured to configure the cache mapping mode of the computing task to a four-way set associative mapping mode based on the third target logical tag control word if the judgment result indicates that the size of the number of thread blocks belongs to the third preset numerical level, so as to complete the corresponding third mapping mode reshaping operation;

[0087] A fourth mapping mode reshaping unit is used to configure the cache mapping mode of the computing task to an eight-way set-associative mapping mode based on the fourth target logical tag control word if the judgment result indicates that the size of the number of thread blocks belongs to the fourth preset numerical level, so as to complete the corresponding fourth mapping mode reshaping operation.

[0088] In some specific embodiments, the data cache remodeling device may specifically include:

[0089] A first target memory access address determination unit is used to reshape the quantity and capacity of the data cache set based on the cache mapping mode and the first preset number of logical capacities, so as to determine a first target data cache set of the computing task, and perform an AND operation with the target data bit in the memory access address through the first target logical tag control word, so as to determine a first target memory access address corresponding to the first target data cache set using a first AND operation result and the target physical tag control word;

[0090] A second target memory access address determination unit is used for, or, based on the cache mapping mode and the second preset number of logical capacities, respectively reshaping the data cache set in quantity and capacity to determine a second target data cache set for the computing task, and performing an AND operation with the target data bit in the memory access address through the second target logical tag control word, so as to determine a second target memory access address corresponding to the second target data cache set using a second AND operation result and the target physical tag control word;

[0091] A third target memory access address determination unit is used for, or, based on the cache mapping mode and the third preset number of the logical capacity, respectively reshaping the data cache set in quantity and capacity to determine a third target data cache set of the computing task, and performing an AND operation with the target data bit in the memory access address through the third target logical tag control word, so as to determine a third target memory access address corresponding to the third target data cache set using a third AND operation result and the target physical tag control word;

[0092] A fourth target memory access address determination unit is used for, based on the cache mapping method and the fourth preset number of logical capacities, respectively reshaping the quantity and capacity of the data cache set to determine the fourth target data cache set of the computing task, and performing an AND operation with the target data bit in the memory access address through the fourth target logical tag control word to determine the fourth target memory access address corresponding to the fourth target data cache set using the fourth AND operation result and the target physical tag control word.

[0093] In some specific embodiments, the data cache remodeling device may further include:

[0094] A clock enable unit is used to trigger a corresponding cache set clock enable operation based on the cache mapping mode of the computing task.

[0095] Furthermore, the present application also discloses an electronic device. Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0096] Figure 7 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data cache remodeling method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0097] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0098] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0099] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the data cache remodeling method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0100] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed data cache remodeling method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0101] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0102] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0103] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0104] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0105] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data cache remodeling method, characterized in that: include: Acquire the number of thread blocks corresponding to the computing task in the streaming multiprocessor in the general-purpose graphics processor, and determine the target logical tag control word corresponding to the computing task based on the number of thread blocks; the target logical tag control word is a logical tag control word used for data cache; Acquire a memory access address of a data cache set corresponding to the computing task, and determine a corresponding target physical label control word using the target logical label control word; The data cache set is reshaped in mapping mode and capacity based on the target logical tag control word, the target physical tag control word and the memory access address, so as to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the stream multiprocessor can use the target data cache set and the target memory access address to perform the computing task.

2. The data cache remodeling method according to claim 1, characterized in that: The acquiring the memory access address of the data cache set corresponding to the computing task and determining the corresponding target physical label control word by using the target logical label control word comprises: Acquire, through a data loading component, a memory access address of a data cache set corresponding to the computing task; The target logical tag control word is inverted to determine a target physical tag control word corresponding to the computing task.

3. The data cache remodeling method according to claim 1, characterized in that: The determining of the target logical tag control word corresponding to the computing task based on the number of thread blocks includes: After performing logical capacity splitting based on the data cache capacity corresponding to the computing task, the size of the number of thread blocks is judged to trigger corresponding logical capacity allocation operations and logical tag control word generation operations based on the obtained judgment result and the logical capacity splitting result.

4. The data cache remodeling method according to claim 3, characterized in that: The determining the size of the number of thread blocks to trigger corresponding logical capacity allocation operations and logical label control word generation operations based on the determination result and the logical capacity splitting result includes: Determine the size of the number of thread blocks by using preset data level information to obtain a determination result; If the judgment result indicates that the number of thread blocks belongs to a first preset value level, a first preset amount of logical capacity is allocated to the computing task based on the obtained logical capacity splitting result, and a corresponding first target logical label control word is determined; If the judgment result indicates that the size of the number of thread blocks belongs to the second preset value level, a second preset amount of the logical capacity is allocated to the computing task based on the logical capacity splitting result, and a corresponding second target logical label control word is determined; If the judgment result indicates that the number of thread blocks belongs to a third preset value level, a third preset amount of the logical capacity is allocated to the computing task based on the logical capacity splitting result, and a corresponding third target logical label control word is determined; If the determination result indicates that the number of thread blocks belongs to a fourth preset value level, a fourth preset amount of the logical capacity is allocated to the computing task based on the logical capacity splitting result, and a corresponding fourth target logical label control word is determined.

5. The data cache remodeling method according to claim 4, characterized in that: Reshaping the data cache set in a mapping manner based on the target logical tag control word includes: If the judgment result indicates that the size of the number of thread blocks belongs to the first preset numerical level, the cache mapping mode of the computing task is configured as direct mapping based on the first target logical tag control word to complete the corresponding first mapping mode reshaping operation; If the judgment result indicates that the size of the number of thread blocks belongs to the second preset numerical level, the cache mapping mode of the computing task is configured as a two-way set-associative mapping mode based on the second target logical tag control word to complete the corresponding second mapping mode reshaping operation; If the judgment result indicates that the size of the number of thread blocks belongs to the third preset numerical level, the cache mapping mode of the computing task is configured as a four-way set associative mapping mode based on the third target logical tag control word to complete the corresponding third mapping mode reshaping operation; If the judgment result indicates that the size of the number of thread blocks belongs to the fourth preset numerical level, the cache mapping mode of the computing task is configured as an eight-way set-associative mapping mode based on the fourth target logical tag control word to complete the corresponding fourth mapping mode reshaping operation.

6. The data cache remodeling method according to claim 5, characterized in that: Reshaping the capacity of the data cache set based on the target logical tag control word, the target physical tag control word, and the memory access address includes: Based on the cache mapping mode and the first preset number of the logical capacity, the data cache set is reshaped in quantity and capacity respectively to determine a first target data cache set of the computing task, and an AND operation is performed with the first target logical tag control word and the target data bit in the memory access address to determine a first target memory access address corresponding to the first target data cache set using the first AND operation result and the target physical tag control word; Or, based on the cache mapping mode and the second preset number of logical capacities, the data cache set is reshaped in quantity and capacity respectively to determine a second target data cache set of the computing task, and an AND operation is performed with the second target logical tag control word and the target data bit in the memory access address to determine a second target memory access address corresponding to the second target data cache set using the second AND operation result and the target physical tag control word; Or, based on the cache mapping mode and the third preset number of logical capacities, the data cache set is reshaped in quantity and capacity respectively to determine a third target data cache set of the computing task, and an AND operation is performed with the third target logical tag control word and the target data bit in the memory access address to determine a third target memory access address corresponding to the third target data cache set using the third AND operation result and the target physical tag control word; Or, based on the cache mapping method and the fourth preset number of logical capacities, the data cache set is reshaped in quantity and capacity to determine a fourth target data cache set of the computing task, and an AND operation is performed with the target data bits in the memory access address through the fourth target logical tag control word to determine the fourth target memory access address corresponding to the fourth target data cache set using the fourth AND operation result and the target physical tag control word.

7. The data cache remodeling method according to claim 5, characterized in that: After determining the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, the method further includes: The cache mapping mode based on the computing task triggers a corresponding cache set clock enable start operation.

8. A data cache remodeling device, characterized in that: include: A control word generation module, used to obtain the number of thread blocks corresponding to the computing task in the stream multiprocessor in the general graphics processor, and determine the target logical tag control word corresponding to the computing task based on the number of thread blocks; the target logical tag control word is a logical tag control word used for data cache; A memory access address acquisition module, used to acquire the memory access address of the data cache set corresponding to the computing task, and determine the corresponding target physical label control word using the target logical label control word; A cache set reshaping module is used to reshape the mapping mode and capacity of the data cache set based on the target logical tag control word, the target physical tag control word and the memory access address, so as to determine the target data cache set of the computing task and the target memory access address corresponding to the target data cache set, so that the stream multiprocessor can use the target data cache set and the target memory access address to perform the computing task.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the data cache reshaping method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the data cache reshaping method as described in any one of claims 1 to 7.

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