Gate drive circuit, array substrate, display panel and display equipment

Abstract

The invention discloses a gate drive circuit, an array substrate, a display panel and a display device. The gate drive circuit comprises a plurality of gate drive units, each gate drive unit comprises an input circuit and an output circuit, and the input circuit receives input voltage and writes the input voltage into a pull-up node; the output circuit is used for outputting a gate driving signal through an output node of the gate driving unit, the gate driving signal is determined according to an input voltage written into the pull-up node, the output circuit is electrically connected with the pull-up node and the output node, and the pull-up node is directly connected with the output node. According to the gate drive circuit, the pull-up node and the output node of the gate drive unit are directly connected, an original capacitor for connecting the pull-up node and the output node is omitted, the space occupied by the gate drive unit in a layout is reduced, and therefore a narrow frame scheme is achieved while the safe distance is met; after the capacitor is deleted, the output capability of the gate driving unit is improved, and the low-temperature starting voltage is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and more specifically, to a gate drive circuit, an array substrate, a display panel and a display device. Background Art

[0002] With the continuous advancement of flat panel display technology, liquid crystal displays have been successfully applied to a variety of display devices. In order to meet the demand for narrow borders, the space of the gate drive circuit is constantly being optimized. In related technologies, the gate drive circuit space is compressed by compressing the line width of the signal line and reducing the distance between the glass edge and the signal line. However, due to the limitations of corrosion resistance and antistatic capabilities, the space occupied by the signal line is close to the limit, and the space occupied by the gate drive circuit cannot be further compressed. Summary of the invention

[0003] Embodiments of the present invention provide a gate driving circuit, an array substrate, a display panel and a display device.

[0004] An embodiment of the present invention provides a gate driving circuit, which includes multiple gate driving units, and the gate driving units include: an input circuit and an output circuit, the input circuit is used to receive an input voltage and write the input voltage into a pull-up node, and the input circuit is electrically connected to the pull-up node; the output circuit is used to output a gate driving signal through an output node of the gate driving unit, and the gate driving signal is determined according to the input voltage written into the pull-up node, and the output circuit is electrically connected to the pull-up node and the output node; the pull-up node and the output node are directly connected.

[0005] In this way, the input voltage received by the gate driving unit is written into the pull-up node through the input circuit, and the output circuit outputs the gate driving signal according to the input voltage at the pull-up node to drive the corresponding pixel to work; the pull-up node and the output node of the gate driving unit are directly connected, and the original capacitor connecting the pull-up node and the output node is deleted, thereby reducing the space occupied by the gate driving unit in the layout, so that a narrow frame solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit is increased, and the low-temperature starting voltage is improved.

[0006] In some embodiments, the input circuit includes a first transistor, a gate and a drain of the first transistor are electrically connected to an input signal line for providing an input signal, and a source of the first transistor is electrically connected to the pull-up node.

[0007] In this way, the first transistor is turned on when the input voltage is at a high level, so that the input voltage can be written into the pull-up node, thereby raising the potential of the pull-up node, so that the output circuit can output a gate driving signal.

[0008] In some embodiments, the gate driving unit further includes a reset circuit, and the reset circuit is used to receive a reset signal and reset the pull-up node.

[0009] In this way, a reset circuit is provided to reset the pull-up node, so as to lower the potential of the pull-up node and prevent the components of the gate driving unit from being damaged due to maintaining a high potential for a long time.

[0010] In some embodiments, the reset circuit also includes a second transistor, the gate of the second transistor is connected to a reset signal line, the reset signal line is used to provide a reset signal, the source of the second transistor is connected to a first voltage line, the first voltage line is used to provide a low level, and the second transistor is electrically connected to the pull-up node.

[0011] In this way, the second transistor can reset the pull-up node under the control of the reset signal.

[0012] In some embodiments, upon receiving a reset signal, the second transistor is used to connect the first voltage line and the pull-up node to reset the pull-up node.

[0013] In this way, the second transistor can reset the pull-up node under the control of the reset signal. When the reset signal is at a high level, the second transistor is turned on so that the low level of the first voltage line can be input to the pull-up node, pulling down the potential of the pull-up node, thereby resetting the pull-up node.

[0014] In some embodiments, the output circuit includes a third transistor, a gate of the third transistor is electrically connected to the pull-up node, a drain of the third transistor is connected to a clock signal line, the clock signal line is used to provide a clock signal, and a source of the third transistor is electrically connected to an output node of the gate drive unit to output the gate drive signal through the output node.

[0015] In this way, the potential of the pull-up node can control the output of the third transistor, so that the third transistor is turned on, thereby connecting the clock signal line and the output node, so that the gate drive signal can be output according to the clock signal.

[0016] In some embodiments, the gate driving unit further includes a pull-down circuit, the pull-down circuit is used to pull down the potential of the pull-up node, the pull-down circuit connects a first voltage line and the pull-up node, and the first voltage line is used to provide a low level.

[0017] In this way, the potential of the pull-up node is pulled down by the pull-down circuit, so that the potential of the pull-up node can be pulled down, thereby avoiding damage to the third transistor due to long-term bias.

[0018] In some embodiments, the pull-down circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the source of the fourth transistor is electrically connected to the pull-down node, the drain of the fourth transistor is connected to a second voltage line, and the second voltage line is used to input a high level; the gate of the fifth transistor is electrically connected to the pull-up node, the drain of the fifth transistor is electrically connected to the pull-down node, and the source of the fifth transistor is connected to the first voltage line; the gate of the sixth transistor is electrically connected to the pull-up node, and the source of the sixth transistor is connected to the first voltage line; the gate and drain of the seventh transistor are both connected to the second voltage line, and the source of the seventh transistor is connected to the drain of the sixth transistor and the gate of the fourth transistor.

[0019] In this way, by lowering the potential of the pull-up node through the pull-down circuit, the potential of the pull-up node can be continuously pulled down, so as to reduce the noise of the pull-up node and thus reduce the output ripple.

[0020] In some embodiments, the gate driving unit further includes a noise reduction circuit, wherein the noise reduction circuit is used to reduce noise of the gate driving unit, and the noise reduction circuit is connected to a first voltage line, wherein the first voltage line is used to provide a low level.

[0021] In this way, the gate driving unit and the first voltage line are connected through the noise reduction circuit, so that the first voltage line can pull down the potential of the gate driving unit to achieve resetting of the gate driving unit, thereby performing noise reduction.

[0022] In some embodiments, the noise reduction circuit includes an eighth transistor, which is used to perform noise reduction on the pull-up node, the gate of the eighth transistor is connected to the start control line, the drain of the eighth transistor is connected to the pull-up node, the source of the eighth transistor is connected to the first voltage line, and the start control line is only used to control the noise reduction of the pull-up node.

[0023] Thus, the first voltage line and the pull-up node are connected through the eighth transistor at the control line of the start control line, so that the low level transmitted by the first voltage line can lower the potential of the pull-up node, thereby resetting the pull-up node and achieving noise reduction for the pull-up node.

[0024] In some embodiments, the noise reduction circuit includes a ninth transistor, which is used to perform noise reduction on the pull-up node, the gate of the ninth transistor is connected to the pull-down node, the drain of the ninth transistor is connected to the pull-up node, the source of the ninth transistor is connected to the first voltage line, and the ninth transistor is used to perform noise reduction on the pull-up node according to the potential of the pull-down node.

[0025] In this way, the ninth transistor is turned on under the control of the pull-down node, thereby connecting the pull-up node and the first voltage line, so that the low level transmitted by the first voltage line can lower the potential of the pull-up node to achieve noise reduction for the pull-up node.

[0026] In some embodiments, the noise reduction circuit includes a tenth transistor, which is used to reduce the noise of the output node of the gate driving unit, the gate of the tenth transistor is electrically connected to the pull-down node, the drain of the tenth transistor is electrically connected to the output node, and the source of the tenth transistor is connected to the first voltage line.

[0027] In this way, the tenth transistor under the control of the pull-down node is turned on, so that the connection between the first voltage line and the output node is connected, the low level transmitted by the first voltage line is input to the output node, and the potential of the output node is pulled down, thereby achieving noise reduction of the output node.

[0028] An embodiment of the present invention provides an array substrate, which includes a gate driving circuit and a via hole according to any of the above embodiments. The gate driving circuit also includes a signal line, and the gate driving unit and the signal line are electrically connected through the via hole.

[0029] In this way, the input voltage received by the gate driving unit of the array substrate is written into the pull-up node through the input circuit, and the output circuit outputs the gate driving signal according to the input voltage at the pull-up node to drive the corresponding pixel to work; the pull-up node and the output node of the gate driving unit are directly connected, and the original capacitor connecting the pull-up node and the output node is deleted, thereby reducing the space occupied by the gate driving unit in the layout, so that a narrow frame solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit is increased, and the low-temperature starting voltage is improved.

[0030] In some embodiments, the vias include a plurality of high potential vias, the high potential vias are arranged in a single pair, and the high potential vias maintain a high potential within a set time.

[0031] In this way, by setting the vias that maintain a high potential within a set time to a single pair, the space occupied on the layout is saved to better meet the requirements of a narrow frame.

[0032] An embodiment of the present invention provides a display panel, which includes an array substrate and pixels according to any one of the above embodiments, wherein a gate driving unit of the array substrate is used to drive the pixels.

[0033] In this way, the input voltage received by the gate driving unit of the display panel is written into the pull-up node through the input circuit, and the output circuit outputs the gate driving signal according to the input voltage at the pull-up node to drive the corresponding pixel to work; the pull-up node and the output node of the gate driving unit are directly connected, and the original capacitor connecting the pull-up node and the output node is deleted, thereby reducing the space occupied by the gate driving unit in the layout, so that a narrow frame solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit is increased, and the low-temperature starting voltage is improved.

[0034] An embodiment of the present invention provides a display device, which includes a housing and the display panel of the above embodiment, wherein the display panel is disposed in the housing.

[0035] In this way, the input voltage received by the gate driving unit of the display panel is written into the pull-up node through the input circuit, and the output circuit outputs the gate driving signal according to the input voltage at the pull-up node to drive the corresponding pixel to work; the pull-up node and the output node of the gate driving unit are directly connected, and the original capacitor connecting the pull-up node and the output node is deleted, thereby reducing the space occupied by the gate driving unit in the layout, so that a narrow frame solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit is increased, and the low-temperature starting voltage is improved.

[0036] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0038] Figure 1 is a schematic diagram of a gate driving unit according to an embodiment of the present invention;

[0039] Figure 2 is a schematic diagram of a gate driving unit of the related art;

[0040] Figure 3 is a timing diagram of a gate driving unit according to an embodiment of the present invention;

[0041] Figure 4 It is a schematic diagram of the layout space occupied by the gate driving unit of the related art;

[0042] Figure 5 is a schematic diagram of the layout space occupied by the gate driving unit according to an embodiment of the present invention;

[0043] Figure 6 is a schematic diagram of a via hole according to an embodiment of the present invention;

[0044] Figure 7 is a schematic diagram of a via hole in the related art. DETAILED DESCRIPTION

[0045] The embodiments of the present invention are described in detail below, and the embodiments of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0046] With the continuous advancement of flat panel display technology, liquid crystal displays have been successfully applied to a variety of display devices. In order to meet the demand for narrow borders, the space of the gate drive circuit is constantly being optimized. In related technologies, the gate drive circuit space is compressed by compressing the line width of the signal line and reducing the distance between the glass edge and the signal line. However, due to the limitations of corrosion resistance and antistatic capabilities, the space occupied by the signal line is close to the limit, and the space occupied by the gate drive circuit cannot be further compressed.

[0047] See also Figure 1 An embodiment of the present invention provides a gate driving circuit, the gate driving circuit includes a plurality of gate driving units 10, the gate driving unit 10 includes: an input circuit 11 and an output circuit 12, the input circuit 11 is used to receive an input voltage and write the input voltage into a pull-up node PU, the input circuit 11 is electrically connected to the pull-up node PU; the output circuit 12 is used to output a gate driving signal through an output node OUTPUT of the gate driving unit 10, the gate driving signal is determined according to the input voltage written into the pull-up node PU, the output circuit 12 is electrically connected to the pull-up node PU and the output node OUTPUT; the pull-up node PU and the output node OUTPUT are directly connected.

[0048] Specifically, see Figure 2 In the related art, a capacitor C1 is set between the pull-up node and the output node. The embodiment of the present invention deletes the capacitor so that the pull-up node PU and the output node OUTPUT are directly connected, thereby saving the space occupied by the gate drive unit 10 in the layout. The gate drive circuit also includes an input signal line, which is used to provide an input voltage INPUT. The input circuit 11 of the gate drive unit 10 is connected to the input signal line, and the input voltage INPUT provided by the input signal line is written into the pull-up node PU, so that the potential of the pull-up node PU is pulled up, thereby controlling the output circuit 12 to output the gate drive signal. After deleting the capacitor, the output capacity of the gate drive unit 10 is improved, thereby increasing the low-temperature starting voltage of the gate drive unit 10.

[0049] In this way, the input voltage received by the gate driving unit 10 is written into the pull-up node PU through the input circuit 11, and the output circuit 12 outputs the gate driving signal according to the input voltage at the pull-up node PU to drive the corresponding pixel to work; the pull-up node PU and the output node OUTPUT of the gate driving unit 10 are directly connected, and the original capacitor connecting the pull-up node PU and the output node OUTPUT is deleted, thereby reducing the space occupied by the gate driving unit 10 in the layout, so that a narrow frame solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit 10 is increased, and the low-temperature starting voltage is improved.

[0050] In some embodiments, the input circuit 11 includes a first transistor M1 , a gate and a drain of the first transistor M1 are electrically connected to an input signal line for providing an input signal, and a source of the first transistor M1 is electrically connected to a pull-up node PU.

[0051] Specifically, when the input voltage of the input signal line is at a high level, the gate potential of the first transistor M1 is at a high level, and the first transistor M1 is turned on, so that the first transistor M1 can connect the input signal line and the pull-up node PU, thereby writing the input voltage INPUT into the pull-up node PU. Since the input voltage is at a high level at this time, the potential of the pull-up node PU is pulled up, so that the output circuit 12 can output a gate drive signal.

[0052] In this way, the first transistor M1 is turned on when the input voltage is at a high level, so that the input voltage can be written into the pull-up node PU, thereby raising the potential of the pull-up node PU, so that the output circuit 12 can output a gate driving signal.

[0053] In some embodiments, the gate driving unit 10 further includes a reset circuit 13, and the reset circuit 13 is used to receive a reset signal and reset the pull-up node PU.

[0054] Specifically, after the input voltage is at a high level, since the first transistor M1 is turned on, the input voltage is written into the pull-up node PU, so that the potential of the pull-up node PU is pulled up. In order to prevent the circuit from being damaged due to long-term voltage bias, the potential of the pull-up node PU needs to be pulled down to reset the pull-up node PU, so the reset circuit 13 is set to reset the pull-up node PU. The reset circuit 13 is electrically connected to the first voltage line and the pull-up node PU. The first voltage line is used to provide a low level. The reset circuit 13 can turn on the first voltage line and the pull-up node PU, so that the low level on the first voltage line is input to the pull-up node PU, thereby pulling down the potential of the pull-up node PU, and resetting the pull-up node PU.

[0055] In this way, the reset circuit 13 is provided to reset the pull-up node PU, so as to lower the potential of the pull-up node PU and prevent the components of the gate driving unit 10 from being damaged due to maintaining a high potential for a long time.

[0056] In some embodiments, the reset circuit 13 also includes a second transistor M2, the gate of the second transistor M2 is connected to the reset signal line RESET, the reset signal line RESET is used to provide a reset signal, the source of the second transistor M2 is connected to the first voltage line, the first voltage line is used to provide a low level, and the second transistor M2 is electrically connected to the pull-up node PU.

[0057] Specifically, the gate of the second transistor M2 is connected to the reset signal line RESET, and is turned on when the reset signal provided by the reset signal line RESET is at a high level, and is turned off when the reset signal is at a low level, so that the second transistor M2 can control the on and off of the first voltage line and the pull-up node PU, thereby achieving the resetting of the pull-up node PU.

[0058] In this way, the second transistor M2 can reset the pull-up node PU under the control of the reset signal.

[0059] In some embodiments, when a reset signal is received, the second transistor M2 is used to connect the first voltage line and the pull-up node PU to reset the pull-up node PU.

[0060] Specifically, when the reset signal is at a high level, the gate potential of the second transistor M2 is pulled high, and the second transistor M2 is turned on, thereby connecting the pull-up node PU connected to the drain and the first voltage line connected to the source, so as to provide the low level transmitted on the first voltage line to the pull-up node PU, thereby lowering the potential of the pull-up node PU to achieve resetting the pull-up node PU.

[0061] In this way, the second transistor M2 can reset the pull-up node PU under the control of the reset signal. When the reset signal is at a high level, the second transistor M2 is turned on so that the low level of the first voltage line can be input to the pull-up node PU, thereby lowering the potential of the pull-up node PU and resetting the pull-up node PU.

[0062] In some embodiments, the output circuit 12 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the pull-up node PU, a drain of the third transistor M3 is connected to a clock signal line, the clock signal line is used to provide a clock signal, and a source of the third transistor M3 is electrically connected to the output node OUTPUT of the gate drive unit 10 to output a gate drive signal through the output node OUTPUT.

[0063] Specifically, when the potential of the pull-up node PU is pulled high, the gate of the third transistor M3 is at a high potential, and the third transistor M3 is turned on, so that the clock signal transmitted by the clock signal line connected to the drain of the third transistor M3 can be output from the output node OUTPUT through the third transistor M3, and when the clock signal CLK is at a high level, the gate drive signal output by the output node OUTPUT is at a high level; when the clock signal CLK is at a low level, the gate drive signal output by the output node OUTPUT is at a low level.

[0064] In this way, the potential of the pull-up node PU can control the output of the third transistor M3, so that the third transistor M3 is turned on, thereby connecting the clock signal line and the output node OUTPUT, so that the gate driving signal can be output according to the clock signal.

[0065] In some embodiments, the gate driving unit 10 further includes a pull-down circuit 14, which is used to pull down the potential of the pull-up node PU. The pull-down circuit 14 connects a first voltage line and the pull-up node PU, and the first voltage line is used to provide a low level.

[0066] Specifically, the gate of the third transistor M3 is connected to the pull-up node PU. If the pull-up node PU continues to maintain a high potential, the third transistor M3 may be damaged due to long-term bias. Therefore, it is necessary to pull down the pull-up node PU so that the pull-up node PU can maintain a low potential when the third transistor M3 does not need to be turned on. The pull-down circuit 14 connects the first voltage line and the pull-up node PU, so that when the potential of the pull-up node PU needs to be pulled down, the first voltage line and the pull-up node PU are cut off, so that the potential of the pull-up node PU on the first voltage line is pulled down, thereby preventing the third transistor M3 from being damaged due to long-term bias.

[0067] In this way, the potential of the pull-up node PU is pulled down by the pull-down circuit 14, so that the potential of the pull-up node PU can be pulled down, thereby preventing the third transistor M3 from being damaged due to long-term bias.

[0068] In some embodiments, the pull-down circuit 14 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, the source of the fourth transistor M4 is electrically connected to the pull-down node PD, the drain of the fourth transistor M4 is connected to the second voltage line, and the second voltage line is used to input a high level; the gate of the fifth transistor M5 is electrically connected to the pull-up node PU, the drain of the fifth transistor M5 is electrically connected to the pull-down node PD, and the source of the fifth transistor M5 is connected to the first voltage line; the gate of the sixth transistor M6 is electrically connected to the pull-up node PU, and the source of the sixth transistor M6 is connected to the first voltage line; the gate and drain of the seventh transistor M7 are both connected to the second voltage line, and the source of the seventh transistor M7 is connected to the drain of the sixth transistor M6 and the gate of the fourth transistor M4.

[0069] Specifically, the drain of the fourth transistor M4 and the drain of the seventh transistor M7, the gate of the fourth transistor M4 is connected to the source of the seventh transistor M7, the source of the fourth transistor M4 is connected to the pull-down node PD, the gate of the seventh transistor M7 is connected to the second voltage line, the high level transmitted by the second voltage line makes the seventh transistor M7 turned on, the high level flows through the seventh transistor M7, the source of the seventh transistor M7 is a high potential, so that the gate of the fourth transistor M4 is a high potential, the fourth transistor M4 is turned on, the high level of the second voltage line flows through the fourth transistor M4 and is input to the pull-down node PD, thereby pulling up the potential of the pull-down node PD, and the high potential of the pull-down node PD can control the reset of the pull-up node PU, that is, control the reset of the potential of the pull-up node PU. The gate of the fifth transistor M5 and the gate of the sixth transistor M6 are connected to the pull-up node PU, the drain of the fifth transistor M5 is connected to the pull-down node PD, the drain of the sixth transistor M6 is connected to the source of the seventh transistor M7, the source of the fifth transistor M5 and the source of the sixth transistor M6 are both connected to the first voltage line, and when the pull-up node PU is at a high potential, the sixth transistor M6 is turned on so that the first voltage line and the source of the seventh transistor M7 are connected, and the fifth transistor M5 is turned on so that the first voltage line and the pull-down node PD are connected, so that the potential of the source of the seventh transistor M7 and the pull-down node PD are pulled down.

[0070] In this way, by lowering the potential of the pull-up node PU through the pull-down circuit 14 , the potential of the pull-up node PU can be continuously pulled down, so as to reduce the noise of the pull-up node PU and thus reduce the output ripple.

[0071] In some embodiments, the gate driving unit 10 further includes a noise reduction circuit 15, which is used to reduce noise on the gate driving unit 10. The noise reduction circuit 15 is connected to a first voltage line, which is used to provide a low level.

[0072] Specifically, the gate drive unit 10 is de-noised, that is, the gate drive unit 10 is reset, so that the gate drive unit 10 will not be in a high potential state for a long time. The noise reduction circuit 15 is connected to the first voltage line, and can transmit the low level of the first voltage line to the gate drive unit 10, thereby lowering the potential of the gate drive unit 10 to reset the gate drive unit 10, thereby achieving noise reduction of the gate drive unit 10 and avoiding the adverse effects caused by excessive noise.

[0073] In this way, the gate driving unit 10 and the first voltage line are connected through the noise reduction circuit 15, so that the first voltage line can pull down the potential of the gate driving unit 10 to achieve resetting of the gate driving unit 10, thereby performing noise reduction.

[0074] In some embodiments, the noise reduction circuit 15 includes an eighth transistor M8, which is used to perform noise reduction on the pull-up node PU. The gate of the eighth transistor M8 is connected to the start control line STV0, the drain of the eighth transistor M8 is connected to the pull-up node PU, and the source of the eighth transistor M8 is connected to the first voltage line. The start control line STV0 is only used to control the noise reduction of the pull-up node PU.

[0075] Specifically, see Figure 3 , the signal of the start control line STV0 is used to control the reset of the gate drive unit to start a new round of work. The gate of the eighth transistor M8 is connected to the start control line STV0, the drain is connected to the pull-up node PU, and the source is connected to the first voltage line. When the start control line STV0 outputs a high level, the eighth transistor M8 is turned on, thereby connecting the first voltage line and the pull-up node PU, so that the low level transmitted by the first voltage line can be input to the pull-up node PU, thereby pulling down the potential of the pull-up node PU to achieve the reset of the pull-up node PU, thereby achieving the noise reduction of the pull-up node PU. In the related art, the start control line is also used to connect the gate of a transistor, the drain of the transistor is connected to the output node, and the source of the transistor is connected to the first voltage line. The start control line controls the connection between the output node and the first voltage line by controlling the conduction of the transistor to control the noise reduction of the output node. In the embodiment of the present invention, the transistor is deleted so that the start control line STV0 is only used to control the noise reduction of the pull-up node PU, reducing the space occupied by the gate drive unit 10 in the layout, so as to better meet the requirements of the narrow frame. Please refer to Figure 4 and Figure 5 ,in, Figure 4 and Figure 5 They respectively include two gate driving units 10. In the gate driving unit 10 of the embodiment of the present invention, the capacitor and transistor in the 11T1C structure of the related art are deleted to obtain a 10T0C structure. Compared with the 11T1C structure, the 10T0C saves 20-30um of space in the layout; and when the 10T0C structure is operated under high temperature conditions, there is no screen flickering problem within 500 hours, and the noise tolerance capability is equivalent to that of 11T1C.

[0076] In this way, the first voltage line and the pull-up node PU are connected through the eighth transistor M8 on the control line of the starting control line STV0, so that the low level transmitted by the first voltage line can lower the potential of the pull-up node PU, thereby resetting the pull-up node PU and achieving noise reduction for the pull-up node PU.

[0077] In some embodiments, the noise reduction circuit 15 includes a ninth transistor M9, which is used to reduce the noise of the pull-up node PU, the gate of the ninth transistor M9 is connected to the pull-down node PD, the drain of the ninth transistor M9 is connected to the pull-up node PU, the source of the ninth transistor M9 is connected to the first voltage line, and the ninth transistor M9 is used to reduce the noise of the pull-up node PU according to the potential of the pull-down node PD.

[0078] Specifically, when the potential of the pull-down node PD is high, the potential of the gate of the ninth transistor M9 is pulled up, and the ninth transistor M9 is turned on, thereby connecting the pull-up node PU and the first voltage line, so that the low level transmitted by the first voltage line can be input to the pull-up node PU, thereby lowering the potential of the pull-up node PU, so as to achieve the reset of the pull-up node PU, thereby achieving the noise reduction of the pull-up node PU. The noise reduction of the pull-up node PU by the eighth transistor M8 is under the control of the starting control line STV0, and the starting control line STV0 needs to output a high level. The pull-up node PU can be noise-reduced when noise reduction is needed under the control of the starting control line STV0; the noise reduction of the pull-up node PU by the ninth transistor M9 is under the control of the potential of the pull-down node PD, and no additional signal control is required. Noise reduction can be achieved according to the node potential control of the gate drive circuit itself.

[0079] In this way, the ninth transistor M9 is turned on under the control of the pull-down node PD, thereby connecting the pull-up node PU and the first voltage line, so that the low level transmitted by the first voltage line can lower the potential of the pull-up node PU to achieve noise reduction for the pull-up node PU.

[0080] In some embodiments, the noise reduction circuit 15 includes a tenth transistor M10, which is used to reduce the noise of the output node OUTPUT of the gate driving unit 10, the gate of the tenth transistor M10 is electrically connected to the pull-down node PD, the drain of the tenth transistor M10 is electrically connected to the output node OUTPUT, and the source of the tenth transistor M10 is connected to the first voltage line.

[0081] Specifically, the gate of the tenth transistor M10 is connected to the pull-down node PD. When the pull-down node PD is at a low potential, the tenth transistor M10 is turned on, connecting the first voltage line connected to the source of the tenth transistor M10 and the output node OUTPUT connected to the drain, so that the low level transmitted by the first voltage line can be input to the output node OUTPUT, and the potential of the output node OUTPUT is pulled down to achieve resetting of the output node OUTPUT, thereby achieving noise reduction of the output node OUTPUT.

[0082] In this way, the tenth transistor M10 is turned on under the control of the pull-down node PD, so that the connection between the first voltage line and the output node OUTPUT is connected, the low level transmitted by the first voltage line is input to the output node OUTPUT, and the potential of the output node OUTPUT is pulled down, thereby achieving noise reduction of the output node OUTPUT.

[0083] See also Figure 6 An embodiment of the present invention provides an array substrate 100, which includes a gate driving circuit and a via 20 of any of the above embodiments. The gate driving circuit also includes a signal line, and the gate driving unit 10 and the signal line are electrically connected through the via 20.

[0084] Specifically, the via 20 includes a first via and a second via, the first via is used to connect the signal line, the second via is used to connect the gate drive unit 10, the first via and the second via are connected to each other and arranged in pairs, thereby realizing the connection between the signal line and the gate drive unit 10, so that the signal line can control the gate drive unit 10. The signal line includes an input signal line, a first voltage line, a second voltage line, a reset signal line RESET, a start control line STV0, a ​​clock signal line, and the like.

[0085] In this way, the input voltage received by the gate driving unit 10 of the array substrate 100 is written into the pull-up node PU through the input circuit 11, and the output circuit 12 outputs the gate driving signal according to the input voltage at the pull-up node PU to drive the corresponding pixel to work; the pull-up node PU and the output node OUTPUT of the gate driving unit 10 are directly connected, and the original capacitor connecting the pull-up node PU and the output node OUTPUT is deleted, thereby reducing the space occupied by the gate driving unit 10 in the layout, so that a narrow frame solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit 10 is increased, and the low-temperature starting voltage is improved.

[0086] See also Figure 6 In some embodiments, the via 20 includes a plurality of high potential vias 21, the high potential vias 21 are arranged in a single pair, and the high potential vias 21 maintain a high potential within a set time.

[0087] Specifically, the high potential via 21 includes a first high potential via, a second high potential via and a third high potential via, wherein the first high potential via is used to connect the fourth transistor M4, the second high potential via is used to connect the seventh transistor M7, and the third high potential via is used to connect the pull-down node PD. Since the gate and drain of the seventh transistor M7 are connected to the second voltage line transmitting a high level, the gate of the seventh transistor M7 is at a high potential, so that the seventh transistor M7 is turned on, and the high level flows through the seventh transistor M7, and the source potential of the seventh transistor M7 is high; the gate of the fourth transistor M4 is connected to the source of the seventh transistor M7, the drain is connected to the second voltage line, and the source is connected to the pull-down node PD. When the source potential of the seventh transistor M7 is high, the fourth transistor M4 is turned on, so that the high level of the second voltage line flows through the fourth transistor M4 and is input to the pull-down node PD connected to the source of the fourth transistor M4. Therefore, the fourth transistor M4, the seventh transistor M7 and the pull-down node PD maintain a high potential for a long time during the operation of the gate driving unit 10, and the first high potential via hole, the second high potential via hole and the third high potential via hole connecting the fourth transistor M4, the seventh transistor M7 and the pull-down node PD maintain a high potential within the set time. Please refer to Figure 7 In the related art, the vias on the board diagram are all set in pairs, that is, there are four vias connecting the same data line and the same component, two of which connect the data line and two connect the components. The dotted circle is a high-potential via. Since high-potential vias are less susceptible to electrochemical corrosion, such as Figure 6 As shown in the dotted circle, the embodiment of the present invention sets the high-potential via 21 as a single pair, that is, there are two vias 20 connecting the same data line and the same component, one via 20 connects the data line, and one via 20 connects the component, thereby saving about 10um of space on the layout.

[0088] In this way, by setting the vias 20 that maintain a high potential within a set time to be a single pair, the space occupied on the layout is saved to better meet the requirements of a narrow frame.

[0089] An embodiment of the present invention provides a display panel, which includes an array substrate 100 and pixels according to any one of the above embodiments. The gate driving unit 10 of the array substrate 100 is used to drive the pixels.

[0090] In this way, the input voltage received by the gate driving unit 10 of the display panel is written into the pull-up node PU through the input circuit 11, and the output circuit 12 outputs the gate driving signal according to the input voltage at the pull-up node PU to drive the corresponding pixel to work; the pull-up node PU and the output node OUTPUT of the gate driving unit 10 are directly connected, and the original capacitor connecting the pull-up node PU and the output node OUTPUT is deleted, thereby reducing the space occupied by the gate driving unit 10 in the layout, so that a narrow border solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit 10 is increased, and the low-temperature starting voltage is improved.

[0091] An embodiment of the present invention provides a display device, which includes a housing and the display panel of the above embodiment, wherein the display panel is disposed in the housing.

[0092] In this way, the input voltage received by the gate driving unit 10 of the display panel is written into the pull-up node PU through the input circuit 11, and the output circuit 12 outputs the gate driving signal according to the input voltage at the pull-up node PU to drive the corresponding pixel to work; the pull-up node PU and the output node OUTPUT of the gate driving unit 10 are directly connected, and the original capacitor connecting the pull-up node PU and the output node OUTPUT is deleted, thereby reducing the space occupied by the gate driving unit 10 in the layout, so that a narrow border solution can be achieved while meeting the safety distance; at the same time, after deleting the capacitor, the output capacity of the gate driving unit 10 is increased, and the low-temperature starting voltage is improved.

[0093] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0094] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0095] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0096] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present invention belong.

[0097] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of gate driving units, and the gate driving units include: An input circuit, the input circuit is used to receive an input voltage and write the input voltage into a pull-up node, the input circuit is electrically connected to the pull-up node; an output circuit, the output circuit being used to output a gate drive signal through an output node of the gate drive unit, the gate drive signal being determined according to the input voltage written into the pull-up node, the output circuit being electrically connected to the pull-up node and the output node; The pull-up node and the output node are directly connected.

2. The gate drive circuit according to claim 1, characterized in that: The input circuit comprises: A first transistor, wherein a gate and a drain of the first transistor are electrically connected to an input signal line, the input signal line is used to provide an input signal, and a source of the first transistor is electrically connected to the pull-up node.

3. The gate drive circuit according to claim 1, characterized in that: The gate driving unit further includes: A reset circuit is used to receive a reset signal and reset the pull-up node.

4. The gate driving circuit according to claim 3, characterized in that: The reset circuit also includes: A second transistor, wherein the gate of the second transistor is connected to a reset signal line, the reset signal line is used to provide a reset signal, the source of the second transistor is connected to a first voltage line, the first voltage line is used to provide a low level, and the second transistor is electrically connected to the pull-up node.

5. The gate driving circuit according to claim 4, characterized in that: When receiving a reset signal, the second transistor is used to connect the first voltage line and the pull-up node to reset the pull-up node.

6. The gate driving circuit according to claim 1, characterized in that: The output circuit comprises: A third transistor, wherein the gate of the third transistor is electrically connected to the pull-up node, the drain of the third transistor is connected to a clock signal line, the clock signal line is used to provide a clock signal, and the source of the third transistor is electrically connected to the output node of the gate driving unit to output the gate driving signal through the output node.

7. The gate driving circuit according to claim 1, characterized in that: The gate driving unit further includes: A pull-down circuit is used to pull down the potential of the pull-up node, the pull-down circuit is connected to a first voltage line and the pull-up node, and the first voltage line is used to provide a low level.

8. The gate driving circuit according to claim 7, characterized in that: The pull-down circuit comprises: a fourth transistor, wherein a source of the fourth transistor is electrically connected to the pull-down node, a drain of the fourth transistor is connected to a second voltage line, and the second voltage line is used to input a high level; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the pull-up node, a drain of the fifth transistor is electrically connected to the pull-down node, and a source of the fifth transistor is connected to the first voltage line; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the pull-up node, and a source of the sixth transistor is connected to the first voltage line; A seventh transistor, wherein the gate and the drain of the seventh transistor are both connected to the second voltage line, and the source of the seventh transistor is connected to the drain of the sixth transistor and the gate of the fourth transistor.

9. The gate driving circuit according to claim 1, characterized in that: The gate driving unit further includes: A noise reduction circuit is used to reduce noise on a gate driving unit, and the noise reduction circuit is connected to a first voltage line, and the first voltage line is used to provide a low level.

10. The gate driving circuit according to claim 9, characterized in that: The noise reduction circuit comprises: An eighth transistor, the eighth transistor is used to reduce the noise of the pull-up node, the gate of the eighth transistor is connected to the start control line, the drain of the eighth transistor is connected to the pull-up node, the source of the eighth transistor is connected to the first voltage line, and the start control line is only used to control the noise reduction of the pull-up node.

11. The gate driving circuit according to claim 9, characterized in that: The noise reduction circuit comprises: A ninth transistor, the ninth transistor is used to reduce the noise of the pull-up node, the gate of the ninth transistor is connected to the pull-down node, the drain of the ninth transistor is connected to the pull-up node, the source of the ninth transistor is connected to the first voltage line, and the ninth transistor is used to reduce the noise of the pull-up node according to the potential of the pull-down node.

12. The gate driving circuit according to claim 9, characterized in that: The noise reduction circuit comprises: A tenth transistor, the tenth transistor is used to reduce noise on the output node of the gate driving unit, the gate of the tenth transistor is electrically connected to the pull-down node, the drain of the tenth transistor is electrically connected to the output node, and the source of the tenth transistor is connected to the first voltage line.

13. An array substrate, characterized in that: The array substrate comprises the gate driving circuit and the via hole according to any one of claims 1 to 12, the gate driving circuit further comprises a signal line, and the gate driving unit and the signal line are electrically connected through the via hole.

14. The array substrate according to claim 13, characterized in that: The vias include a plurality of high potential vias, the high potential vias are arranged in a single pair, and the high potential vias maintain a high potential within a set time.

15. A display panel, characterized in that: The display panel comprises the array substrate and pixels according to claim 13 or 14, and the gate driving unit of the array substrate is used to drive the pixels.

16. A display device, characterized in that: The display device includes a housing and the display panel according to claim 15, wherein the display panel is disposed in the housing.

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