Display panel and display device

Abstract

According to the display panel and the display device, a display area and a lower frame area in the display panel are arranged in the first direction, and the lower frame area comprises a plurality of pins; the number of pixels arranged in the first direction in the display panel is N1, the number of pixels arranged in the second direction is N2, N1 is larger than N2, and the first direction intersects with the second direction. The display panel is provided with scanning lines which extend along a first direction and are electrically connected with a plurality of pixels arranged along the first direction. According to the embodiment of the invention, the scanning lines can drive the pixels column by column, so that more time for data voltage writing is reserved for the pixels in each column under the same refresh frequency, and preparation is made for a display technology with higher refresh frequency of the display panel; and the time for each pixel in the display panel to receive the data voltage can be improved under the same refresh frequency, so that the accuracy of the data voltage received by the pixel is improved, the accuracy of the luminance of the pixel is improved, and the display effect of the display panel in high-frequency work is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes multiple pixels. When the display panel operates at high frequency, it is easy to face the problem of insufficient pixel charging time, which can easily cause problems such as inaccurate data voltage received by the pixels, which is not conducive to the display panel adapting to the needs of high-frequency operation and improving the display effect of the display panel. Summary of the invention

[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising: a display area and a lower frame area, wherein the display area and the lower frame area are arranged along a first direction, and the lower frame area comprises a plurality of pins; A plurality of pixels, the number of pixels arranged along the first direction is N1, the number of pixels arranged along the second direction is N2, N1>N2, the first direction intersects the second direction; a plurality of scan lines arranged along the second direction, the scan lines extend along the first direction and are electrically connected to the plurality of pixels arranged along the first direction.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0006] In an embodiment of the present application, the scan lines in the display panel are arranged to extend in the first direction and to be arranged in the second direction, which is beneficial for the scan lines to drive the pixels column by column, thereby reserving more time for writing data voltages for the pixels in each column at the same refresh frequency, which is beneficial for preparing the display panel for display technology with a higher refresh frequency, and is beneficial for increasing the time for each pixel in the display panel to receive the data voltage at the same refresh frequency, thereby improving the accuracy of the data voltage received by the pixel, improving the accuracy of the luminous brightness of the pixel, and improving the display effect of the display panel under high-frequency operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0008] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application; Figure 2A schematic plan view of another display panel provided in an embodiment of the present application; Figure 3 A schematic plan view of another display panel provided in an embodiment of the present application; Figure 4 A method provided in the embodiment of the present application Figure 2 Schematic diagram of the cross section along the A-A' direction; Figure 5 A schematic plan view of another display panel provided in an embodiment of the present application; Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application; Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application; Figure 8 A schematic plan view of another display panel provided in an embodiment of the present application; Fig. 9 A method provided in the embodiment of the present application Figure 6 Schematic diagram of the cross section along the B-B' direction; Fig.10 A schematic plan view of another display panel provided in an embodiment of the present application; Fig.11 A schematic plan view of another display panel provided in an embodiment of the present application; Fig.12 A schematic plan view of another display panel provided in an embodiment of the present application; Fig.13 A schematic plan view of another display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0009] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0010] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0011] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0012] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0013] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0014] It should be understood that although the terms first, second, etc. may be used to describe directions, connecting lines, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish directions, connecting lines, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first direction may also be referred to as the second direction, and similarly, the second direction may also be referred to as the first direction. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0015] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0016] The embodiment of the present application provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a display area A10 and a lower frame area A20, the display area A10 and the lower frame area A20 are arranged along a first direction X1, and the lower frame area A20 includes a plurality of pins Pin. Optionally, the plurality of pins in the lower frame area A20 of the display panel 100 can be used to transmit data voltages, panel control signals, etc., and at least part of the plurality of pins in the lower frame area A20 is electrically connected to the flexible circuit board. In the embodiment of the present application, the direction in which the lower frame area A20 including the pins in the display panel 100 and the display area A10 are arranged along the first direction X1 is taken as an example for description.

[0017] The display panel 100 also includes a plurality of pixels 10, the number of pixels 10 arranged along the first direction X1 is N1, the number of pixels 20 arranged along the second direction X2 is N2, N1>N2, and the first direction X1 intersects with the second direction X2. In combination with the above, it can be seen that the display area A10 and the lower frame area A20 of the display panel 100 are arranged along the column direction, and accordingly, the second direction X2 is the row direction. Then, the number of pixels 10 in the display panel 100 in the first direction X1 is greater than the number of pixels 10 arranged in the second direction X2, and the shape of the display panel 100 provided in the embodiment of the present application is a panel whose length in the column direction is greater than the length in the row direction. For example, the display panel 100 included in a display device such as a mobile phone, a vertical screen computer display screen, etc.

[0018] In the related art, when the display panel 100 is working, the pixels 10 are usually scanned row by row, and the pixels 10 turned on by the scanning drive begin to receive the data voltage Vdata, and the same data line is electrically connected to the multiple pixels 10 arranged along the first direction X1. Therefore, the same data line also writes the data voltage Vdata to the multiple pixels 10 arranged in the first direction X1 one by one. It can be understood that in the process of turning on the pixels 10 row by row, the time left for each row of pixels 10 to write the data voltage Vdata is the time left for turning on a row of pixels 10 under a frame refresh frequency. For example, when the refresh frequency of a frame in the display panel 100 is 120Hz, taking the number of pixel rows in the display panel 100 as 2800 rows, the time left for each row of pixels 10 to write data is about 2.9μs, which is close to the time limit for charging the pixels 10. However, in order to further increase the refresh frequency of the display panel 100, it is also faced with the challenge of insufficient charging time for the pixels 10, especially under high-frequency driving, there is a serious problem of image quality uniformity.

[0019] The embodiment of the present application is to increase the charging time of the display panel 100 for the pixel 10 under high frequency, to ensure that the pixel 10 can also receive accurate data voltage under high frequency driving of the display panel 100, thereby generating accurate luminous brightness, and improving the display effect of the display panel 100 under high frequency operation, and the technical solution of the present application is proposed.

[0020] In the embodiment of the present application, it is proposed that the display panel 100 further includes a plurality of scan lines 20 arranged along the second direction X2. Optionally, the scan line 20 is used to drive the pixel 10 to turn on and receive the data voltage Vdata. The scan line 20 extends along the first direction X1 and is electrically connected to the plurality of pixels 10 arranged along the first direction X1. The scan line 20 extends in the column direction, and the plurality of scan lines 20 arranged in the second direction X2 sequentially transmit effective signals to drive the pixel 10 to turn on and receive the data voltage Vdata. At this time, the plurality of pixels 10 in the display panel 100 are turned on by column, and the pixels 10 are scanned column by column. In combination with the above content, it can be seen that the number of pixels 10 arranged along the first direction X1 of the display panel 100 provided in the embodiment of the present application is greater than the number of pixels 10 arranged in the second direction X2. When the scan line 20 scans the pixel 10, the number of times the pixel column is scanned is less than the number of times the pixel row is scanned, which is conducive to increasing the time reserved for data writing to each pixel 10 at the same refresh frequency. For example, when the refresh frequency of a frame in the display panel 100 is 120 Hz, taking the number of pixel rows in the display panel 100 as 2800 rows and the number of pixel column data as 1260 columns, the time reserved for writing data to the pixels 10 in each column increases to about 6.2 μs, and it can be clearly seen that the time reserved for charging the pixels 10 is relatively sufficient. Then, when the refresh frequency of the display panel 100 is increased, for example, when the refresh frequency of the same display panel 100 is increased to 165 Hz, the time reserved for writing data to the pixels 10 in each column is about 4.52 μs, which is still a relatively ideal charging time.

[0021] In the embodiment of the present application, the scan lines 20 in the display panel 100 are arranged to extend in the first direction X1 and arranged in the second direction X2, which is beneficial for the scan lines 20 to drive the pixels 10 column by column, thereby reserving more time for writing data voltages for the pixels 10 in each column at the same refresh frequency, which is beneficial for preparing the display panel 100 for display technology with a higher refresh frequency, and is beneficial for increasing the time for each pixel 10 in the display panel 100 to receive the data voltage Vdata at the same refresh frequency, thereby improving the accuracy of the data voltage Vdata received by the pixel 10, improving the accuracy of the luminous brightness of the pixel 10, and improving the display effect of the display panel 100 in high-frequency operation.

[0022] Figure 2 A schematic plan view of another display panel provided in an embodiment of the present application.

[0023] In one embodiment of the present application, Figure 2As shown, the display panel 100 further includes a frame area AA0, the frame area AA0 includes a lower frame area A20 and a side frame area A30, and the frame area AA0 surrounds the display area A10. The frame area A40 of the display panel 100 can be used to protect the display area A10 and can be used to prepare a variety of circuits for driving the display panel 100. The side frame area A30 includes a first sub-frame area A31, and the first sub-frame area A31 is located on opposite sides of the display area A10 in the second direction X2.

[0024] The display panel 100 further includes a plurality of cascaded shift register circuits 30, at least part of which is located in the first sub-frame area A31. Since the length of the display panel 100 in the first direction X1 is greater than the length in the second direction X2, the length of the first sub-frame area A31 is greater than the length of the lower frame area A20, and the preparation of the plurality of cascaded shift register circuits 30 in the first sub-frame area A31 is conducive to providing a relatively sufficient space for the preparation of the shift register circuits 30, and avoiding circuit crowding between the shift register circuits 30.

[0025] The shift register circuit 30 includes an output terminal 301, and the display area A10 also includes a plurality of first connection lines SL1, and at least part of the scan lines 20 are electrically connected to the output terminal 301 of the shift register circuit 30 through the first connection lines SL1. The shift register circuit 30 proposed in the embodiment of the present application is described by taking the enable signal that can generate the control pixel 10 to start receiving the data voltage Vdata as an example. Of course, in some other embodiments, the shift register circuit 30 can be used to generate other control signals, and the scan line 20 can also be used to transmit other control signals. The shift register circuit 30 is electrically connected to the scan line 20. Since the display panel 100 in the embodiment of the present application is refreshed column by column, and the number of pixel columns is less than the number of pixel rows, it is beneficial to reduce the number of shift register circuits 30 prepared in the display panel 100.

[0026] In the embodiment of the present application, the scanning lines 20 in the display panel 100 are arranged to scan column by column, which is beneficial to reducing the number of shift register circuits 30 prepared, reducing the circuit preparation cost of the display panel 100, and improving the preparation efficiency. Figure 2 As shown, the shift register circuit 30 and the scan line 20 are electrically connected through the first connecting line SL1, which is beneficial for the shift register circuit 30 and the scan line 20 to be wound in the display area A10 when they are electrically connected, thereby avoiding the problem of increasing the winding distance between the shift register circuit 30 and the scan line 20 when they are wound in the border area AA0, and is also beneficial for reducing the routing congestion in the border area AA0.

[0027] Figure 3 A schematic plan view of another display panel provided in an embodiment of the present application.

[0028] In one embodiment of the present application, Figure 3 As shown, the frame area AA0 further includes an upper frame area A32 , and the upper frame area A32 and the lower frame area A20 are respectively located at two opposite sides of the display panel 100 in the first direction X1 .

[0029] In the embodiment of the present application, at least part of the shift register circuit 30 is arranged in the upper frame area A32, which is conducive to reducing the space pressure of preparing the shift register circuit 30 in the first sub-frame area A31. In addition, the shift register circuit 30 is electrically connected to the scan line 20, and the scan line 20 extends along the first direction X1. When the shift register circuit 30 is arranged in the upper frame area A32, it is conducive to aligning at least part of the shift register circuit 30 with the pixels 10 of the corresponding column in the first direction X1, so that the output end 301 of the shift register circuit 30 can be directly electrically connected to the scan line 20, thereby reducing the number of prepared first connection lines SL1. Alternatively, the distance between the shift register circuit 30 prepared in the upper frame area A32 and the corresponding pixel column is also closer, which is conducive to reducing the winding distance of part of the first connection line SL1.

[0030] When at least part of the shift register circuit 30 is located in the upper frame area A32, as shown in FIG. Figure 3 As shown, it is beneficial to prepare the shift register circuit 30 distributed in the first sub-frame area A31 and the upper frame area A32, and it is possible that the first sub-frame area A31 and the upper frame area A32 are not completely occupied, which is beneficial to prepare the shift register circuit 30 in a manner of semi-enclosed display area A10, and to reserve space in the first sub-frame area A31 and the upper frame area A32 to prepare global wiring such as power lines, which is beneficial to make the wiring distribution in the display panel 100 more uniform, and avoid signal deviation problems caused by wiring impedance due to wiring distribution at different positions in the display panel 100.

[0031] Figure 4 A method provided in the embodiment of the present application Figure 2 Schematic diagram of the cross section along the A-A' direction.

[0032] In one embodiment of the present application, Figure 2 , Figure 4As shown, the first connection line SL1 and the scan line 20 are located in different film layers. In the embodiment of the present application, the scan line 20 is located in the display area A10 and extends along the first direction X1 to be electrically connected to a plurality of pixels 10, and at least part of the shift register circuit 30 is located in the first sub-frame area A31, so that the position of the register circuit 30 is arranged in the second direction X2, so that at least part of the first connection line SL1 in the display area A10 extends along the second direction X2 to the position of the scan line 20. Therefore, setting the scan line 20 and the first connection line SL1 in different film layers is conducive to avoiding the situation where the two cross in the same layer, thereby ensuring the accuracy of the control signal transmitted by the scan line 20. Optionally, the first connection line SL1 and the scan line 20 are electrically connected through a perforation.

[0033] Figure 5 A schematic plan view of another display panel provided in an embodiment of the present application.

[0034] In one embodiment of the present application, Figure 5 As shown, the display panel 100 further includes a first power signal line SL2 and a second power signal line SL3, and at least part of the first power signal line SL2 and / or at least part of the second power signal line SL3 are located in the frame area AA0. Optionally, the first power signal line SL2 is used to transmit a positive voltage PVDD to the display panel 100, and the second power signal line SL3 is used to provide a negative voltage PVEE to the display panel 100. Alternatively, optionally, the first power voltage signal line SL2 and the second power voltage signal line SL3 are used to transmit global signals such as a positive voltage PVDD, a negative voltage PVEE, a reset voltage Vref, and a compensation data voltage DVH.

[0035] In the embodiment of the present application, at least part of the shift register circuit 30 is arranged in the first area A311 in the first sub-frame area A31, at least part of the first power signal line SL2 and / or at least part of the second power signal line SL3 is located in the second area A312 in the first sub-frame area A31, and the first area A311 and the second area A312 are arranged along the first direction X1, which is conducive to making at least one of the first power voltage signal line SL2 and the second power voltage signal line SL3 distributed in the first sub-frame area A31 that is vacated by reducing the number of shift register circuits 30, and is conducive to improving the distribution position of the first power signal line SL2 and the second power signal line SL3 in the display panel 100, thereby facilitating the improvement of the distribution uniformity of the signal line in the display panel 100, improving the voltage drop problem of the signal line in the display panel 100, and improving the display uniformity of the display panel 100. It should be noted that the first power signal line SL2 and the second power signal line SL3 proposed in the embodiment of the present application are not only distributed in the first sub-frame area A31, but are also prepared in positions other than the first sub-frame area A31.

[0036] Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application.

[0037] In one embodiment of the present application, Figure 6 As shown, the pixel 10 includes a sub-pixel 101, and the display panel 100 further includes a plurality of data lines 40, which extend along the second direction X2 and are electrically connected to the plurality of sub-pixels 101 arranged along the second direction X2. Optionally, the plurality of sub-pixels 101 arranged along the first direction X1 have different colors. The plurality of sub-pixels 101 distributed along the second direction X2 are electrically connected to the same data line 40, and the data line 40 sequentially inputs data voltages Vdata to the plurality of sub-pixels 101 distributed along the second direction X2.

[0038] In the embodiment of the present application, a plurality of data lines 40 are arranged to extend along the second direction X2 and are electrically connected to a plurality of sub-pixels 101 arranged along the second direction X2. This is beneficial for the data lines 40 to be prepared so as to transmit data voltages Vdata to the sub-pixels 101 that are turned on column by column, and is beneficial for realizing the technical solution of turning on the pixels 10 column by column in the embodiment of the present application, thereby increasing the data writing time for each pixel 10.

[0039] In one embodiment of the present application, continue to refer to Figure 6 As shown, the display area A10 includes a plurality of second connection lines SL4, the lower frame area A20 includes a plurality of data leads P1, and at least some of the data lines 40 are electrically connected to the data leads P1 of the lower frame area A20 through the second connection lines SL4. Optionally, the data leads P1 can be used to provide different data voltages Vdata to the data lines 40.

[0040] It can be seen from the above that the number of pixels 10 in the first direction X1 proposed in the embodiment of the present application is greater than the number in the second direction X2. Accordingly, the number of sub-pixels 101 in the display panel 100 arranged along the first direction X1 is greater than the number arranged along the second direction X2. Taking the example of each row of sub-pixels 101 being electrically connected to one data line 40, the number of data lines 40 that need to be electrically connected to the display panel 100 is greatly increased, and thus the number of data leads P1 required for the increase in the number of data lines 40 also increases.

[0041] In the embodiment of the present application, the data lead P1 is electrically connected to the data line 40 through the second connection line SL4 located in the display area A10. Figure 6As shown, one end of the second connection line SL4 is electrically connected to the data lead P1, and the other end is electrically connected to the data line 40 in the display area A10. This is conducive to reducing the position correspondence condition between the data lead P1 and the data line 40, and can also achieve a good electrical connection between the data lead P1 and the data line 40. It is also conducive to reducing the routing preparation pressure in the lower frame area A20 by winding the second connection line SL4 in the display area A10, which is conducive to achieving the condition of increasing the number of data lines 40 in the technical solution of the present application, and better completing the technical solution of driving pixels 10 by columns in the embodiment of the present application.

[0042] Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Figure 8 A schematic plan view of another display panel provided in an embodiment of the present application.

[0043] In one embodiment of the present application, Figure 7-Figure 8 As shown, the display panel 100 further includes a side frame area A30 , and the side frame area A30 further includes a first sub-frame area A31 , and the first sub-frame area A31 is located at two opposite sides of the display area A10 in the second direction X2 .

[0044] In the embodiment of the present application, optionally, Figure 7 As shown, the first sub-frame area A31 includes a plurality of data leads P1 arranged along the first direction X1, and the data line 40 is electrically connected to the data lead P1. Alternatively, as Figure 8 As shown, the data lead P1 is provided in both the first sub-frame area A31 and the lower frame area A20. Optionally, the data lead P1 is prepared in a portion of the first sub-frame area A31 where the shift register circuit 30 is not prepared in the first sub-frame area A31. In the embodiment of the present application, the data lead P1 is also provided in the first sub-frame area A31, which is beneficial to reducing the wiring pressure in the lower frame area A20. Moreover, the first sub-frame area A31 is adjacent to the display area A10 in the second direction X2, and the data line 40 extends along the second direction X2, then at least part of the data lead P1 can be prepared to correspond to the data line 40 in the second direction X2, so that the data line 40 and the data lead P1 do not need to be directly electrically connected through the second connection line SL4, which is beneficial to reducing the number of the second connection lines SL4 prepared in the display area A10, thereby providing more available space for the display panel 100.

[0045] In one embodiment of the present application, continue to refer to Figure 6-Figure 8As shown, a first gap M1 is included between two adjacent pixels 10, and at least a portion of the second connection line SL4 passes through the first gap M1 to be electrically connected to the data line 40, which is conducive to electrically connecting the data lead P1 to the data line 40 through the second connection line SL4, and the second connection line SL4 can pass through multiple first gaps M1 when winding in the display area A10, which is conducive to improving the flexibility of the process of preparing the second connection line SL4 and preparing the routing more reasonably.

[0046] In one embodiment of the present application, continue to refer to Figure 6-Figure 8 As shown, N3 second connection lines SL4 are arranged to pass through the first gap M1, and N3≥1.

[0047] In the embodiment of the present application, multiple second connection lines SL4 are allowed to pass through the same first gap M1. Taking the example that the number of second connection lines SL4 is equal to the number of data lines 40, it is beneficial to better utilize the wiring space in the display panel 100 when the number of data lines 40 increases, and complete the electrical connection between the data lines 40 and the data leads P1.

[0048] Fig. 9 A method provided in the embodiment of the present application Figure 6 Schematic diagram of the cross section along the B-B' direction.

[0049] In one embodiment of the present application, Figure 6 , Fig. 9 As shown, the second connection line SL4 and the data line 40 are located in different film layers. In combination with the above content, it can be seen that part of the data lead P1 is located in the lower frame area A20, so when the second connection line SL4 is wound to electrically connect the data line 40, the second connection line SL4 may have a part of the line extending along the first direction X1, and the data line 40 extends in the second direction X2. Therefore, setting the second connection line SL4 and the data line 40 in different film layers is conducive to avoiding the second connection line SL4 and the data line 40 from crossing in the same layer, thereby ensuring that the data line 40 transmits an accurate data voltage Vdata. Optionally, the second connection line SL4 and the data line 40 are electrically connected by punching.

[0050] In some other embodiments, most of the second connection line SL4 and the data line 40 may be located in the same film layer, and the second connection line SL4 and the data line 40 may be arranged to cross the film layer at the intersection position to avoid the second connection line SL4 and the data line 40 crossing in the same film layer.

[0051] Fig.10 A schematic plan view of another display panel provided in an embodiment of the present application.

[0052] In one embodiment of the present application, Fig.10As shown, the display panel 100 also includes a plurality of multi-way selection circuits 50, and the multi-way selection circuit 50 includes switches 501. The input ends of the plurality of switches 501 of the multi-way selection circuit 50 are electrically connected to the same data lead P1, and the output ends of the plurality of switches 501 of the multi-way selection circuit 50 are electrically connected to different data lines 40. The control ends of the switches 501 in the same multi-way selection circuit 50 are electrically connected to different control signal lines, so that the plurality of switches 501 are turned on in time division. Optionally, the switches 501 of the multi-way selection circuit 50 provided in the embodiment of the present application are switch transistors. In combination with the technical solution of driving the plurality of pixels 10 by column provided in the embodiment of the present application, the plurality of data lines 40 electrically connected to the plurality of switches 501 of the multi-way selection circuit 50 provided in the embodiment of the present application are electrically connected to the sub-pixels 101 of different rows, respectively. When a certain column of sub-pixels 101 in the display panel 100 starts to receive the data voltage Vdata, the data lead P1 electrically connected to the multi-way selection circuit 50 sequentially transmits the data voltage Vdata required by the plurality of sub-pixels 101 located in different rows.

[0053] In the embodiment of the present application, the display panel 100 is provided to include a plurality of multiplexer circuits 50, and one of the multiplexer circuits 50 is electrically connected to a data lead P1, so that the same multiplexer circuit 50 can sequentially transmit the data voltage Vdata required by the sub-pixels 101 of different rows, which is beneficial to reducing the number of data leads P1 required to be prepared in the frame area AA0, and is beneficial to improving the problem of an increase in the number of data leads P1 caused by an increase in the number of data lines 40 in the embodiment of the present application. This is beneficial to improving the problem of a large number of power supply terminals required in the frame area AA0, and reducing the pressure of preparing the power supply terminals in the frame area AA0.

[0054] In one embodiment of the present application, continue to refer to Fig.10 As shown, a plurality of switches 501 of the multi-way selection circuit 50 are located in the lower frame area A20, and output ends of the plurality of switches 501 are electrically connected to the data lines 40 through the second connection lines SL4.

[0055] In the embodiment of the present application, multiple switches 401 of the multi-way selection circuit 50 are electrically connected to the data line 40 by means of the second connecting line SL4, which is beneficial to reducing the correspondence accuracy between the position of the multi-way selection circuit 50 and the position of the data line 40, and is beneficial to more flexibly prepare the position of the multi-way selection circuit 50, thereby improving the layout flexibility of the display panel 100.

[0056] Fig.11 A schematic plan view of another display panel provided in an embodiment of the present application.

[0057] In one embodiment of the present application, Fig.11As shown, the multiple switches 501 included in the multiple selection circuit 50 are located in the first sub-frame area A31, the data lead P1 electrically connected to the input end of the multiple switches 501 extends from the lower frame area A31 through the display area A10 to the first sub-frame area A31, the power supply end of the data lead P1 is located in the lower frame area A20, and the data lead P1 electrically connected to the multiple selection circuit 50 extends from the lower frame area A20 to the first sub-frame area A31. The power supply end that generates the data voltage generates different time signals in the lower frame area A20 in time division, and is transmitted to the input end of the multiple selection circuit 50 by the data lead P1. The multiple switches 501 in the multiple selection circuit 50 are started in time division to receive the corresponding data voltage Vdata.

[0058] In the embodiment of the present application, the multiple switches of the multi-way selection circuit 50 are located in the first sub-frame area A31, which is conducive to making the switch 501 adjacent to the data line 40 in the second direction X2, providing conditions for the data line 40 to be directly electrically connected to the output end of the switch 501, thereby reducing winding. The data lead P1 extends from the lower frame area A20 to the first sub-frame area A31, which is conducive to the preparation of the power supply end of the multi-way selection circuit 50 and the output data voltage Vdata in two frame areas, which is conducive to reducing the wiring pressure of a certain frame area, and is conducive to reducing the width of the frame area AA0 that needs to be prepared for the display panel 100 by reducing the wiring in one of the frame areas, thereby increasing the area of ​​the display area A10 of the display panel 100.

[0059] Fig.12 A schematic plan view of another display panel provided in an embodiment of the present application.

[0060] In one embodiment of the present application, Fig.12 As shown, a multi-way selection circuit 50 is provided to include N3 switches 501, and the first switch 50A of the multi-way selection circuit 50 is located in the lower frame area A20 and its input end is electrically connected to the data lead P1. The remaining N3-1 switches of the multi-way selection circuit 50 are located in the first sub-frame area A31, and each output end of the N3-1 switches is electrically connected to the corresponding data line 40. In the embodiment of the present application, N3=3 is used as an example for explanation. Fig.12 As shown, the multi-way selection circuit 50 includes three switches 501, wherein the first switch 50A is located in the lower frame area A20, and the remaining two switches are located in the first sub-frame area A31. Preparing the switches of the multi-way selection circuit 50 in the lower frame area A20 and the first sub-frame area A31 respectively is conducive to increasing the space available for preparing the multi-way selection circuit 50 and reducing the pressure of preparing circuits in frame areas at different positions.

[0061] In the embodiment of the present application, the output end of the switch located in the lower frame area A20 in the multi-way selection circuit 50 is electrically connected to the data line 40 through the second connection line SL4, and the input ends of the remaining N3-1 switches located in the first sub-frame area A31 in the multi-way selection circuit 50 are all electrically connected to the data line 40 electrically connected to the first switch. That is to say, the first switch 50A is not only used to transmit the data voltage Vdata required by the sub-pixels 101 of one row, but also used to transmit the data voltage Vdata required by the sub-pixels 101 of the remaining two rows. When the data line 40 electrically connected to the switch 501 located in the first sub-frame area A31 requires the data voltage Vdata, the first switch 50A is also turned on and outputs the corresponding data voltage Vdata. At this time, the row of the sub-pixels 101 directly electrically connected to the first switch 50A does not start to receive the data voltage Vdata, which is conducive to improving the utilization rate of the first switch 50A in the multi-way selection circuit 50, saving the number of wirings electrically connected to the multi-way selection circuit 50, and improving the available space in the display panel 100.

[0062] In one embodiment of the present application, continue to refer to Fig.12 As shown, the output ends of the multiple switches 501 included in the multi-way selection circuit 50 are respectively electrically connected to the N3 rows of sub-pixels 101 arranged in sequence in the first direction X1. In combination with the above content, N3=3, taking the multiple switches 501 included in the multi-way selection circuit 50 as an example, which are respectively electrically connected to the sub-pixels 101 in three adjacent rows. The data lead P1 electrically connected to the first switch 50A included in the multi-way selection circuit 50 first sequentially transmits the data voltage Vdata required by the sub-pixels 101 electrically connected to the N3-1 switches located in the first sub-frame area A31, and finally transmits the data voltage Vdata required by the sub-pixel 101 electrically connected to the first switch 50A.

[0063] Since the data voltage Vdata required by the sub-pixel 101 electrically connected to the two switches in the first sub-border area A31 must be transmitted through the first switch 50A, when the first switch 50A transmits the data voltage Vdata required by the sub-pixel 101 electrically connected to the switch in the first sub-border area A31, the data voltage Vdata will also be pre-stored by the data line 40 electrically connected to the first switch.

[0064] In the embodiment of the present application, when the data lead P1 transmits the data voltage Vdata, the data voltage Vdata required by the sub-pixel 101 electrically connected to the data line 40 electrically connected to the switch 501 located in the first sub-border area A31 is transmitted first, and finally the data voltage Vdata required by the sub-pixel 101 electrically connected to the data line 40 directly electrically connected to the first switch 50A is transmitted. This is beneficial for covering the pre-stored data voltage Vdata of the data line 40 electrically connected to the first switch 50A, so that the sub-pixel 101 electrically connected thereto receives the accurate data voltage Vdata, thereby ensuring the accuracy of the light brightness emitted by each sub-pixel 101.

[0065] Fig.13 A schematic plan view of another display device provided in an embodiment of the present application.

[0066] The present application embodiment provides a display device 200, such as Fig.13 As shown, the display device 200 includes the display panel 100 provided in the above embodiment. The display device 200 can be a device for display such as a computer, a mobile phone, etc.

[0067] In the display device 200, the scan lines 20 in the display panel 100 are arranged to extend in the first direction X1 and arranged in the second direction X2, which is beneficial for the scan lines 20 to drive the pixels 10 column by column, thereby reserving more time for writing data voltages for the pixels 10 in each column at the same refresh frequency, which is beneficial for preparing the display panel 100 for display technology with a higher refresh frequency, and is beneficial for increasing the time for each pixel 10 in the display panel 100 to receive the data voltage Vdata at the same refresh frequency, thereby improving the accuracy of the data voltage Vdata received by the pixel 10, improving the accuracy of the luminous brightness of the pixel 10, and improving the display effect of the display panel 100 in high-frequency operation.

[0068] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: A display area and a lower frame area, wherein the display area and the lower frame area are arranged along a first direction, and the lower frame area includes a plurality of pins; A plurality of pixels, the number of the pixels arranged along the first direction is N1, the number of the pixels arranged along the second direction is N2, N1>N2, and the first direction intersects the second direction; A plurality of scan lines are arranged along the second direction, wherein the scan lines extend along the first direction and are electrically connected to the plurality of pixels arranged along the first direction.

2. The display panel according to claim 1, characterized in that: The display panel further comprises a frame area, the frame area comprises a lower frame area and a side frame area, the frame area surrounds the display area; the side frame area comprises a first sub-frame area, the first sub-frame area is located at two opposite sides of the display area in the second direction; the display panel further comprises a plurality of cascaded shift register circuits, at least part of the shift register circuits is located in the first sub-frame area; The shift register circuit includes an output end, and the display area further includes a plurality of first connecting lines, and at least part of the scan lines are electrically connected to the output end of the shift register circuit through the first connecting lines.

3. The display panel according to claim 2, characterized in that: The frame area further includes an upper frame area, and the upper frame area and the lower frame area are respectively located on two opposite sides of the display panel in the first direction; At least a portion of the shift register circuit is located within the upper border area.

4. The display panel according to claim 2, characterized in that: The first connecting line and the scanning line are located in different film layers.

5. The display panel according to claim 2, characterized in that: The display panel further comprises a first power signal line and a second power signal line, and at least a portion of the first power signal line and / or at least a portion of the second power signal line is located in the frame area; At least part of the shift register circuit is located in a first area within the first sub-border area, at least part of the first power signal line and / or at least part of the second power signal line is located in a second area within the first sub-border area, and the first area and the second area are arranged along the first direction.

6. The display panel according to claim 1, characterized in that: The pixel includes sub-pixels, and the display panel further includes a plurality of data lines, wherein the data lines extend along the second direction and are electrically connected to the plurality of sub-pixels arranged along the second direction.

7. The display panel according to claim 6, characterized in that: The display area includes a plurality of second connection lines, the lower frame area includes a plurality of data lead lines, and at least part of the data lines are electrically connected to the data lead lines in the lower frame area through the second connection lines.

8. The display panel according to claim 6 or 7, characterized in that: The display panel further includes a side frame area, and the side frame area further includes a first sub-frame area, and the first sub-frame area is located at two opposite sides of the display area in the second direction; The first sub-frame area includes a plurality of data leads arranged along the first direction, and the data lines are electrically connected to the data leads.

9. The display panel according to claim 8, characterized in that: A first gap is provided between two adjacent pixels, and at least a portion of the second connecting line passes through the first gap and is electrically connected to the data line.

10. The display panel according to claim 9, characterized in that: N3 second connection lines pass through the first gap; Among them, N3≥1.

11. The display panel according to claim 7, characterized in that: The second connecting line and the data line are located in different film layers.

12. The display panel according to claim 7, characterized in that: The display panel also includes a plurality of multi-way selection circuits, each of which includes switches, wherein input ends of the plurality of switches of the multi-way selection circuit are electrically connected to the same data lead, and output ends of the plurality of switches of the multi-way selection circuit are electrically connected to different data lines, respectively.

13. The display panel according to claim 12, characterized in that: The multiple switches of the multi-way selection circuit are located in the lower frame area, and the output ends of the multiple switches are electrically connected to the data lines through the second connecting lines respectively.

14. The display panel according to claim 12, characterized in that: The multiple switches included in the multi-way selection circuit are located in the first sub-frame area, and the data leads electrically connected to the input ends of the multiple switches extend from the lower frame area through the display area to the first sub-frame area.

15. The display panel according to claim 12, characterized in that: The multi-way selection circuit includes N3 switches, the first switch of the multi-way selection circuit is located in the lower frame area and its input end is electrically connected to the data lead; the remaining N3-1 switches of the multi-way selection circuit are located in the first sub-frame area, and each output end of the N3-1 switches is electrically connected to the corresponding data line; The output end of the switch located in the lower border area in the multi-way selection circuit is electrically connected to the data line through the second connecting line, and the input ends of the remaining N3-1 switches located in the first sub-border area in the multi-way selection circuit are all electrically connected to the data line electrically connected to the first switch.

16. The display panel according to claim 15, characterized in that: The output ends of the multiple switches included in the multi-way selection circuit are respectively electrically connected to the N3 rows of sub-pixels arranged in sequence in the first direction; the data leads electrically connected to the first switch included in the multi-way selection circuit first transmit the data voltages required by the sub-pixels electrically connected to N3-1 switches located in the first sub-border area in sequence, and finally transmit the data voltages required by the sub-pixels electrically connected to the first switch.

17. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-16.

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