Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a plurality of sub-pixels and a plurality of first signal lines, the first signal lines are electrically connected with the sub-pixels, the first signal lines extend along a first direction, the plurality of first signal lines are arranged along a second direction, and the first direction intersects with the second direction; in the multiple sub-pixels arranged in the first direction, at least part of the sub-pixels are electrically connected with the same first signal line, and the sub-pixels electrically connected with the same first signal line have the same color; the display panel further comprises a plurality of demultiplexers, each demultiplexer comprises an input end and at least two output ends, the input ends are electrically connected with the initial signal lines, and the at least two output ends are electrically connected with different first signal lines respectively; wherein in the same demultiplexer, the number of the output ends is twice that of the input ends. The power consumption of the display panel can be reduced on the basis of not influencing the quality of a display picture, and the cost of a driving chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel, a data signal line is usually provided to provide a data voltage to a sub-pixel, and the sub-pixel can display a corresponding brightness according to the received data voltage. However, in the prior art, the power consumption caused by the signal jump on the data signal line is high, which is not conducive to energy saving and consumption reduction. Therefore, a solution is urgently needed. Summary of the invention

[0003] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising a plurality of sub-pixels and a plurality of first signal lines, wherein the first signal lines are electrically connected to the sub-pixels, the first signal lines extend along a first direction, and the plurality of first signal lines are arranged along a second direction, and the first direction intersects with the second direction; among the plurality of sub-pixels arranged along the first direction, at least some of the sub-pixels are electrically connected to the same first signal line, and the colors of the sub-pixels electrically connected to the same first signal line are the same; the display panel also comprises a plurality of demultiplexers, the demultiplexers comprising an input terminal and at least two output terminals, the input terminal being electrically connected to the initial signal line, and the at least two output terminals being electrically connected to different first signal lines, respectively; wherein, in the same demultiplexer, the number of output terminals is twice the number of input terminals.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0006] In the embodiment of the present application, if the sub-pixels electrically connected to the same first signal line have the same color, the first signal line can only transmit signals to the sub-pixels of the same color, which is beneficial to reducing the degree of signal jumps on the first signal line and reducing power consumption.

[0007] At the same time, the input end of the demultiplexer is electrically connected to the initial signal line, and at least two output ends are electrically connected to the first signal line. Then, at least two first signal lines can be electrically connected to the same initial signal line through the demultiplexer, which is beneficial to reducing the number of initial signal lines in the display panel, and further beneficial to reducing the number of ports of the driving chip, saving the cost of the driving chip.

[0008] In addition, setting the number of output terminals of the demultiplexer to twice the number of input terminals can help avoid excessive compression of the opening time of the switch unit in the demultiplexer during the scanning period of a row of sub-pixels, thereby helping to improve the accuracy of the signal transmitted from the initial signal line to the first signal line, and further helping to improve the accuracy of the sub-pixel receiving signal, thereby ensuring the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0010] Figure 1 It is a schematic plan view of a display panel in the prior art;

[0011] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application;

[0012] Figure 3 for Figure 2 A timing diagram of a demultiplexer in FIG.

[0013] Figure 4 for Figure 2 A timing diagram of the display panel shown;

[0014] Figure 5 A schematic plan view of another display panel provided in an embodiment of the present application;

[0015] Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application;

[0016] Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application;

[0017] Figure 8 for Figure 7 A timing diagram of the display panel shown;

[0018] Fig. 9 A schematic plan view of another display panel provided in an embodiment of the present application;

[0019] Fig.10 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0021] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0023] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0024] Figure 1 The figure is a plan view of a display panel in the prior art.

[0025] In the prior art, the display panel 01' comprises a plurality of sub-pixels 10' and a plurality of data signal lines 20', the data signal lines 20' are electrically connected to the sub-pixels 10' and are used to transmit data signals to the sub-pixels 10'. The data signal lines 20' extend along the column direction Y', and the plurality of data lines 20' are arranged along the row direction X'.

[0026] The plurality of sub-pixels 10' include a first color sub-pixel 11', a second color sub-pixel 12' and a third color sub-pixel 13'. The plurality of first color sub-pixels 11' and the plurality of second color sub-pixels 12' are located in the same column, and the plurality of third color sub-pixels 13' are located in the same column.

[0027] The sub-pixels 10 ′ in the same column are electrically connected to the same data signal line 20 ′.

[0028] The inventor of the present application has found through research that in the existing display panel 01', the sub-pixels 10' electrically connected to the same data signal line 20' include first color sub-pixels 11' and second color sub-pixels 12' of different colors. That is, the same data signal line 20' needs to provide data signals to sub-pixels 10' of different colors.

[0029] Since the data signals required by the first color sub-pixel 11 ′ and the second color sub-pixel 12 ′ of different colors are usually quite different, this will cause a large signal jump degree on the same data signal line 20 ′ connected to the two, increase power consumption, and be disadvantageous to energy saving and consumption reduction.

[0030] In view of this, an embodiment of the present application provides a solution to solve the problems existing in the prior art.

[0031] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application.

[0032] The present application embodiment provides a display panel 01, such as Figure 2 As shown, the display panel 01 includes a plurality of sub-pixels 10 and a plurality of first signal lines 20, the first signal lines 20 are electrically connected to the sub-pixels 10, and the first signal lines 20 can be used to transmit data voltages to pixel circuits in the sub-pixels 10. The first signal lines 20 extend along a first direction Y, and the plurality of first signal lines 20 are arranged along a second direction X, and the first direction Y intersects with the second direction X.

[0033] Exemplarily, the first direction Y is the column direction of the display panel 01 , and the second direction X is the row direction of the display panel 01 .

[0034] Among the plurality of sub-pixels 10 arranged along the first direction Y, at least some of the sub-pixels 10 are electrically connected to the same first signal line 20 , and the sub-pixels 10 electrically connected to the same first signal line 20 have the same color.

[0035] That is, at least part of the sub-pixels 10 arranged along the first direction Y may share the same first signal line 20 , and the sub-pixels 10 sharing the same first signal line 20 have the same color.

[0036] For example, Figure 2 As shown, the plurality of first signal lines 20 include a first sub-signal line 21 and a second sub-signal line 22. The plurality of sub-pixels 10 arranged along the first direction Y include a first color sub-pixel 11 and a second color sub-pixel 12, wherein each first color sub-pixel 11 is electrically connected to the first sub-signal line 21, and each second color sub-pixel 12 is electrically connected to the second sub-signal line 22.

[0037] In addition, the plurality of first signal lines 20 further include a third sub-signal line 23 , the plurality of sub-pixels 10 further include third color sub-pixels 13 , and the third color sub-pixels 13 arranged along the first direction Y are electrically connected to the third sub-signal line 23 .

[0038] Please continue to refer to Figure 2 The display panel 01 further includes a plurality of demultiplexers 30, and the demultiplexers 30 include an input terminal 31 and at least two output terminals 32. The input terminal 31 is electrically connected to the initial signal line 40, and the at least two output terminals 32 are electrically connected to different first signal lines 20, respectively. The initial signal line 40 can be used to transmit the data voltage output by the driving chip to the demultiplexer 30, and the demultiplexer 30 transmits the received data voltage to the first signal line 20, and finally transmits it to the pixel circuit of the sub-pixel 10.

[0039] In the same demultiplexer 30 , the number of output terminals 32 is twice the number of input terminals 31 .

[0040] Optionally, the demultiplexer 30 includes an input terminal 31 and two output terminals 32 .

[0041] For example, Figure 2 As shown, the two output terminals 32 of the demultiplexer 30 include a first output terminal 321 and a second output terminal 322. The demultiplexer 30 further includes a plurality of switch units K, the plurality of switch units K including a first transistor T1 and a second transistor T2, the first transistor T1 having a first electrode electrically connected to the input terminal 31, a second electrode electrically connected to the first output terminal 321, and a gate electrically connected to the first control signal line MUX1; the second transistor T2 having a first electrode electrically connected to the input terminal 31, a second electrode electrically connected to the second output terminal 322, and a gate electrically connected to the second control signal line MUX2.

[0042] Combination Figure 3 As shown, Figure 3 for Figure 2 A timing diagram of the demultiplexer in the embodiment, the first control signal line MUX1 and the second control signal line MUX2 transmit the enable signal in time-sharing, in the phase Z1 when the first control signal line MUX1 transmits the enable signal (such as a low level signal), the first transistor T1 is turned on, the second transistor T2 is turned off, and the signal received by the input terminal 31 is transmitted to the first output terminal 321 through the first transistor T1. In the phase Z2 when the second control signal line MUX2 transmits the enable signal (such as a low level signal), the second transistor T2 is turned on, the first transistor T1 is turned off, and the signal received by the input terminal 31 is transmitted to the second output terminal 322 through the second transistor T1.

[0043] Exemplarily, in the multiple demultiplexers 30 in the display panel 01, the first transistor T1 in each demultiplexer 30 is electrically connected to the same first control signal line MUX1, and the signal provided by the first control signal line MUX1 controls the switching state of each first transistor T1 to be the same; the second transistor T2 in each demultiplexer 30 is electrically connected to the same second control signal line MUX2, and the signal provided by the second control signal line MUX2 controls the switching state of each second transistor T2 to be the same.

[0044] In the embodiment of the present application, if the sub-pixels 10 electrically connected to the same first signal line 20 have the same color, the first signal line 20 can only transmit signals to the sub-pixels 10 of the same color, which is beneficial to reducing the degree of signal jumps on the first signal line 20 and reducing power consumption.

[0045] At the same time, the input end 31 of the demultiplexer 30 is electrically connected to the initial signal line 40, and at least two output ends 32 are electrically connected to the first signal line 20. Then, at least two first signal lines 20 can be electrically connected to the same initial signal line 40 through the demultiplexer 30, which is beneficial to reducing the number of initial signal lines 40 in the display panel 01, and further beneficial to reducing the number of ports of the driving chip, saving the cost of the driving chip.

[0046] In addition, setting the number of output terminals 32 of the demultiplexer 30 to twice the number of input terminals 31 can help avoid excessive compression of the opening time of the switch unit K in the demultiplexer 30 during the scanning period of a row of sub-pixels 10, thereby helping to improve the accuracy of the signal transmitted from the initial signal line 40 to the first signal line 20, and further helping to improve the accuracy of the sub-pixel 10 receiving the signal, thereby ensuring the display quality.

[0047] In one embodiment of the present application, please continue to refer to Figure 2 The plurality of sub-pixels 10 include first color sub-pixels 11 and second color sub-pixels 12, and the first color sub-pixels 11 and the second color sub-pixels 12 may be arranged in an array along a first direction Y and a second direction X. That is, some of the first color sub-pixels 11 and the second color sub-pixels 12 may be arranged along the first direction Y, and some of the first color sub-pixels 11 and the second color sub-pixels 12 may be arranged along the second direction X.

[0048] The display panel 01 further includes a second signal line 50 extending along the first direction X, the second signal line 50 being electrically connected to the sub-pixel 10, and the second signal line 50 being used to transmit a scan signal to a pixel circuit in the sub-pixel 10, and a data signal can be written into the pixel circuit of the sub-pixel 10 during a period in which the second signal line 50 transmits an enable signal. A plurality of sub-pixels 10 arranged along the second direction X form a sub-pixel row 101, and the same sub-pixel row 101 can be electrically connected to the same second signal line 50.

[0049] The output end 32 of the demultiplexer 30 includes a first output end 321 and a second output end 322. In the same sub-pixel row 101, the first color sub-pixel 11 and the second color sub-pixel 12 are electrically connected to different first output ends 321 or different second output ends 322, respectively.

[0050] That is, a subpixel row 101 includes a first color subpixel 11 and a second color subpixel 12 , and the first color subpixel 11 and the second color subpixel 12 in the same subpixel row 101 are both electrically connected to the first output terminal 321 , or are both electrically connected to the second output terminal 322 .

[0051] like Figure 4 As shown, Figure 4 for Figure 2A timing diagram of the display panel shown in FIG. 1 shows that in the time period Z when the second signal line 50 transmits an enable signal (such as a low level signal), the first control signal line MUX1 transmits an enable signal (such as a low level signal), or the second control line MUX2 transmits an enable signal (such as a low level signal).

[0052] In the embodiment of the present application, the first color sub-pixel 11 and the second color sub-pixel 12 in the same sub-pixel row 101 are both electrically connected to the first output terminal 321, or both electrically connected to the second output terminal 322. Then, during the period Z when the second signal line 50 transmits the enable signal, only the first control signal line MUX1 can be controlled to transmit the enable signal, or only the second control signal line MUX2 can be controlled to transmit the enable signal, so that the data signal writing of the first color sub-pixel 11 and the second color sub-pixel 12 in the sub-pixel row 101 can be realized. In this way, during the scanning process of a sub-pixel row 101, only one of the first transistor T1 and the second transistor T2 needs to be controlled to be turned on, and there is no need to control both the first transistor T1 and the second transistor T2 to be turned on, which is conducive to further reducing the power consumption of the display panel 01.

[0053] Moreover, since only one of the first transistor T1 and the second transistor T2 needs to be turned on, the time period Z1 during which the first control signal line MUX1 transmits the enable signal, or the time period Z2 during which the second control signal line MUX2 transmits the enable signal can be approximately the same as the time period Z during which the second signal line 50 transmits the enable signal, which is beneficial to increase the charging time of the first color sub-pixel 11 and the second color sub-pixel 12, further improve the accuracy of the first color sub-pixel 11 and the second color sub-pixel 12 receiving the data signal, and thus is beneficial to further ensure the display quality of the display panel 01.

[0054] Optional, such as Figure 2 As shown, in two adjacent sub-pixel rows 101 in the first direction Y, the first color sub-pixel 11 and the second color sub-pixel 12 in one are electrically connected to different first output terminals 321, respectively, and the first color sub-pixel 11 and the second color sub-pixel 12 in the other are electrically connected to different second output terminals 322, respectively.

[0055] For example, Figure 2 As shown, the plurality of sub-pixel rows 101 include a first sub-pixel row 1011 , a second sub-pixel row 1012 , a third sub-pixel row 1013 and a fourth sub-pixel row 1014 which are sequentially arranged along the first direction Y.

[0056] The first color sub-pixel 11 and the second color sub-pixel 12 in the first sub-pixel row 1011 are both electrically connected to the first output terminal 321, the first color sub-pixel 11 and the second color sub-pixel 12 in the second sub-pixel row 1012 are both electrically connected to the second output terminal 322, the first color sub-pixel 11 and the second color sub-pixel 12 in the third sub-pixel row 1013 are both electrically connected to the first output terminal 321, and the first color sub-pixel 11 and the second color sub-pixel 12 in the fourth sub-pixel row 1014 are both electrically connected to the second output terminal 322.

[0057] The plurality of second signal lines 50 include a first row of scan lines 51, a second row of scan lines 52, a third row of scan lines 53 and a fourth row of scan lines 54 which are arranged in sequence in the first direction Y, the first row of scan lines 51 is electrically connected to the first sub-pixel row 1011, the second row of scan lines 52 is electrically connected to the second sub-pixel row 1012, the third row of scan lines 53 is electrically connected to the third sub-pixel row 1013, and the fourth row of scan lines 54 is electrically connected to the fourth sub-pixel row 1014.

[0058] Combination Figure 4 As shown, during the time period Z when the first row scan line 51 and the third row scan line 53 transmit the enable signal (such as a low level signal), the first control signal line MUX1 transmits the enable signal (such as a low level signal), and during the time period Z when the second row scan line 52 and the fourth row scan line 54 transmit the enable signal (such as a low level signal), the second control signal line MUX2 transmits the enable signal (such as a low level signal).

[0059] In one embodiment of the present application, please continue to refer to Figure 2 In the same demultiplexer 30 , the first output terminal 321 and the second output terminal 322 are electrically connected to different sub-pixel rows 101 , respectively.

[0060] Exemplarily, the first output terminal 321 is electrically connected to the odd sub-pixel row 101, and the second output terminal 322 is electrically connected to the even sub-pixel row 101. That is, in the same demultiplexer 30, the first signal line 20 connected to the first output terminal 321 is electrically connected to the sub-pixels 10 in the odd rows; the first signal line 20 connected to the second output terminal 322 is electrically connected to the sub-pixels 10 in the even rows.

[0061] In the same demultiplexer 30 , the sub-pixels 10 electrically connected to the first output terminal 321 and the second output terminal 322 have the same color.

[0062] For example, Figure 2As shown, in the partial demultiplexer 30, the first output terminal 321 is electrically connected to the first color sub-pixel 11 of the odd-numbered rows, and the second output terminal 322 is electrically connected to the first color sub-pixel 11 of the even-numbered rows. In the partial demultiplexer 30, the first output terminal 321 is electrically connected to the second color sub-pixel 12 of the odd-numbered rows, and the second output terminal 322 is electrically connected to the second color sub-pixel 12 of the even-numbered rows.

[0063] In the embodiment of the present application, the first output terminal 321 and the second output terminal 322 of the same demultiplexer 30 are set, and the sub-pixels 10 electrically connected have the same color. Then, the initial signal line 40 electrically connected to the input terminal 31 of the demultiplexer 30 can only transmit the data signal required by the sub-pixels 10 of the same color, which is beneficial to reduce the degree of signal jump on the initial signal line 40, thereby helping to further reduce the power consumption of the display panel 01.

[0064] Please continue to refer to Figure 2 In one embodiment of the present application, the first color sub-pixels 11 and the second color sub-pixels 12 arranged along the first direction Y constitute a first sub-pixel column 102, and a plurality of first sub-pixel columns 102 are arranged along the second direction X.

[0065] Exemplarily, the first sub-pixel column 102 includes the first color sub-pixel 11 and the second color sub-pixel 12 , but does not include the third color sub-pixel 13 .

[0066] In the same demultiplexer 30 , the first output terminal 321 and the second output terminal 322 are electrically connected to two adjacent first sub-pixel columns 102 , respectively.

[0067] That is to say, no other first sub-pixel columns 102 are arranged between two first sub-pixel columns 102 electrically connected to the same demultiplexer 30 .

[0068] In the embodiment of the present application, while reducing the degree of signal jump on the initial signal line 40, the two first signal lines 20 electrically connected to the same demultiplexer 30 can be made closer, which is beneficial to reducing the difficulty of electrically connecting the output end 32 of the demultiplexer 30 with the first signal line 20, thereby helping to reduce the difficulty of preparing the display panel 01.

[0069] Figure 5 A schematic plan view of another display panel provided in an embodiment of the present application.

[0070] Optional, such as Figure 5 As shown, the first color sub-pixels 11 and the second color sub-pixels 12 arranged along the first direction Y form a first sub-pixel column 102 , and a plurality of first sub-pixel columns 102 are arranged along the second direction X.

[0071] For example, Figure 5As shown, the first sub-pixel column 102 includes a first color sub-pixel 11 and a second color sub-pixel 12 , but does not include a third color sub-pixel 13 .

[0072] In the same demultiplexer 30 , the first output terminal 321 and the second output terminal 322 are electrically connected to two first sub-pixel columns 102 arranged at intervals, respectively.

[0073] That is to say, other first sub-pixel columns 102 may be arranged between two first sub-pixel columns 102 electrically connected to the same demultiplexer 30 .

[0074] Of course, since the display panel 01 includes a plurality of demultiplexers 30, it can be configured that in some demultiplexers 30, the first output terminal 321 and the second output terminal 322 are respectively electrically connected to two first sub-pixel columns 102 arranged at intervals. In some demultiplexers 30, the first output terminal 321 and the second output terminal 322 are respectively electrically connected to two adjacent first sub-pixel columns 102.

[0075] For example, Figure 5 As shown, the multiple demultiplexers 30 include a demultiplexer 30A and a demultiplexer 30B. In the demultiplexer 30A, the first output terminal 321 and the second output terminal 322 are respectively electrically connected to two adjacent first sub-pixel columns 102. In the demultiplexer 30B, the first output terminal 321 and the second output terminal 322 are respectively electrically connected to two first sub-pixel columns 102 arranged at intervals.

[0076] Based on this arrangement, on the one hand, it is beneficial to increase the structural diversity of the display panel 01, and on the other hand, it is beneficial to flexibly adjust the first sub-pixel column 102 connected thereto according to the position of the demultiplexer 30, so that the wiring can be flexibly performed according to the actual layout of the display panel 01.

[0077] In one embodiment of the present application, Figure 2 and Figure 4 As shown, the display panel 01 further includes a plurality of second signal lines 50, the second signal lines 50 extend along the second direction X, and the plurality of second signal lines 50 are arranged along the first direction Y. The second signal lines 50 can be used to transmit scan signals to the pixel circuits in the sub-pixels 10, and during the period when the second signal lines 50 transmit enable signals, data voltages can be written into the pixel circuits of the sub-pixels 10.

[0078] At least part of the sub-pixels 10 arranged along the second direction X are electrically connected to the same second signal line 50 . Exemplarily, the same sub-pixel row 101 is electrically connected to the same second signal line 50 .

[0079] Among them, in the period when the first output terminal 321 outputs a signal and the period when the second output terminal 322 outputs a signal, one overlaps with the period Z when the second signal line 50 transmits an enable signal, and the other does not overlap with the period Z when the second signal line 50 transmits an enable signal.

[0080] It is understandable that the period when the first transistor T1 is turned on is the period when the first output terminal 321 outputs a signal, and the period when the second transistor T2 is turned on is the period when the second output terminal 322 outputs a signal. The signals output by the first output terminal 321 and the second output terminal 322 are data signals.

[0081] Since the first control signal line MUX1 transmits an enable signal to control the first transistor T1 to turn on, and the second control signal line MUX2 transmits an enable signal to control the second transistor T2 to turn on, therefore, one of the time periods when the first output terminal 321 outputs a signal and the time period when the second output terminal 322 outputs a signal overlaps with the time period Z when the second signal line 50 transmits an enable signal, and the other does not overlap with the time period Z when the second signal line 50 transmits an enable signal, which means that one of the time periods Z1 when the first control signal line MUX1 transmits an enable signal and the time period Z2 when the second control signal line MUX2 transmits an enable signal overlaps with the time period Z when the second signal line 50 transmits an enable signal, and the other does not overlap with the time period Z when the second signal line 50 transmits an enable signal.

[0082] For example, combined with Figure 2 and Figure 4 As shown, the multiple second signal lines 50 include a first row scan line 51, the time period Z1 of the first control signal line MUX1 transmitting the enable signal overlaps with the time period Z of the first row scan line 51 transmitting the enable signal, and the time period Z2 of the second control signal line MUX2 transmitting the enable signal does not overlap with the time period Z of the first row scan line 51 transmitting the enable signal.

[0083] In the embodiment of the present application, during the time period Z when the second signal line 50 transmits the enable signal, only the first control signal line MUX1 may transmit the enable signal, or only the second control signal line MUX2 may be controlled to transmit the enable signal. Therefore, the time period Z1 when the first control signal line MUX1 transmits the enable signal, or the time period Z2 when the second control signal line MUX2 transmits the enable signal may be approximately the same as the time period Z when the second signal line 50 transmits the enable signal, which is beneficial to increase the charging time of the first color sub-pixel 11 and the second color sub-pixel 12, further improve the accuracy of the first color sub-pixel 11 and the second color sub-pixel 12 receiving the data signal, and thus is beneficial to further ensure the display quality of the display panel 01.

[0084] Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application.

[0085] In one embodiment of the present application, Figure 6 As shown, in the same demultiplexer 30 , the first output terminal 321 and the second output terminal 322 are electrically connected to different sub-pixel rows 101 , respectively.

[0086] For example, Figure 6 As shown, the first output terminal 321 is electrically connected to the odd sub-pixel row 101, and the second output terminal 322 is electrically connected to the even sub-pixel row 101. That is, in the same demultiplexer 30, the first signal line 20 connected to the first output terminal 321 is electrically connected to the sub-pixels 10 in the odd rows; the first signal line 20 connected to the second output terminal 322 is electrically connected to the sub-pixels 10 in the even rows.

[0087] The first color sub-pixels 11 and the second color sub-pixels 12 arranged along the first direction Y form a first sub-pixel column 102 , and a plurality of first sub-pixel columns 102 are arranged along the second direction X.

[0088] For example, Figure 6 As shown, the first sub-pixel column 102 includes a first color sub-pixel 11 and a second color sub-pixel 12 , but does not include a third color sub-pixel 13 .

[0089] In the same demultiplexer 30 , the first output terminal 321 and the second output terminal 322 are electrically connected to the same first sub-pixel column 102 .

[0090] From the above analysis, it can be known that the sub-pixels 10 electrically connected to the same first signal line 20 have the same color. Therefore, in the same first sub-pixel column 102, the first color sub-pixel 11 and the second color sub-pixel 12 can be electrically connected to different first signal lines 20. The multiple first signal lines 20 electrically connected to the same first sub-pixel column 102 are usually close to each other.

[0091] In the embodiment of the present application, the first output terminal 321 and the second output terminal 322 of the same demultiplexer 30 are electrically connected to the same first sub-pixel column 102, so that the two first signal lines 20 electrically connected to the same demultiplexer 30 can be closer to each other, which is conducive to facilitating the electrical connection between the output terminal 32 of the demultiplexer 30 and the first signal line 20, thereby helping to further reduce the difficulty of manufacturing the display panel 01.

[0092] For example, Figure 6 As shown, no other first signal line 20 is provided between the two first signal lines 20 electrically connected to the same demultiplexer 30. In this way, the distance between the two first signal lines 20 electrically connected to the same demultiplexer 30 is reduced to a large extent, thereby facilitating the wiring connection between the output end 32 of the same demultiplexer 30 and the first signal line 20.

[0093] It should be noted that, in the embodiment of the present application, the first output terminal 321 and the second output terminal 322 of the same demultiplexer 30 can be electrically connected to sub-pixels 10 of different colors through different first signal lines 20 .

[0094] Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application.

[0095] like Figure 7 As shown, in one embodiment of the present application, a plurality of sub-pixels 10 arranged along the second direction X form a sub-pixel row 101, and a plurality of sub-pixel rows 101 are arranged along the first direction Y. The same sub-pixel row 101 includes a first color sub-pixel 11 and a second color sub-pixel 12.

[0096] The output terminal 32 of the demultiplexer 30 includes a first output terminal 321 and a second output terminal 322. In the same sub-pixel row 101, some sub-pixels 10 are electrically connected to different first output terminals 321, and some sub-pixels 10 are electrically connected to different second output terminals 322.

[0097] For example, Figure 7 As shown, in the same sub-pixel row 101, some first color sub-pixels 11 and second color sub-pixels 12 are electrically connected to the first output terminals 321 of different demultiplexers 30, and some first color sub-pixels 11 and second color sub-pixels 12 are electrically connected to the second output terminals 322 of different demultiplexers 30.

[0098] In the embodiment of the present application, during the scanning process of a sub-pixel row 101 , the first output terminal 321 and the second output terminal 322 of the demultiplexer 30 can output signals in sequence to implement data writing to sub-pixels 10 of different colors in a sub-pixel row 101 .

[0099] Specifically, Figure 7 As shown, the display panel 01 further includes a second signal line 50, the second signal line 50 extends along the second direction X, and a plurality of second signal lines 50 are arranged along the first direction Y. The second signal line 50 can be used to transmit a scan signal to a pixel circuit in the sub-pixel 10, and a data signal can be written into the pixel circuit of the sub-pixel 10 during a period when the second signal line 50 transmits an enable signal.

[0100] At least part of the sub-pixels 10 arranged along the second direction X are electrically connected to the same second signal line 50 . Exemplarily, the same sub-pixel row 101 is electrically connected to the same second signal line 50 .

[0101] Combination Figure 8 As shown, Figure 8 for Figure 7The timing diagram of the display panel is shown, in the period Z when the second signal line 50 transmits the enable signal, the first output terminal 321 and the second output terminal 322 sequentially output signals. Here, the signals sequentially output by the first output terminal 321 and the second output terminal 322 are data signals.

[0102] Since the first control signal line MUX1 transmits an enable signal to control the first transistor T1 to turn on, and the second control signal line MUX2 transmits an enable signal to control the second transistor T2 to turn on, therefore, during the period Z1 when the first control signal line MUX1 transmits the enable signal, the first output terminal 321 outputs a signal; during the period Z2 when the second control signal line MUX2 transmits the enable signal, the second output terminal 322 outputs a signal.

[0103] Based on this setting, during the time period Z when the second signal line 50 transmits the enable signal, the first control signal line MUX1 and the second control signal line MUX2 transmit the enable signal in sequence, and control the first output terminal 321 and the second output terminal 322 to output the data signal in sequence, thereby realizing the writing of data to different sub-pixels 10 in a sub-pixel row 101.

[0104] Please continue to refer to Figure 7 In one embodiment of the present application, in the same demultiplexer 30 , the first output terminal 321 and the second output terminal 322 are electrically connected to the same sub-pixel row 101 .

[0105] For example, Figure 7 As shown, the multiple demultiplexers 30 include a first demultiplexer 301 and a second demultiplexer 302. In the same first demultiplexer 301, the first output terminal 321 and the second output terminal 322 are both electrically connected to the odd sub-pixel rows 101; in the same second demultiplexer 302, the first output terminal 321 and the second output terminal 322 are both electrically connected to the even sub-pixel rows 101.

[0106] In the same demultiplexer 30 , the sub-pixels 10 electrically connected to the first output terminal 321 and the second output terminal 322 have the same color.

[0107] For example, Figure 7 As shown, in the same first demultiplexer 301, the first output terminal 321 and the second output terminal 322 are both electrically connected to the first color sub-pixels 11 of the odd-numbered rows, or are both electrically connected to the second color sub-pixels 12 of the odd-numbered rows. In the same second demultiplexer 302, the first output terminal 321 and the second output terminal 322 are both electrically connected to the first color sub-pixels 11 of the even-numbered rows, or are both electrically connected to the second color sub-pixels 12 of the even-numbered rows.

[0108] In the embodiment of the present application, the first output terminal 321 and the second output terminal 322 of the same demultiplexer 30 are set, and the sub-pixels 10 electrically connected have the same color. Then, the initial signal line 40 electrically connected to the input terminal 31 of the demultiplexer 30 can only transmit the data signal required by the sub-pixels 10 of the same color, which is beneficial to reduce the degree of signal jump on the initial signal line 40, thereby helping to further reduce the power consumption of the display panel 01.

[0109] Fig. 9 A schematic plan view of another display panel provided in an embodiment of the present application.

[0110] In one embodiment of the present application, Fig. 9 As shown, the plurality of sub-pixels 10 include first color sub-pixels 11 and second color sub-pixels 12 , and the first color sub-pixels 11 and the second color sub-pixels 12 are arranged in an array along a first direction Y and a second direction X.

[0111] The first color sub-pixels 11 and the second color sub-pixels 12 arranged along the first direction Y form a first sub-pixel column 102 , and a plurality of first sub-pixel columns 102 are arranged along the second direction X.

[0112] Exemplarily, the first sub-pixel column 102 includes the first color sub-pixel 11 and the second color sub-pixel 12 , but does not include the third color sub-pixel 13 .

[0113] In the same demultiplexer 30 , the first output terminal 321 and the second output terminal 322 are electrically connected to two adjacent first sub-pixel columns 102 , respectively.

[0114] That is to say, no other first sub-pixel columns 102 are arranged between two first sub-pixel columns 102 electrically connected to the same demultiplexer 30 .

[0115] In the embodiment of the present application, while reducing the degree of signal jump on the initial signal line 40, the two first signal lines 20 electrically connected to the same demultiplexer 30 can be made closer, which is beneficial to reducing the difficulty of electrically connecting the output end 32 of the demultiplexer 30 with the first signal line 20, thereby helping to reduce the difficulty of preparing the display panel 01.

[0116] In one embodiment of the present application, Figure 2 , Figure 5-Figure 7 , Fig. 9 As shown, the plurality of sub-pixels 10 include a first color sub-pixel 11, a second color sub-pixel 12, and a third color sub-pixel 13. The plurality of first signal lines 20 include a first sub-signal line 21, a second sub-signal line 22, and a third sub-signal line 23.

[0117] Among them, one end of the first sub-signal line 21 is electrically connected to the first color sub-pixel 11, and the other end is electrically connected to the demultiplexer 30, one end of the second sub-signal line 22 is electrically connected to the second color sub-pixel 12, and the other end is electrically connected to the demultiplexer 30, and one end of the third sub-signal line 23 is electrically connected to the third color sub-pixel 13, and the other end is electrically connected to the initial signal line 40.

[0118] That is to say, in the display panel 01 provided in the embodiment of the present application, the first color sub-pixel 11 and the second color sub-pixel 12 both receive the data signal provided by the initial signal line 40 through the demultiplexer 30, and the third color sub-pixel 13 can be directly connected to the initial signal line 40 and can receive the data signal provided by the initial signal line 40 without going through the demultiplexer 30.

[0119] In the embodiment of the present application, the first color sub-pixel 11 and the second color sub-pixel 12 are both electrically connected to the demultiplexer 30, and the third color sub-pixel 13 is not electrically connected to the demultiplexer 30. On the one hand, the number of demultiplexers 30 in the display panel 01 can be reduced, which is beneficial to cost saving; on the other hand, the control difficulty of the initial signal line 40 transmitting the data signal to the third color sub-pixel 13 can be reduced, which is beneficial to reducing the control difficulty of the display panel 01.

[0120] Optionally, the first color sub-pixel 11 is a red sub-pixel, the second color sub-pixel 12 is a blue sub-pixel, and the third color sub-pixel 13 is a green sub-pixel. The light output from the first color sub-pixel 11, the second color sub-pixel 12, and the third color sub-pixel 13 can cooperate with each other to achieve full-color display of the display panel 01.

[0121] Optional, such as Figure 2 , Figure 5-Figure 7 , Fig. 9 As shown, the first color sub-pixels 11 and the second color sub-pixels 12 arranged along the first direction Y constitute a first sub-pixel column 102 , and the third color sub-pixels 13 arranged along the first direction Y constitute a second sub-pixel column 103 .

[0122] Exemplarily, the first sub-pixel column 102 includes the first color sub-pixel 11 and the second color sub-pixel 12, but does not include the third color sub-pixel 13, and the same first sub-pixel column 102 is electrically connected to the first sub-signal line 21 and the second sub-signal line 22. The second sub-pixel column 103 includes the third color sub-pixel 13, but does not include the first color sub-pixel 11 and the second color sub-pixel 12, and the same second sub-pixel column 103 is electrically connected to the third sub-signal line 23.

[0123] In the second direction X, the first sub-pixel columns 102 and the second sub-pixel columns 103 are arranged alternately.

[0124] Based on this arrangement, the first color sub-pixel 11 , the second color sub-pixel 12 , and the third color sub-pixel 13 can be located relatively close to each other, which is beneficial for improving the picture fineness of the display panel 01 .

[0125] Optional, such as Figure 2 , Figure 5-Figure 7 , Fig. 9 As shown, the first color sub-pixels 11 and the second color sub-pixels 12 are arranged in an array along a first direction Y and a second direction X.

[0126] Wherein, along the first direction Y, the first color sub-pixels 11 and the second color sub-pixels 12 are arranged alternately. Along the second direction X, the first color sub-pixels 11 and the second color sub-pixels 12 are arranged alternately.

[0127] In this way, the distances between the first color sub-pixel 11 , the second color sub-pixel 12 and the third color sub-pixel 13 are further reduced, thereby further improving the picture resolution of the display panel 01 .

[0128] Fig.10 A schematic diagram of a display device provided in an embodiment of the present application.

[0129] The present application also provides a display device 02, such as Fig.10 As shown, the display device 02 includes the display panel 01 provided in the above embodiment. For example, the display device 02 provided in the embodiment of the present application can be an electronic device such as a mobile phone, a computer, a car display, a wearable display, etc., and the present application does not make any specific limitation.

[0130] In the display device 02, if the sub-pixels 10 electrically connected to the same first signal line 20 have the same color, the first signal line 20 can only transmit signals to the sub-pixels 10 of the same color, which is beneficial to reducing the degree of signal jumps on the first signal line 20 and reducing power consumption.

[0131] At the same time, the input end 31 of the demultiplexer 30 is electrically connected to the initial signal line 40, and at least two output ends 32 are electrically connected to the first signal line 20. Then, at least two first signal lines 20 can be electrically connected to the same initial signal line 40 through the demultiplexer 30, which is beneficial to reducing the number of initial signal lines 40 in the display panel 01, and further beneficial to reducing the number of ports of the driving chip, saving the cost of the driving chip.

[0132] In addition, setting the number of output terminals 32 of the demultiplexer 30 to twice the number of input terminals 31 can help avoid excessive compression of the opening time of the switch unit K in the demultiplexer 30 during the scanning period of a row of sub-pixels 10, thereby helping to improve the accuracy of the signal transmitted from the initial signal line 40 to the first signal line 20, and further helping to improve the accuracy of the sub-pixel 10 receiving the signal, thereby ensuring the display quality.

[0133] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The device comprises a plurality of sub-pixels and a plurality of first signal lines, wherein the first signal lines are electrically connected to the sub-pixels, the first signal lines extend along a first direction, and the plurality of first signal lines are arranged along a second direction, and the first direction intersects with the second direction; Among the plurality of sub-pixels arranged along the first direction, at least some of the sub-pixels are electrically connected to the same first signal line, and the sub-pixels electrically connected to the same first signal line have the same color; The display panel further comprises a plurality of demultiplexers, each of the demultiplexers comprising an input terminal and at least two output terminals, wherein the input terminal is electrically connected to an initial signal line, and at least two of the output terminals are electrically connected to different first signal lines respectively; Wherein, in the same demultiplexer, the number of the output terminals is twice the number of the input terminals.

2. The display panel according to claim 1, characterized in that: The plurality of sub-pixels include first color sub-pixels and second color sub-pixels, and the first color sub-pixels and the second color sub-pixels are arranged in an array along the first direction and the second direction; The output ends of the demultiplexer include a first output end and a second output end; The plurality of sub-pixels arranged along the second direction form a sub-pixel row. In the same sub-pixel row, the first color sub-pixels and the second color sub-pixels are electrically connected to different first output terminals, or are electrically connected to different second output terminals, respectively.

3. The display panel according to claim 2, characterized in that: In two adjacent sub-pixel rows in the first direction, the first color sub-pixels and the second color sub-pixels in one are electrically connected to different first output terminals, respectively, and the first color sub-pixels and the second color sub-pixels in the other are electrically connected to different second output terminals, respectively.

4. The display panel according to claim 3, characterized in that: In the same demultiplexer, the first output terminal and the second output terminal are electrically connected to different sub-pixel rows respectively; In the same demultiplexer, the sub-pixels to which the first output terminal and the second output terminal are electrically connected have the same color.

5. The display panel according to claim 4, characterized in that: The first color sub-pixels and the second color sub-pixels arranged along the first direction form a first sub-pixel column, and a plurality of the first sub-pixel columns are arranged along the second direction; In the same demultiplexer, the first output end and the second output end are electrically connected to two adjacent first sub-pixel columns respectively.

6. The display panel according to claim 4, characterized in that: The first color sub-pixels and the second color sub-pixels arranged along the first direction form a first sub-pixel column, and a plurality of the first sub-pixel columns are arranged along the second direction; In at least part of the demultiplexer, the first output end and the second output end are electrically connected to two of the first sub-pixel columns that are arranged at intervals, respectively.

7. The display panel according to claim 2, characterized in that: The display panel further includes a second signal line, the second signal line extends along the second direction, and a plurality of the second signal lines are arranged along the first direction; At least part of the sub-pixels arranged along the second direction are electrically connected to the same second signal line; Among them, in the time period when the first output terminal outputs a signal and the time period when the second output terminal outputs a signal, one overlaps with the time period when the second signal line transmits an enable signal, and the other does not overlap with the time period when the second signal line transmits an enable signal.

8. The display panel according to claim 3, characterized in that: In the same demultiplexer, the first output terminal and the second output terminal are electrically connected to different sub-pixel rows respectively; The first color sub-pixels and the second color sub-pixels arranged along the first direction form a first sub-pixel column, and a plurality of the first sub-pixel columns are arranged along the second direction; Wherein, in the same demultiplexer, the first output end and the second output end are electrically connected to the same first sub-pixel column.

9. The display panel according to claim 1, characterized in that: A plurality of the sub-pixels arranged along the second direction form a sub-pixel row, and a plurality of the sub-pixel rows are arranged along the first direction; The output ends of the demultiplexer include a first output end and a second output end; in the same sub-pixel row, some of the sub-pixels are electrically connected to different first output ends, and some of the sub-pixels are electrically connected to different second output ends.

10. The display panel according to claim 9, characterized in that: In the same demultiplexer, the first output terminal and the second output terminal are electrically connected to the same sub-pixel row; In the same demultiplexer, the sub-pixels to which the first output terminal and the second output terminal are electrically connected have the same color.

11. The display panel according to claim 9, characterized in that: The plurality of sub-pixels include first color sub-pixels and second color sub-pixels, and the first color sub-pixels and the second color sub-pixels are arranged in an array along the first direction and the second direction; The first color sub-pixels and the second color sub-pixels arranged along the first direction form a first sub-pixel column, and a plurality of the first sub-pixel columns are arranged along the second direction; In the same demultiplexer, the first output end and the second output end are electrically connected to two adjacent first sub-pixel columns respectively.

12. The display panel according to claim 9, characterized in that: The display panel further includes a second signal line, the second signal line extends along the second direction, and a plurality of the second signal lines are arranged along the first direction; At least part of the sub-pixels arranged along the second direction are electrically connected to the same second signal line; Wherein, during the period when the second signal line transmits an enable signal, the first output end and the second output end output signals in sequence.

13. The display panel according to claim 1, characterized in that: The plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; the plurality of first signal lines include a first sub-signal line, a second sub-signal line and a third sub-signal line; Among them, one end of the first sub-signal line is electrically connected to the first color sub-pixel, and the other end is electrically connected to the demultiplexer; one end of the second sub-signal line is electrically connected to the second color sub-pixel, and the other end is electrically connected to the demultiplexer; one end of the third sub-signal line is electrically connected to the third color sub-pixel, and the other end is electrically connected to the initial signal line.

14. The display panel according to claim 13, characterized in that: The first color sub-pixels and the second color sub-pixels are arranged in an array along the first direction and the second direction; Along the first direction, the first color sub-pixels and the second color sub-pixels are arranged alternately; along the second direction, the first color sub-pixels and the second color sub-pixels are arranged alternately.

15. The display panel according to claim 13, characterized in that: The first color sub-pixels and the second color sub-pixels arranged along the first direction form a first sub-pixel column, and a plurality of the third color sub-pixels arranged along the first direction form a second sub-pixel column; In the second direction, the first sub-pixel columns and the second sub-pixel columns are arranged alternately.

16. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-15.

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