Flexible circuit board, driving method thereof and display equipment

Abstract

The invention provides a flexible circuit board, a driving method thereof and display equipment. The flexible circuit board comprises a board body, a plurality of input pins, a plurality of output pins and a plurality of signal lines. The plurality of input pins and the plurality of output pins are arranged on the board body. The plurality of signal lines are arranged on the board body, two ends of each signal line are respectively connected with one input pin and one output pin, and the plurality of signal lines are suitable for transmitting data in a three-phase signal mode under a C-PHY transmission protocol and transmitting data in a differential pair mode under a D-PHY transmission protocol. According to the invention, each signal line selectively transmits data in a three-phase signal mode under a C-PHY transmission protocol or in a differential pair mode under a D-PHY transmission protocol according to the enable signal sent by the terminal mainboard in the display device, so that switching of two transmission protocols between the terminal mainboard and the display panel is realized.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a flexible circuit board and a driving method thereof, and a display device. Background Art

[0002] The data transmission between the terminal motherboard and the driver IC (DIC) of the display panel is realized through the Mobile Industry Processor Interface (MIPI) bus. The MIPI bus is divided into three categories according to the data transmission method: C-PHY, D-PHY and MPHY. Display and camera generally use C-PHY or D-PHY.

[0003] However, traditionally, only one communication protocol, C-PHY or D-PHY, can be used to send information between the terminal motherboard and the flexible circuit board, which may result in incompatible communication interfaces between the terminal motherboard and the flexible circuit board. Summary of the invention

[0004] In view of this, the present application provides a flexible circuit board and a driving method thereof, and a display device, so as to improve the problem of incompatibility between the terminal mainboard and the flexible circuit board interface.

[0005] The technical solution adopted by this application to solve the above technical problems is:

[0006] In a first aspect, an embodiment of the present application provides a flexible circuit board, comprising:

[0007] plate body;

[0008] A plurality of input pins and a plurality of output pins, wherein the plurality of input pins and the plurality of output pins are all arranged on the board;

[0009] A plurality of signal lines are arranged on the board, and both ends of each of the signal lines are respectively connected to an input pin and an output pin. The plurality of signal lines transmit data in a three-phase signal mode under the C-PHY transmission protocol and transmit data in a differential pair mode under the D-PHY transmission protocol.

[0010] In some embodiments of the present application, the number of the signal lines is an even number, and under the C-PHY transmission protocol, at least one of the plurality of signal lines does not transmit a signal, and the remaining signal lines are used to transmit data signals.

[0011] In some embodiments of the present application, the number of the signal lines is an odd number, and under the D-PHY transmission protocol, at least two of the multiple signal lines are used to transmit data signals, at least two are used to transmit clock signals, and at least one does not transmit signals.

[0012] In some embodiments of the present application, the flexible circuit board includes two main shielding lines, the main shielding lines are arranged on the board body, the plurality of signal lines are located between the two main shielding lines, and the main shielding lines are grounded.

[0013] In some embodiments of the present application, the flexible circuit board further includes a plurality of secondary shielding lines, wherein the secondary shielding lines are disposed on the board body, the secondary shielding lines are located between two adjacent signal lines, and the secondary shielding lines are grounded.

[0014] In some embodiments of the present application, the distance between two adjacent signal lines is not less than twice the line width of the signal lines.

[0015] In some embodiments of the present application, the flexible circuit board further includes a plurality of secondary shielding lines, three adjacent signal lines constitute a signal channel, the signal channel is used to transmit a three-phase signal, and the secondary shielding lines are provided between adjacent signal channels.

[0016] In a second aspect, an embodiment of the present application provides a display device, including:

[0017] Terminal mainboard;

[0018] A display panel, comprising a driving chip and the flexible circuit board as described in the first aspect, wherein the driving chip is connected to the flexible circuit board;

[0019] Wherein, the terminal mainboard is connected to the flexible circuit board and is used to send an enable signal to the flexible circuit board.

[0020] In some embodiments of the present application, when the enable signal is at a high level, the flexible circuit board adopts the D-PHY communication protocol, and when the enable signal is at a low level, the flexible circuit board adopts the C-PHY communication protocol; or,

[0021] When the enable signal is at a high level, the flexible circuit board adopts the C-PHY communication protocol, and when the enable signal is at a low level, the flexible circuit board adopts the D-PHY communication protocol.

[0022] In a third aspect, an embodiment of the present application provides a method for driving a flexible circuit board, comprising:

[0023] Sending an enable signal to the flexible circuit board;

[0024] According to the enable signal, the flexible circuit board adopts the communication protocol of C-PHY or D-PHY to match the pin rule.

[0025] In some embodiments of the present application, the step of adopting the C-PHY or D-PHY communication protocol of the flexible circuit board to match the pin rule according to the enable signal includes:

[0026] When the enable signal is a high level signal, the flexible circuit board adopts the C-PHY communication protocol; when the enable signal is a low level signal, the flexible circuit board adopts the D-PHY communication protocol.

[0027] In some embodiments of the present application, the step of adopting the C-PHY or D-PHY communication protocol of the flexible circuit board to match the pin rule according to the enable signal includes:

[0028] When the enable signal is a high level signal, the flexible circuit board adopts the D-PHY communication protocol; when the enable signal is a low level signal, the flexible circuit board adopts the C-PHY communication protocol.

[0029] In some embodiments of the present application, the communication protocol of the C-PHY is that multiple signal lines are respectively connected to multiple pins, every three adjacent signal lines constitute a signal channel, and the signal lines are used to transmit data signals; the communication protocol of the D-PHY is that multiple signal lines are respectively connected to multiple pins, every two adjacent signal lines constitute a signal channel, some of the signal channels are used to transmit data signals, and some of the signal channels are used to transmit clock signals.

[0030] In summary, due to the adoption of the above technical solution, this application has at least the following beneficial effects:

[0031] The embodiment of the present application provides a flexible circuit board and a driving method thereof, and a display device, by independently connecting each signal line on the flexible circuit board to different input pins and output pins, so that each signal line can selectively transmit data in a three-phase signal mode under the C-PHY transmission protocol or in a differential pair mode under the D-PHY transmission protocol according to an enable signal sent by a terminal mainboard in the display device, thereby realizing the switching of the two transmission protocols between the terminal mainboard and the display panel. In detail, by arranging a plurality of input pins, a plurality of output pins, and a plurality of signal lines on the board body, and making each signal line independently connected between an input pin and an output pin, each signal line can independently play the role of transmitting a signal or not transmitting a signal. When the terminal mainboard sends an enable signal, the multiple signal lines on the flexible circuit board can independently play their respective transmission functions according to the enable signal. For example, some input pins can play the role of transmitting data signals, and some signals can play the role of transmitting clock signals, thereby realizing the D-PHY transmission mode for signal transmission between the terminal mainboard and the display panel; if some or all signal lines play the role of transmitting data signals and all signal lines do not play the role of transmitting clock signals, then the C-PHY transmission mode can be used for signal transmission between the terminal mainboard and the display panel, and then the switching of the two transmission protocols can be realized, so that the display panel can be compatible with terminal mainboards with two transmission protocols. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a flexible circuit board provided with MIPI routing in an embodiment of the present application;

[0033] Figure 2 for Figure 1 A partial enlarged diagram of the MIPI routing in part A;

[0034] Figure 3 A schematic diagram of MIPI routing of a flexible circuit board provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of MIPI routing of another flexible circuit board provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of MIPI routing of another flexible circuit board provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of MIPI signal pin definition of a flexible circuit board provided in an embodiment of the present application;

[0038] Figure 7 for Figure 3An eye diagram simulation diagram of a flexible circuit board with D-PHY routing;

[0039] Figure 8 for Figure 3 An eye diagram simulation diagram of a flexible circuit board with C-PHY routing;

[0040] Fig. 9 for Figure 4 An eye diagram simulation diagram of a flexible circuit board with D-PHY routing;

[0041] Fig.10 for Figure 4 An eye diagram simulation diagram of a flexible circuit board with C-PHY routing;

[0042] Fig.11 for Figure 5 An eye diagram simulation diagram of a flexible circuit board with D-PHY routing;

[0043] Fig.12 for Figure 5 An eye diagram simulation diagram of a flexible circuit board with C-PHY routing;

[0044] Fig.13 An impedance control data diagram of a flexible circuit board provided in an embodiment of the present application;

[0045] Fig.14 A flowchart of a method for driving a flexible printed circuit board provided in an embodiment of the present application.

[0046] Description of reference numerals:

[0047] 10. Flexible circuit board; 11. Board body; 12. Signal line; 121. Meandering portion; 13. Main shielding line; 14. Secondary shielding line; 15. Input pin; 16. Output pin; 17. Signal transfer hole; 18. Ground wire transfer hole; 19. Ground layer. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0049] In the description of this application, it should be understood that the words "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0050] The present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or multiple times in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0051] The embodiment of the present application provides a display device, including: a terminal mainboard (not shown in the figure) and a display panel (not shown in the figure). Among them, the display panel includes a driver chip and a flexible circuit board 10. The driver chip is connected to the flexible circuit board 10, and the flexible circuit board 10 mainly plays a role in signal transmission. The terminal mainboard of the terminal mainboard is connected to the flexible circuit board 10 signal, and an enable signal is sent to the flexible circuit board 10. The flexible circuit board 10 transmits the signal sent by the terminal mainboard to the driver chip to drive the display panel to display the target picture.

[0052] In some embodiments, when the enable signal is at a high level, the flexible circuit board 10 adopts the D-PHY communication protocol, and when the enable signal is at a low level, the flexible circuit board 10 adopts the C-PHY communication protocol. By utilizing the routing structure of the physical layer of the flexible circuit board 10 and the signal conduction of the control layer, the display panel switches different transmission protocols for different terminal motherboards. In short, only one type of signal transmission interface of the display panel needs to be set, and different terminal motherboards can be connected to the signal transmission interface of the display panel. The display panel can perform the corresponding communication protocol routing of the flexible circuit board 10 according to the type of enable signal output by the terminal motherboard, so that the display panel can be compatible with terminal motherboards with different communication protocols.

[0053] It should be noted that, for the correspondence between the enable signal and the communication protocol, in addition to the method described in the above embodiment, the following correspondence may also be adopted:

[0054] When the enable signal is at a high level, the flexible circuit board 10 adopts the C-PHY communication protocol, and when the enable signal is at a low level, the flexible circuit board 10 adopts the D-PHY communication protocol. This is not limited in this embodiment.

[0055] In some embodiments, see Fig.14 The present application also provides a method for driving a flexible circuit board, comprising:

[0056] S1. Send an enable signal to the flexible circuit board.

[0057] In the display device, the terminal mainboard can control the selection of its transmission protocol by sending an enable signal (EnableSignal) to the flexible circuit board 10. The enable signal is usually a level signal (high level or low level) used to switch between C-PHY and D-PHY. For example:

[0058] When the enable signal is at a high level, the flexible circuit board 10 adopts the C-PHY communication protocol;

[0059] When the enable signal is at a low level, the flexible circuit board 10 adopts the communication protocol of D-PHY.

[0060] In this way, the system can automatically select the appropriate transmission protocol as needed without replacing the flexible circuit board 10. This dynamic selection method is not only highly adaptable, but also can save design and production costs.

[0061] S2. According to the enable signal, the flexible circuit board adopts the communication protocol of C-PHY or D-PHY to match the pin rule.

[0062] After receiving the enable signal, the flexible circuit board 10 will select the communication protocol of C-PHY or D-PHY according to the high or low level of the signal to match the pin rule of the DIC.

[0063] C-PHY communication protocol: Under the C-PHY protocol, each lane contains three signal lines 12, namely P, N and Z signals. These three signal lines 12 are connected to the driver chip according to the preset pin rules to form a three-phase transmission channel. It should be noted that the line spacing, line width and impedance of the three signal lines 12 need to meet the transmission requirements of C-PHY to ensure signal quality.

[0064] D-PHY communication protocol: Under the D-PHY protocol, each channel contains only two signal lines 12, which are positive and negative signals (usually marked as P and N), forming a differential pair. The differential pair can effectively suppress electromagnetic interference (EMI) and improve the signal's anti-interference ability. The D-PHY protocol also requires an additional clock signal line 12, so it is necessary to ensure the stability and anti-interference ability of the clock signal.

[0065] In this way, the flexible circuit board 10 can switch between C-PHY and D-PHY, thereby being compatible with different display module requirements.

[0066] It should be noted that C-PHY and D-PHY refer to two physical layer protocols in the MIPI standard. C-PHY adopts a three-phase transmission mode, and each channel consists of three signal lines 12 (P, N, Z), which can achieve a higher data transmission rate with the same number of pins. D-PHY is a differential signal transmission mode, and each channel uses two signal lines 12 (differential pair, positive and negative poles) for signal transmission. The enable signal is a control signal, usually in the form of a high level or a low level, which is used to indicate which transmission protocol the flexible circuit board 10 should adopt.

[0067] The driver IC (DIC) of the display panel is usually located in the display module, and the pins of the driver chip define the requirements for data input, such as the number of pins, the arrangement order of the signal lines 12, the requirements for the clock signal, etc. In this method, the pin rules of the driving signal are first preset to determine the specific communication protocol of the flexible circuit board 10.

[0068] For example, if the driver chip supports the C-PHY transmission protocol, the pin arrangement and signal requirements under the protocol need to be preset. The C-PHY protocol uses three signal lines 12 (usually marked as P, N and Z) for three-phase signal transmission, so it is necessary to ensure that each signal channel (lane) in the flexible circuit board 10 contains three signal lines 12 to match the input requirements of the driver chip. For the D-PHY protocol, the preset pin rules need to consider the requirements of differential signal pairs, each signal channel contains two signal lines 12 (positive and negative), and provides 12 clock signal lines.

[0069] In some embodiments, the step of using the C-PHY or D-PHY communication protocol of the flexible circuit board 10 to match the pin rule according to the enable signal includes:

[0070] When the enable signal is a high level signal, the flexible circuit board 10 adopts the C-PHY communication protocol; when the enable signal is a low level signal, the flexible circuit board 10 adopts the D-PHY communication protocol.

[0071] In some other embodiments, the step of using the C-PHY or D-PHY communication protocol of the flexible circuit board 10 to match the pin rule according to the enable signal includes:

[0072] When the enable signal is a high level signal, the flexible circuit board 10 adopts the D-PHY communication protocol; when the enable signal is a low level signal, the flexible circuit board 10 adopts the C-PHY communication protocol.

[0073] Whether it is the first embodiment or the second embodiment, the communication protocols of C-PHY and D-PHY are the same, and the only difference is the matching of the enable signal and the communication protocol. The communication protocol of C-PHY is that multiple signal lines 12 are respectively connected to multiple pins, and every three adjacent signal lines 12 constitute a signal channel, and the signal line 12 is used to transmit data signals; the communication protocol of D-PHY is that multiple signal lines 12 are respectively connected to multiple pins, and every two adjacent signal lines 12 constitute a signal channel, and some of the signal channels are used to transmit data signals, and some of the signal channels are used to transmit clock signals.

[0074] Specifically, every three adjacent signal lines 12 form a signal lane, and each lane consists of three signal lines 12, marked as P, N and Z, for transmitting three-phase signals. The three signal lines 12 transmit data in a three-phase encoding manner, and each signal line 12 is used to transmit a data signal (data signal) without the need for a dedicated clock line. The three-phase encoding method of C-PHY allows a higher data transmission rate to be achieved with the same number of pins, so it has advantages in high-frequency data transmission applications.

[0075] Every two adjacent signal lines 12 form a differential pair signal channel (lane), one of which is used to transmit a positive signal and the other is used to transmit a negative signal. This differential pair design can suppress common mode noise and improve anti-interference performance. In D-PHY mode, part of the signal channel is used to transmit data signals (data signals), and part of the signal channel is used to transmit clock signals to ensure the synchronization of data transmission.

[0076] To help understand the driving method of the flexible circuit board, the following is a detailed example. For details, please refer to Figure 6 .

[0077] Figure 6 The pin distribution can be divided into several categories: data pins, clock pins and ground pins, which are described as follows:

[0078] Data Pins:

[0079] Under the D-PHY protocol, data pins are configured in differential pair mode. For example, "D0+" and "D0-" constitute the first pair of data channels, and "D1+" and "D1-" constitute the second pair of data channels. Each pair of data pins transmits a set of differential signals, where one pin transmits a positive signal and the other pin transmits a negative signal. This configuration can effectively suppress external interference and maintain signal stability and integrity.

[0080] Under the C-PHY protocol, data pins are configured in a three-phase signal mode, for example, "P0", "N0", and "Z0" form a group of three-phase encoding channels. Each group of three signal lines 12 transmits signals of different phases, and the data bandwidth is increased by three-phase encoding, without the need for a separate clock signal line 12. The advantage of three-phase signal transmission in the C-PHY mode is that a higher data transmission rate can be achieved with the same number of pins.

[0081] Clock Pins:

[0082] Under the D-PHY protocol, the clock signal is transmitted through a pair of differential pins, namely "CLK+" and "CLK-". This pair of clock pins is used to synchronize the transmission speed of the data pins, so that the data receiving end can maintain the same timing as the sending end. This is a major difference between D-PHY and C-PHY. The D-PHY protocol relies on an external clock for data synchronization.

[0083] Under the C-PHY protocol, the clock signal is embedded in the data transmission, so there is no need for a separate clock pin. By combining clock information and data for transmission, the C-PHY protocol can reduce the number of pins, simplify the design, and improve transmission efficiency.

[0084] GND Pins:

[0085] Ground pins are used to provide a reference potential for electrical connections and are usually located near data pins and clock pins to reduce signal interference and improve noise immunity. Ground pins are usually inserted between adjacent signal pins to form a shield to further reduce interference. For example, a ground line may be laid near the D0+ and D0- data pairs to stabilize the signal.

[0086] In D-PHY mode: the signal lines 12 of the flexible circuit board 10 are configured in a differential pair manner. Every two adjacent signal lines 12 form a pair of transmission channels for transmitting data (such as "D0+" and "D0-" as a pair, transmitting positive and negative signals of the same data), and transmitting clock signals ("CLK+" and "CLK-") therein. This differential signal design can effectively suppress external electromagnetic interference, thereby improving the anti-interference ability of transmission.

[0087] In C-PHY mode: the signal lines 12 of the flexible circuit board 10 are configured according to the three-phase encoding method. Every three adjacent signal lines 12 form a three-phase encoding signal channel (such as "P0", "N0" and "Z0" form a channel) to transmit three-phase signals. Compared with the D-PHY mode, C-PHY does not require a separate clock signal. The clock information is embedded through the three-phase encoding technology, which reduces the demand for the number of pins and improves the transmission rate.

[0088] In practical applications, the MIPI pin configuration can allow the flexible circuit board 10 to support dual-mode communication of D-PHY and C-PHY. For example, the motherboard of a display device sends an enable signal to the flexible circuit board 10. When the flexible circuit board 10 receives a high level, the system switches to the D-PHY mode; when the flexible circuit board 10 receives a low level, the system switches to the C-PHY mode.

[0089] In the D-PHY mode, the flexible circuit board 10 uses differential signal pairs to transmit data and clock signals. Each signal channel is composed of a pair of signal lines 12, and all data pins (such as "D0+", "D0-", etc.) work in differential mode.

[0090] In C-PHY mode, the flexible circuit board 10 uses a three-phase signal mode to transmit data without a separate clock pin. The signal channel consists of three signal lines 12 (such as "P0", "N0", and "Z0"), and three-phase encoding technology is used to achieve efficient data transmission.

[0091] In some embodiments, see Figures 7 to 12 , perform eye diagram simulation on the flexible circuit board 10 to ensure that it can pass the eye diagram specifications at the preset CPHY and DPHY communication rates. The D-PHY transmission protocol requires that the eye height of the mask is not less than plus or minus 70mv, that is, the total height is at least 140mv, and the width needs to meet 0.3 times the inverse of the data rate. For C-PHY, the protocol requires that the eye height of the mask is plus or minus 40mv, that is, the total height is 80mv, and the width needs to meet 0.5 times the inverse of the data rate. The eye diagram refers to a graph drawn by superimposing multiple cycles of a digital signal. It is shaped like an "eye" and can intuitively reflect the quality of the signal, such as jitter, noise, and signal amplitude. Eye height refers to the height of the opening in the vertical direction of the eye diagram, which indicates the amplitude margin of the signal between the logic high level and the logic low level. A higher eye height indicates that the signal has a stronger ability to resist noise.

[0092] from Figure 7 It can be seen that the flexible circuit board adopts Figure 3 The MIPI routing method in the MCU and the D-PHY transmission protocol are adopted to pass the eye diagram specification at a rate of 1.5Gbps to meet the engineering design requirements. Specifically, Figure 7 The eye height in is 374mv. Figure 8 It can be seen that the flexible circuit board adopts Figure 3 The MIPI routing method in the MCU and the C-PHY transmission protocol are adopted to pass the eye diagram specifications at a rate of 1.2Gbps to meet the engineering design requirements. Figure 8The eye heights of the three signal lines of the three-phase differential signal are 136mv, 137mv, and 136mv from left to right, and the eye widths of the three signal lines of the three-phase differential signal are 690ps, 687ps, and 687ps from left to right. Fig. 9 It can be seen that the flexible circuit board adopts Figure 4 The MIPI routing method in the MCU and the D-PHY transmission protocol are adopted to pass the eye diagram specification at a rate of 1.5Gbps to meet the engineering design requirements. Specifically, Fig. 9 The eye height in is 355mv. Fig.10 It can be seen that the flexible circuit board adopts Figure 4 The MIPI routing method in the MCU and the C-PHY transmission protocol are adopted to pass the eye diagram specifications at a rate of 1.2Gbps to meet the engineering design requirements. Fig.10 The eye heights of the three signal lines of the three-phase differential signal are 141mv, 140mv and 139mv from left to right, and the eye widths of the three signal lines of the three-phase differential signal are 682ps, 679ps and 681ps from left to right. Fig.11 It can be seen that the flexible circuit board adopts Figure 5 The MIPI routing method in the MCU and the D-PHY transmission protocol are adopted to pass the eye diagram specification at a rate of 1.5Gbps to meet the engineering design requirements. Specifically, Fig.11 The eye height in is 355mv. Fig.12 It can be seen that the flexible circuit board adopts Figure 5 The MIPI routing method in the 3D 3D 3D MIPI Controller and the C-PHY transmission protocol are used to pass the eye diagram specification at a rate of 1.2Gbps, meeting the engineering design requirements. Specifically, Fig.12 The eye heights of the three signal lines of the three-phase differential signal are 140mv, 141mv and 140mv from left to right, and the eye widths of the three signal lines of the three-phase differential signal are 683ps, 680ps and 680ps from left to right.

[0093] See also Fig.13 During the production of the flexible circuit board 10, the single-ended impedance of C-PHY is controlled. When the single-ended impedance control is met, the line width and line spacing are adjusted to prepare multiple sets of flexible circuit board 10 samples. From the samples, the set with the D-PHY impedance that best meets the requirements is selected for production. Fig.13 As can be seen in the figure, the standard impedance is set to 100Ω. The standard impedance refers to the expected impedance target of the test. The maximum impedance is set to 110Ω and the minimum impedance is set to 90Ω. Five line width tests were conducted, and each line width was tested 5 times. All five line widths met the impedance target. The staff can select one of the line widths according to the actual situation. Fig.13In the embodiment, another standard setting is performed, that is, the standard impedance is set to 50Ω, the maximum impedance is set to 55Ω, and the minimum impedance is set to 45Ω. Five line width tests are performed, each line width is tested 10 times, and the five line widths all meet the impedance target. The staff can select one of the line widths according to the actual situation. In this embodiment, the flexible circuit board 10 can use the measured line width 5 for routing.

[0094] In some embodiments, see Figure 1 and Figure 2 .exist Figure 1 In the example, the multiple traces located at the corners of the flexible circuit board 10 are MIPI traces. Figure 2 It is a partial enlarged schematic diagram of the MIPI routing in the flexible circuit board 10. It can be seen from the figure that a main shielding line 13 and a secondary shielding line 14 are arranged between adjacent signal lines 12, the signal line 12 is located between two main shielding lines 13, and a secondary shielding line 14 is arranged between multiple adjacent signal lines 12 between the two main shielding lines 13. Both the main shielding line 13 and the secondary shielding line 14 are ground lines.

[0095] Exemplarily, the flexible circuit board 10 includes a board body 11, on which a plurality of signal lines 12, a main shielding line 13 and a secondary shielding line 14 are provided. The plurality of signal lines 12, the main shielding line 13 and the secondary shielding line 14 are all arranged near one side edge of the board body 11, and are routed along the shape of the edge contour of the board body 11. The number of the main shielding lines 13 is at least two, and the two main shielding lines 13 are arranged opposite to each other, and the plurality of signal lines 12 are arranged between the two main shielding lines 13 to play a shielding role. Every three adjacent signal lines 12 constitute a signal line 12 group to adapt to data transmission in a three-phase signal mode, and can also adapt to data transmission in a differential pair mode. A secondary shielding line 14 is arranged between two adjacent signal groups to also play a shielding role between adjacent signal groups.

[0096] In some embodiments, the board body 11 is composed of a multi-layer structure, which at least includes a MIPI routing layer and a ground layer 19. The MIPI routing layer is stacked above the ground layer 19, and the ground layer 19 is a whole surface layer to provide electrical shielding between the multi-layer structures. The MIPI routing layer includes a plurality of signal lines 12 and is provided with a plurality of signal transfer holes 17 and a plurality of ground transfer holes 18. The signal line 12 can be electrically connected to other layers through the signal transfer holes 17. If the signal line 12 needs to be electrically connected to the layer structure below the ground layer 19, a signal transfer hole 17 can also be provided on the ground layer 19 so that the signal line 12 can be transferred to the corresponding electrical layer below the ground layer 19 to achieve electrical connection between the MIPI routing layer and other electrical layers. A main shielding line 13 and a secondary shielding line 14 are also provided on the MIPI routing layer. The main shielding line 13 and the secondary shielding line 14 can be extended to other layers through the ground transfer hole 18 to provide multi-layer shielding.

[0097] Furthermore, the total lengths of adjacent signal lines 12 on the MIPI routing layer are the same to ensure consistency in signal transmission speed. In this embodiment, since some signal lines 12 are connected to different positions of the signal transfer holes 17, the lengths of the signal lines 12 located on the MIPI routing layer may be different. Exemplarily, the two ends of one of the signal lines 12 are respectively transferred to other layers through the signal transfer holes 17, and the two ends of a signal line 12 adjacent to the signal line 12 are also transferred to other layers through the signal transfer holes 17, and the distance between the signal transfer holes 17 transferred at the two ends of one signal line 12 is greater than the distance between the signal transfer holes 17 transferred at the two ends of another signal line 12. In order to ensure that the signal line 12 with a shorter distance between the signal transfer holes 17 at both ends is the same or similar in length to the other signal line 12, at least one winding portion 121 may be provided on the shorter signal line 12, so that the signal line 12 can extend the length of the signal line 12 for transmitting signals within the limited distance of the signal transfer holes 17 at both ends.

[0098] Furthermore, the end of the secondary shielding line 14 near the signal transfer hole 17 can be transferred to other layers through the ground transfer hole 18 to achieve multi-layer shielding. In addition, the shielding requirement of the signal line 12 near the signal transfer hole 17 is smaller than the shielding requirement far from the signal transfer hole 17. Therefore, in this embodiment, the width of the secondary shielding line 14 near the ground transfer hole 18 is gradually reduced to reduce the space of the board 11 occupied by the secondary shielding line 14.

[0099] To make the MIPI routing more clear, Figure 3 , Figure 4 , Figure 5 To simplify the three different routing diagrams after MIPI routing, Figures 3 to 5 The flexible circuit board 10 includes a board body 11 , a plurality of input pins 15 , a plurality of output pins 16 and a plurality of signal lines 12 .

[0100] Multiple input pins 15 and multiple output pins 16 are provided on the board 11. Multiple signal lines 12 are provided on the board 11, and both ends of each signal line 12 are respectively connected to an input pin 15 and an output pin 16, and the multiple signal lines 12 are suitable for transmitting data in a three-phase signal mode under the C-PHY transmission protocol and transmitting data in a differential pair mode under the D-PHY transmission protocol.

[0101] The technical solution provided in this embodiment is to independently connect each signal line 12 on the flexible circuit board 10 to different input pins 15 and output pins 16, so that each signal line 12 can selectively transmit data in a three-phase signal mode under the C-PHY transmission protocol or in a differential pair mode under the D-PHY transmission protocol according to the enable signal sent by the terminal mainboard in the display device, thereby realizing the switching of the two transmission protocols between the terminal mainboard and the display panel. In detail, by arranging a plurality of input pins 15, a plurality of output pins 16 and a plurality of signal lines 12 on the board body 11, and making each signal line 12 independently connected between an input pin 15 and an output pin 16, each signal line 12 can independently play the role of transmitting a signal or not transmitting a signal. When the terminal mainboard sends an enable signal, the multiple signal lines 12 on the flexible circuit board 10 can independently play their respective transmission functions according to the enable signal. For example, some input pins 15 can play the role of transmitting data signals, and some signals play the role of transmitting clock signals, thereby realizing the D-PHY transmission method for signal transmission between the terminal mainboard and the display panel; if some or all of the signal lines 12 play the role of transmitting data signals and all the signal lines 12 do not play the role of transmitting clock signals, then the C-PHY transmission method can be used for signal transmission between the terminal mainboard and the display panel, and then the switching of the two transmission protocols can be realized, so that the display panel can be compatible with the terminal mainboards of the two transmission protocols.

[0102] For the routing structure of the flexible circuit board 10, the specific working principle is as follows:

[0103] In C-PHY mode, the signal line 12 transmits data in a three-phase signal mode. This means that every three signal lines 12 form an independent signal channel to transmit data in a three-phase encoding manner. Specifically, the three signal lines 12 transmit three-phase signals with a phase difference of 120°, thereby avoiding the need for a separate clock signal line 12. In the implementation process, the flexible circuit board 10 is designed so that every three signal lines 12 form a channel to transmit three different phase signals (which can be called P, N, and Z). This three-phase encoding not only improves the data transmission rate, but also saves additional pin requirements.

[0104] In D-PHY mode, the signal line 12 transmits data in differential pair mode, that is, every two signal lines 12 form a pair of differential signal channels, one of which transmits a positive signal and the other transmits a negative signal. This differential transmission method can effectively suppress electromagnetic interference and improve the stability of signal transmission. In practical applications, every two signal lines 12 can be designed as a group of differential pairs, and each group of differential pairs is used to transmit single-channel data to ensure data integrity and anti-interference ability.

[0105] In a specific application, assuming that the flexible circuit board 10 needs to transmit high-definition image data to a display module, the design and operation can be performed according to the following steps:

[0106] Input pins 15 and output pins are set on the board body 11, and each pair of pins is connected through a signal line 12. Select C-PHY or D-PHY mode according to protocol requirements: If the C-PHY protocol is adopted, the signal line 12 is configured as a three-phase mode, so that every three signal lines 12 form a channel. If the D-PHY protocol is adopted, the signal line 12 is configured as a differential pair mode, so that every two signal lines 12 form a group for the transmission of positive and negative signals. The routing structure of the flexible circuit board 10 not only realizes dual-protocol compatibility, but also can be freely switched in different transmission modes, and has strong adaptability.

[0107] In some embodiments, the number of signal lines 12 is an even number, and under the C-PHY transmission protocol, at least one of the plurality of signal lines 12 does not transmit a signal, and the remaining signal lines 12 are used to transmit the data signal. By setting an even number of signal lines 12 and leaving one signal line 12 vacant, the transmission requirements of the C-PHY protocol can be met, and three-phase signal transmission can be effectively achieved without increasing the number of circuit board pins.

[0108] In C-PHY mode, since the protocol adopts three-phase encoding transmission, every three signal lines 12 form a channel to transmit three-phase signals. Therefore, the number of signal lines 12 involved in signal transmission needs to be based on multiples of 3, and the total number of even-numbered signal lines 12 is retained to adapt to the wiring design of the actual circuit board.

[0109] Specifically, assuming that there are 6 signal lines 12 on the circuit board, it can be configured as two three-phase channels, and each channel uses 3 signal lines 12 to transmit three-phase signals. However, in actual design, sometimes it is not necessary for all signal lines 12 to participate in signal transmission, so one or more of the signal lines 12 can be left vacant to reduce signal interference. Under the C-PHY protocol, in order to simplify the design of the circuit board and reduce possible electromagnetic interference, one of the even-numbered signal lines 12 can be selected not to transmit the signal. The purpose of this design is to reduce signal integrity issues that may be caused by electromagnetic interference without affecting data throughput. For example, if there are 8 signal lines 12 on the flexible circuit board 10, 6 signal lines 12 can be configured for C-PHY three-phase encoding transmission, and the remaining 2 signal lines 12 remain vacant. This layout ensures the integrity of the number of transmission channels and avoids the need for additional shielding measures.

[0110] In the design, the signal lines 12 that do not transmit signals can be arranged between the signal lines 12 that transmit signals to form a certain "interval area", which helps to reduce the electromagnetic coupling effect between the signal lines 12, thereby further reducing noise interference. For example, among the six signal lines 12, an empty signal line 12 can be left next to each group of three-phase signal channels to serve as a natural shielding layer.

[0111] In some embodiments, the number of signal lines 12 is an odd number, and under the D-PHY transmission protocol, at least two of the multiple signal lines 12 are used to transmit data signals, at least two are used to transmit clock signals, and at least one does not transmit signals. By configuring the odd number of signal lines 12, stable signal transmission can be achieved in the D-PHY differential pair mode. The vacant signal lines 12 can act as "isolation zones" here to reduce interference between other signal lines 12 and increase signal integrity.

[0112] Specifically, in the D-PHY mode, a differential pair transmission method is adopted, wherein at least two pairs of signal lines 12 are used to transmit data and clock signals respectively. To adapt to the characteristics of differential signals, the number of signal lines 12 is designed to be an odd number, so that some signal lines 12 can be flexibly configured to be vacant to avoid redundant signal interference.

[0113] For example, if there are 5 signal lines 12 on the flexible circuit board 10, 4 of them can be used as differential pairs, 2 for transmitting data signal pairs, 2 for transmitting clock signal pairs, and the remaining 1 signal line 12 remains vacant to isolate signal interference. In the D-PHY transmission protocol, differential pair signals are used to improve the signal's anti-interference ability. Two signal lines 12 are combined into a differential pair to transmit a group of signals. Therefore, at least 4 signal lines 12 are required, two for transmitting data and the other two for transmitting clock signals to ensure the synchronization of data and clock. Assuming that there are 7 signal lines 12 on the flexible circuit board 10, 4 signal lines 12 can be configured to transmit two differential pair data signals and two differential pair clock signals, and at least 1 of the remaining 3 signal lines 12 can be set not to transmit signals. Such a design can effectively reduce interference between signals. In the configuration of the signal line 12, at least one of the remaining odd-numbered signal lines 12 remains vacant to isolate other signals. Specifically, the idle signal line 12 may be placed between a data signal pair and a clock signal pair, or between any two differential pair signals, to reduce crosstalk between adjacent signal pairs.

[0114] It should be noted that the clock signal refers to the reference signal used to synchronize data transmission in digital circuits. The clock signal ensures that the data can be correctly interpreted at the receiving end to avoid data asynchrony or errors.

[0115] In some embodiments, see Figure 3The flexible circuit board 10 includes two main shielding lines 13, which are arranged on the board body 11, and a plurality of signal lines 12 are located between the two main shielding lines 13, and the main shielding lines 13 are grounded. The flexible circuit board 10 is provided with a main shielding line 13 on both sides of the distribution area of ​​the signal line 12 on the board body 11, and the main shielding line 13 extends parallel to the board body 11. All signal lines 12 are arranged between the two main shielding lines 13. The main shielding line 13 is grounded, which can provide a good shielding effect, thereby reducing the electromagnetic coupling between the signal line 12 and the external environment.

[0116] In some embodiments, see Figure 3 The flexible circuit board 10 further includes a plurality of secondary shielding lines 14, which are arranged on the board body 11, between two adjacent signal lines 12, and grounded. A secondary shielding line 14 is arranged between every two adjacent signal lines 12 on the flexible circuit board 10. The secondary shielding line 14 provides additional electromagnetic shielding by grounding, so that each signal line 12 can be fully shielded.

[0117] For example, if there are ten signal lines 12 on the flexible circuit board 10, nine secondary shielding lines 14 will be arranged between the ten signal lines 12. Each secondary shielding line 14 is connected to the ground to form a grounded shielding network. The main shielding line 13 is arranged on both sides of the signal line 12 area and is grounded to form an overall shield; and the secondary shielding line 14 further refines the shielding between each signal line 12. The coordinated work of the main and secondary shielding lines 14 divides the entire signal transmission area into multiple independent shielding channels. In high-speed signal transmission, each signal line 12 is separated from the adjacent signal line 12 by the grounded secondary shielding line 14, which not only reduces the crosstalk between adjacent signal lines 12, but also reduces the interference of external electromagnetic fields on signal transmission.

[0118] In some embodiments, see Figure 4 or Figure 5 , the distance between two adjacent signal lines 12 is not less than twice the line width of the signal line 12. Specifically, the distance between two adjacent signal lines 12 may be equal to twice the line width of the signal line 12, and the distance between two adjacent signal lines 12 may also be equal to three times the line width of the signal line 12, without limitation. For example, if the width of the signal line 12 is 0.2 mm, the minimum distance between adjacent signal lines 12 must be maintained at more than 0.4 mm. This spacing setting can prevent crosstalk between the signal lines 12 during high-frequency signal transmission, and can also reduce signal distortion caused by signal coupling.

[0119] In some embodiments, the flexible circuit board 10 further includes a plurality of secondary shielding lines 14, and three adjacent signal lines 12 constitute a signal channel, the signal channel is used to transmit a three-phase signal, and a secondary shielding line 14 is provided between adjacent signal channels. Specifically, the signal lines 12 on the flexible circuit board 10 are arranged in a group of three predetermined signal lines 12. Each group of three adjacent signal lines 12 constitutes an independent signal channel, which is suitable for three-phase signal transmission, such as the MIPI C-PHY protocol. Compared with the traditional differential signal transmission mode, the three-phase signal transmission mode can increase the data transmission rate and reduce the number of lines when transmitting high-frequency signals. For example, in the MIPI C-PHY protocol, the three-phase signal mode uses three signal lines 12 to transmit data of three state changes in each cycle, providing more data throughput than the traditional two-wire differential signal. The secondary shielding line 14 is arranged between adjacent signal channels, and the secondary shielding line 14 is grounded to effectively isolate the electromagnetic interference between the channels. A shielding layer is formed by the grounded secondary shielding line 14 to suppress electromagnetic radiation from adjacent signal channels.

[0120] It should be noted that in order to simplify the description of the embodiments of the present application and thus help understand one or more embodiments, in the above description of the embodiments of the present application, multiple features are sometimes merged into one embodiment, drawing or description thereof. However, this disclosure method does not mean that the features required by the object of the present application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

Claims

1. A flexible circuit board, characterized in that: include: plate body; A plurality of input pins and a plurality of output pins, wherein the plurality of input pins and the plurality of output pins are all arranged on the board; A plurality of signal lines are arranged on the board, and both ends of each of the signal lines are respectively connected to an input pin and an output pin. The plurality of signal lines transmit data in a three-phase signal mode under the C-PHY transmission protocol and transmit data in a differential pair mode under the D-PHY transmission protocol.

2. The flexible circuit board according to claim 1, characterized in that: The number of the signal lines is an even number, and under the C-PHY transmission protocol, at least one of the plurality of signal lines does not transmit a signal, and the remaining signal lines are used to transmit data signals.

3. The flexible circuit board according to claim 1, characterized in that: The number of the signal lines is an odd number, and under the D-PHY transmission protocol, at least two of the plurality of signal lines are used to transmit data signals, at least two are used to transmit clock signals, and at least one does not transmit signals.

4. The flexible circuit board according to any one of claims 1 to 3, characterized in that: The flexible circuit board comprises two main shielding lines, the main shielding lines are arranged on the board body, the plurality of signal lines are all located between the two main shielding lines, and the main shielding lines are grounded.

5. The flexible circuit board according to claim 4, characterized in that: The flexible circuit board also includes a plurality of secondary shielding lines, which are arranged on the board body, located between two adjacent signal lines, and grounded.

6. The flexible circuit board according to claim 4, characterized in that: The distance between two adjacent signal lines is not less than twice the line width of the signal lines.

7. The flexible circuit board according to claim 6, characterized in that: The flexible circuit board also includes a plurality of secondary shielding lines. Three adjacent signal lines form a signal channel. The signal channel is used to transmit three-phase signals. The secondary shielding lines are arranged between adjacent signal channels.

8. A display device, characterized in that: include: Terminal mainboard; A display panel, comprising a driving chip and a flexible circuit board according to any one of claims 1 to 7, wherein the driving chip is connected to the flexible circuit board; Wherein, the terminal mainboard is connected to the flexible circuit board and is used to send an enable signal to the flexible circuit board.

9. The display device according to claim 8, characterized in that When the enable signal is at a high level, the flexible circuit board adopts the D-PHY communication protocol, and when the enable signal is at a low level, the flexible circuit board adopts the C-PHY communication protocol; or, When the enable signal is at a high level, the flexible printed circuit board adopts the C-PHY communication protocol, and when the enable signal is at a low level, the flexible printed circuit board adopts the D-PHY communication protocol.

10. A method for driving a flexible circuit board, characterized in that: include: Sending an enable signal to the flexible circuit board; According to the enable signal, the flexible circuit board adopts the communication protocol of C-PHY or D-PHY to match the pin rule.

11. The driving method of the flexible printed circuit board according to claim 10, characterized in that: The step of the flexible circuit board using the C-PHY or D-PHY communication protocol to match the pin rule according to the enable signal includes: When the enable signal is a high level signal, the flexible circuit board adopts the C-PHY communication protocol; when the enable signal is a low level signal, the flexible circuit board adopts the D-PHY communication protocol.

12. The driving method of the flexible printed circuit board according to claim 10, characterized in that: The step of the flexible circuit board using the C-PHY or D-PHY communication protocol to match the pin rule according to the enable signal includes: When the enable signal is a high level signal, the flexible circuit board adopts the D-PHY communication protocol; when the enable signal is a low level signal, the flexible circuit board adopts the C-PHY communication protocol.

13. The driving method of the flexible printed circuit board according to claim 11 or 12, characterized in that: The communication protocol of the C-PHY is that multiple signal lines are respectively connected to multiple pins, every three adjacent signal lines constitute a signal channel, and the signal lines are used to transmit data signals; the communication protocol of the D-PHY is that multiple signal lines are respectively connected to multiple pins, every two adjacent signal lines constitute a signal channel, some of the signal channels are used to transmit data signals, and some of the signal channels are used to transmit clock signals.

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