Driving method and device of display panel, electronic device and storage medium

Abstract

The invention relates to a driving method and device of a display panel, an electronic device and a storage medium. The method comprises the following steps: controlling the display panel to perform display driving in a first mode; controlling the display panel to be switched from the first mode to a second mode for display driving; wherein the refresh frequency of the first mode is greater than that of the second mode; each display period of the first mode comprises at least one data writing frame; each display period of the second mode comprises at least one data writing frame and at least one data holding frame; the N data holding frames in the first display period in the second mode are located before the first data writing frame in the first display period in the second mode, and N is an integer larger than or equal to 1. Therefore, the brightness difference of the display panel can be reduced in the process of switching different refresh frequencies to perform display driving, so that the problem of flicker of the display panel is solved.

Description

Technical Field

[0001] The present disclosure relates to the field of display panels, and in particular to a display panel driving method and device, an electronic device, and a storage medium. Background Art

[0002] With the rapid development of technology today, the application scenarios of display panels are increasing. In different application scenarios, the display panel can be controlled to switch to different refresh frequencies for display driving. However, in the process of controlling the display panel to switch to different refresh frequencies for display driving, the brightness of the display panel will suddenly change, causing the display panel to flicker, which seriously affects the user experience. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a display panel driving method and device, an electronic device and a storage medium, so as to overcome the problem that when the display panel switches to different refresh frequencies for display driving, the brightness of the display panel changes suddenly, causing the display panel to flicker.

[0004] According to a first aspect of an embodiment of the present disclosure, a method for driving a display panel is provided, the method comprising:

[0005] Controlling the display panel to perform display driving in a first mode;

[0006] Control the display panel to switch from the first mode to the second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data write frame; each display cycle of the second mode includes at least one data write frame and at least one data hold frame; N data hold frames in the first display cycle of the second mode are located before the first data write frame in the first display cycle of the second mode, and N is an integer greater than or equal to 1.

[0007] In some embodiments, each display cycle of the first mode includes R1 data write frames and H1 data hold frames, and each display cycle of the second mode includes R2 data write frames and H2 data hold frames; wherein R1 / (R1+H1) is greater than R2 / (R2+H2), R1, R2, H2 are all integers greater than or equal to 1, and H1 is an integer greater than or equal to 0.

[0008] In some embodiments, N is less than H2.

[0009] In some embodiments, an arrangement of data writing frames and data holding frames in a first display period in the second mode is different from an arrangement of data writing frames and data holding frames in other display periods in the second mode.

[0010] In some embodiments, when R2 is 1, in the first display cycle of the second mode, one data write frame is located between H2 data hold frames, N data hold frames are located before the data write frame and (H2-N) data hold frames are located after the data write frame; in other display cycles of the second mode, one data write frame is located before the consecutively arranged H2 data hold frames.

[0011] In some embodiments, when R2 is 1, the number of sorting bits for writing data to the frame in the first display cycle in the second mode is (N+1), wherein the range of the number of sorting bits (N+1) is 1 / 3*(H2+1) to 2 / 3*(H2+1).

[0012] In some embodiments, the data write frames and the data hold frames are arranged in the same manner in each display cycle in the first mode; R1 consecutively arranged data write frames in each display cycle in the first mode are located before H1 consecutively arranged data hold frames.

[0013] In some embodiments, when H1 is 0, N data holding frames are spaced between the data writing frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode;

[0014] When H1 is greater than or equal to 1, N data holding frames are spaced between the last data holding frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode.

[0015] According to a second aspect of an embodiment of the present disclosure, there is provided a driving device for a display panel, the device comprising:

[0016] A first driving module, configured to control the display panel to perform display driving in a first mode;

[0017] A second driving module is configured to control the display panel to switch from the first mode to the second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data writing frame; each display cycle of the second mode includes at least one data writing frame and at least one data holding frame; N data holding frames in the first display cycle in the second mode are located before the first data writing frame in the first display cycle in the second mode, and N is an integer greater than or equal to 1.

[0018] In some embodiments, each display cycle of the first mode includes R1 data write frames and H1 data hold frames, and each display cycle of the second mode includes R2 data write frames and H2 data hold frames; wherein R1 / (R1+H1) is greater than R2 / (R2+H2), R1, R2, H2 are all integers greater than or equal to 1, and H1 is an integer greater than or equal to 0.

[0019] In some embodiments, N is less than H2.

[0020] In some embodiments, an arrangement of data writing frames and data holding frames in a first display period in the second mode is different from an arrangement of data writing frames and data holding frames in other display periods in the second mode.

[0021] In some embodiments, when R2 is 1, in the first display cycle of the second mode, one data write frame is located between H2 data hold frames, N data hold frames are located before the data write frame and (H2-N) data hold frames are located after the data write frame; in other display cycles of the second mode, one data write frame is located before the consecutively arranged H2 data hold frames.

[0022] In some embodiments, when R2 is 1, the number of sorting bits for writing data to the frame in the first display cycle in the second mode is (N+1), wherein the range of the number of sorting bits (N+1) is 1 / 3*(H2+1) to 2 / 3*(H2+1).

[0023] In some embodiments, the data write frames and the data hold frames are arranged in the same manner in each display cycle in the first mode; R1 consecutively arranged data write frames in each display cycle in the first mode are located before H1 consecutively arranged data hold frames.

[0024] In some embodiments, when H1 is 0, N data holding frames are spaced between the data writing frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode;

[0025] When H1 is greater than or equal to 1, N data holding frames are spaced between the last data holding frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode.

[0026] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, the device comprising:

[0027] processor;

[0028] a memory for storing processor-executable instructions;

[0029] Wherein, the processor is configured to: implement the steps in any one of the display panel driving methods in the first aspect when executed.

[0030] According to a fourth aspect of an embodiment of the present disclosure, a non-temporary computer-readable storage medium is provided. When instructions in the storage medium are executed by a processor in an electronic device, the electronic device can perform the steps in any method for driving a display panel in the first aspect.

[0031] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0032] In an embodiment of the present disclosure, the display panel is controlled to perform display driving in a first mode; the display panel is controlled to switch from the first mode to a second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data write frame; each display cycle of the second mode includes at least one data write frame and at least one data hold frame; N data hold frames in the first display cycle in the second mode are located before the first data write frame in the first display cycle in the second mode, and N is an integer greater than or equal to 1.

[0033] Through the embodiments of the present disclosure, when the display panel switches to different refresh frequencies for display driving, N data retention frames in the first display cycle in the second mode are located before the first data write frame in the first display cycle in the second mode. In this way, the display panel can be controlled to reduce the brightness difference of the display panel during the process of switching to different refresh frequencies for display driving, thereby improving the flickering problem of the display panel.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0036] Figure 1 is a characteristic curve diagram of the hysteresis effect of the thin film transistor of the pixel circuit;

[0037] Figure 2 It is a schematic diagram of brightness change of a display panel during the process of controlling the display panel to perform display driving at different refresh frequencies;

[0038] Figure 3is a schematic diagram of the brightness change of the display panel after adding the transition frame;

[0039] Figure 4 is a flow chart of a method for driving a display panel according to an exemplary embodiment;

[0040] Figure 5 is a schematic diagram of brightness change of a display panel shown in a related technical solution;

[0041] Figure 6 is a schematic diagram showing brightness change of a display panel according to an exemplary embodiment;

[0042] Figure 7 is a block diagram of a driving device for a display panel according to an exemplary embodiment;

[0043] Figure 8 is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0045] In different application scenarios, the display panel can be controlled to drive the display at different refresh frequencies. For presenting dynamic images, the display panel can be controlled to drive the display at a higher refresh frequency, and the display panel presents a better picture smoothness at this time; for static images, the display panel can be controlled to drive the display at a lower refresh frequency, and the power consumption of the display panel is lower at this time. In other words, controlling the display panel to switch different refresh frequencies for display driving can achieve a balance between picture smoothness and low power consumption. For example, the Low Temperature Polycrystalline Oxide (LTPO) screen can achieve adaptive refresh rates of 1Hz to 120Hz, and has become one of the main screens for current high-end mobile phone products.

[0046] In this article, "refresh rate" refers to the number of times the image is refreshed per unit time, measured in Hz. Generally, the higher the refresh rate, the shorter the refresh period. For example, if the refresh rate is 1Hz, then the refresh period is 1s; if the refresh rate is 120Hz, then the refresh period is (1 / 120)s, which is about 8.3ms.

[0047] However, when controlling the display panel to switch different refresh frequencies for display driving, due to the hysteresis effect of the thin film transistor (TFT) in the pixel circuit, the threshold voltage (Vth) shifts during the process of the thin film transistor switching from one working state to another, and the current driving the organic light-emitting diode (OLED) changes.

[0048] Exemplarily, the display panel may include a pixel circuit and a light-emitting element, the pixel circuit may include a driving transistor, and the light-emitting element may include a light-emitting diode; wherein the driving transistor may be used to provide a driving current to the light-emitting element to control the light-emitting element to emit light. Ions may be polarized inside the driving transistor, thereby forming a built-in electric field inside the driving transistor, causing the threshold voltage of the driving transistor to shift.

[0049] The "hysteresis effect" herein refers to the fact that a current variation curve when a voltage applied to a thin film transistor changes from low to high does not overlap with a current variation curve when a voltage applied to the thin film transistor changes from high to low.

[0050] Figure 1 It is a characteristic curve of the hysteresis effect of the thin film transistor of the pixel circuit. Figure 1 As shown, the horizontal axis is the voltage Vgs between the gate and the source, and the vertical axis is the current Ids between the source and the drain. Figure 1 The solid line in the middle shows the current change curve when the voltage applied to the thin film transistor changes from low to high, and the dotted line shows the current change curve when the voltage applied to the thin film transistor changes from high to low. The solid line and the dotted line do not overlap. Among them, for the same current value, the voltage V1 can be obtained according to the current change curve shown by the solid line, and the voltage V2 can be obtained according to the current change curve shown by the dotted line. The difference between the voltage V1 and the voltage V2 is ΔV. In other words, different current values ​​can be obtained for the same voltage value. In this way, the hysteresis effect affects the stability of the driving current provided by the driving transistor, and then affects the light-emitting stability of the light-emitting element.

[0051] Figure 2 Schematic diagram of the brightness change of the display panel during the process of controlling the display panel to display at different refresh frequencies. Figure 2As shown, the horizontal axis is time and the vertical axis is brightness. The display panel is controlled to be driven at a refresh rate of 120Hz, and the brightness of the display panel remains stable; the refresh rate is switched from 120Hz to 10Hz, and the display panel is controlled to be driven at a refresh rate of 10Hz, the brightness of the first frame with a refresh rate of 10Hz decreases, and the brightness of the second frame with a refresh rate of 10Hz remains stable. In other words, when the refresh rate is switched from 120Hz to 10Hz, the brightness of the display panel corresponding to the first frame with a refresh rate of 10Hz changes suddenly, causing the display panel to flicker, which seriously affects the user experience.

[0052] In the related technical solutions, the hysteresis characteristics of the thin film transistor can be improved by process optimization, thereby improving the problem of flickering of the display panel caused by sudden changes in the brightness of the display panel. However, the above process optimization solution is relatively complicated.

[0053] In the related technical solution, a transition frame can be inserted between switching refresh frequencies to reduce the refresh frequency difference between two adjacent frames, thereby improving the flicker problem of the display panel. Figure 2 As shown, in the process of switching the refresh rate from 120 Hz to 10 Hz, due to the large difference between the refresh rates, the change difference between two adjacent frames is large, which may cause the display panel to flicker.

[0054] For example, if the refresh frequency is directly switched from 120 Hz to 1 Hz, the frequency difference between two adjacent frames is 119 Hz. The change difference between the two adjacent frames is relatively large, which may cause flickering on the display panel. Figure 3 is a schematic diagram of the brightness change of the display panel after adding the transition frame. Figure 3 As shown, in the process of switching the refresh rate from 120 Hz to 1 Hz, a transition frame is inserted, that is, the refresh rate is switched from 120 Hz to 60 Hz, 20 Hz, 8 Hz, and finally to 1 Hz. In this way, the difference in refresh rate between any two adjacent frames is reduced, thereby improving the flickering problem of the display panel. However, the above method of inserting transition frames requires increased power consumption and is more complicated to set up.

[0055] In view of this, embodiments of the present disclosure provide a method and device for driving a display panel, an electronic device, and a storage medium.

[0056] Figure 4 FIG. 1 is a flow chart of a method for driving a display panel according to an exemplary embodiment. Figure 4 As shown, the method mainly includes the following steps:

[0057] In step 401, the display panel is controlled to perform display driving in a first mode;

[0058] In step 402, the display panel is controlled to switch from the first mode to the second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data write frame; each display cycle of the second mode includes at least one data write frame and at least one data hold frame; N data hold frames in the first display cycle in the second mode are located before the first data write frame in the first display cycle in the second mode, and N is an integer greater than or equal to 1.

[0059] In the embodiment of the present disclosure, the difference between the first mode and the second mode is that the refresh frequency is different. In other words, controlling the display panel to perform display driving in the first mode means controlling the display panel to perform display driving at the first refresh frequency, and controlling the display panel to perform display driving in the second mode means controlling the display panel to perform display driving at the second refresh frequency; wherein the first refresh frequency is greater than the second refresh frequency. In the driving method provided in the embodiment of the present disclosure, controlling the display panel to perform display driving at a higher refresh frequency switches to controlling the display panel to perform display driving at a lower refresh frequency.

[0060] In the disclosed embodiment, the display period in different modes is related to the refresh rate. In the first mode, the duration of the first display period is the reciprocal of the first refresh rate; in the second mode, the duration of the second display period is the reciprocal of the second refresh rate. In other words, the higher the refresh rate, the shorter the corresponding display period.

[0061] In a specific example, the first refresh frequency in the first mode is 120 Hz, and the corresponding first display period is (1 / 120) s; the second refresh frequency in the second mode is 10 Hz, and the corresponding second display period is (1 / 10) s.

[0062] In the embodiment of the present disclosure, the display cycle may include a data writing (Refresh) frame and a data holding (Holding) frame. As mentioned above, the display panel may include a driving transistor and a light-emitting element, and the driving transistor may be used to provide a driving current to the light-emitting element and control the light-emitting element to emit light. More specifically, the driving transistor has a data input terminal, a control terminal and a data output terminal, wherein the data input terminal is the source of the driving transistor, which is used to input a data signal to the driving transistor; the data output terminal is the drain of the driving transistor, which is used to connect the light-emitting element and provide a driving current to the light-emitting element; the control terminal is the gate of the driving transistor, which is used to control the driving transistor to be turned on or off. In the data writing frame, the source of the driving transistor can receive the data signal, and the driving transistor is turned on, and the driving transistor provides a driving current to the light-emitting element, thereby driving the display panel to display a picture. In the data holding frame, the source of the driving transistor does not receive the data signal, and the driving transistor does not provide a driving current to the light-emitting element, and the picture of the data writing frame will be maintained at this time.

[0063] Exemplarily, the maximum refresh frequency of the display panel is 120Hz, then the display cycle corresponding to 120Hz includes 1 data write frame. If the display panel needs to be switched to other refresh frequencies for display driving, the number of data write frames and data hold frames in the display cycle needs to be adjusted. The refresh frequency corresponding to the display cycle is the maximum refresh frequency * (number of data write frames / (number of data write frames + number of data hold frames)). When the number of data write frames in the display cycle remains at 1, if the display cycle includes 1 data write frame and 1 data hold frame, then the corresponding refresh frequency is 1 / 2 of the maximum refresh frequency, that is, 60Hz; if the display cycle includes 1 data write frame and 2 data hold frames, then the corresponding refresh frequency is 1 / 3 of the maximum refresh frequency, that is, 40Hz. Similarly, if the display cycle includes 1 data write frame and the number of data hold frames is 3, 4, 5, 7, 9, 11, 19, 23, 29, 39, 59 or 119, the corresponding refresh frequencies are 30Hz, 24Hz, 20Hz, 15Hz, 12Hz, 10Hz, 6Hz, 5Hz, 4Hz, 3Hz, 2Hz or 1Hz respectively.

[0064] Of course, more diverse refresh frequencies can also be achieved by adjusting the number of data write frames in the display cycle. When the number of data hold frames in the display cycle remains at 1, if the display cycle includes 2 data write frames and 1 data hold frame, the corresponding refresh frequency is 2 / 3 of the maximum refresh frequency, that is, 80 Hz; if the display cycle includes 3 data write frames and 1 data hold frame, the corresponding refresh frequency is 3 / 4 of the maximum refresh frequency, that is, 90 Hz.

[0065] Here, in the display cycle, the data writing frame is located before the data holding frame, and all the data writing frames are arranged continuously, and all the data holding frames are arranged continuously. For example, in the display cycle corresponding to 40 Hz, after 1 data writing frame, 2 data holding frames are arranged continuously. For example, in the display cycle corresponding to 90 Hz, before 1 data writing frame, 3 data writing frames are arranged continuously.

[0066] In the embodiment of the present disclosure, the display panel is driven by switching from the first mode to the second mode, that is, switching from the first refresh frequency to the second refresh frequency, and the last display cycle in the first mode and the first display cycle in the second mode are two adjacent display cycles. N data holding frames in the first display cycle in the second mode are located before the first data writing frame in the first display cycle in the second mode, and N is an integer greater than or equal to 1.

[0067] In some embodiments, each display cycle in the first mode may include 1 data writing frame and does not include a data holding frame, and in this case, the data writing frame in the last display cycle in the first mode and the first data holding frame in the first display cycle in the second mode are adjacently arranged. In other words, the data writing frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode are not adjacently arranged; or, the data writing frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode are separated by N data holding frames; or, the N data holding frames in the first display cycle in the second mode are located before the first data writing frame in the first display cycle in the second mode.

[0068] In some embodiments, each display cycle in the first mode may include 1 data writing frame and at least 1 data holding frame, and the last data holding frame in the last display cycle in the first mode and the first data holding frame in the first display cycle in the second mode are adjacently arranged. In other words, the last data holding frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode are not adjacently arranged; or, the last data holding frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode are spaced by N data holding frames; or, the N data holding frames in the first display cycle in the second mode are located before the first data writing frame in the first display cycle in the second mode.

[0069] Figure 51 is a schematic diagram of the brightness change of the display panel shown in the related technical solution. Take the first refresh frequency of the first mode as 120Hz and the second refresh frequency of the second mode as 10Hz as an example for explanation. At this time, 120Hz is a high frequency and 10Hz is a low frequency. Figure 5 As shown, the horizontal axis is time and the vertical axis is brightness. Figure 5 Three display cycles of the first mode are illustrated. Each display cycle of the first mode includes one data writing frame and does not include a data holding frame. Figure 5 The three display cycles of the second mode are also illustrated. The arrangement of the data write frame and the data hold frame in each display cycle of the second mode is the same, that is, each display cycle of the second mode includes 1 data write frame and 11 data hold frames, and after 1 data write frame, 11 data hold frames are arranged continuously.

[0070] Reference Figure 5 , control the display panel to switch from high frequency to low frequency for display driving, and the data writing frame in the last display cycle in the first mode and the data writing frame in the first display cycle in the second mode are set adjacently. The threshold voltage compensation of the pixel circuit is collected in real time. When the threshold voltage compensation is performed on the first data writing frame in the first display cycle of low frequency, the threshold voltage compensation at the previous moment will be used, that is, the threshold voltage compensation for the first data writing frame in the first display cycle of low frequency will use the threshold voltage compensation of the last display cycle of high frequency, resulting in a sudden change in the brightness of the first display cycle of low frequency, causing flickering of the display panel. The brightness will remain stable until the second display cycle of low frequency. Figure 5 It is shown that the difference between the brightness of the last display period in the first mode and the minimum brightness of the first display period in the second mode is ΔL1.

[0071] Figure 6 FIG. 1 is a schematic diagram showing the brightness change of a display panel according to an exemplary embodiment. Taking the first refresh frequency of the first mode as 120 Hz and the second refresh frequency of the second mode as 10 Hz as an example, 120 Hz is a high frequency and 10 Hz is a low frequency. Figure 6 As shown, the horizontal axis is time and the vertical axis is brightness. Figure 6 Three display cycles of the first mode are illustrated. Each display cycle of the first mode includes one data writing frame and does not include a data holding frame. Figure 6The three display cycles of the second mode are also illustrated. The arrangement of the data writing frame and the data holding frame in the first display cycle of the second mode is different from the arrangement of the data writing frame and the data holding frame in other display cycles of the second mode. Each display cycle in the second mode includes 1 data writing frame and 11 data holding frames. In the first display cycle of the second mode, 1 data writing frame is located between the 11 data holding frames, that is, in the first display cycle of the second mode, 3 data holding frames are located before 1 data writing frame and 8 data holding frames are located after 1 data writing frame; in other display cycles of the second mode, 1 data writing frame is located before the 11 data holding frames arranged continuously.

[0072] Reference Figure 6 , control the display panel to switch from high frequency to low frequency for display driving, the data write frame in the last display cycle in the first mode and the first data write frame in the first display cycle in the second mode are not set adjacently, that is, the data write frame in the last display cycle in the first mode and the first data write frame in the first display cycle in the second mode are separated by 3 data hold frames, wherein the 3 data hold frames all belong to the first display cycle in the second mode. In other words, the 3 data hold frames in the first display cycle in the second mode are located before the first data write frame in the first display cycle in the second mode. Since there are already 3 data hold frames separated, there is a certain buffer time, and when the threshold voltage compensation is performed on the first data write frame in the first display cycle at low frequency, the threshold voltage compensation in the low-frequency state can be used, so that the flicker problem of the display panel can be improved. Figure 6 It is shown that the difference between the brightness of the last display period in the first mode and the minimum brightness of the first display period in the second mode is ΔL2. Figure 6 The brightness difference ΔL2 shown is less than Figure 5 The brightness difference ΔL1 is shown; the human eye can feel the flicker of the display panel when observing the brightness difference ΔL1, but cannot feel the flicker of the display panel when observing the brightness difference ΔL2. Therefore, by reducing the difference between the brightness of the last display cycle in the first mode and the minimum brightness of the first display cycle in the second mode, the flicker problem of the display panel can be effectively improved.

[0073] In the disclosed embodiment, the display panel is controlled to switch from a high-frequency first mode to a low-frequency second mode for display driving, and N data holding frames in the first display cycle in the second mode are located before the first data writing frame in the first display cycle in the second mode. In this way, the display panel can be controlled to adjust the driving timing in the process of switching different refresh frequencies for display driving, so as to effectively reduce the brightness difference of the display panel, thereby improving the flicker problem of the display panel.

[0074] In some embodiments, N is less than the number of data holding frames included in the display cycle in the second mode. That is, at least one data holding frame in the first display cycle in the second mode is located before the first data writing frame in the first display cycle in the second mode; and at least one data holding frame in the first display cycle in the second mode is located after the first data writing frame in the first display cycle in the second mode.

[0075] In some embodiments, each display cycle of the first mode includes R1 data write frames and H1 data hold frames, and each display cycle of the second mode includes R2 data write frames and H2 data hold frames; wherein R1 / (R1+H1) is greater than R2 / (R2+H2), R1, R2, H2 are all integers greater than or equal to 1, and H1 is an integer greater than or equal to 0.

[0076] Here, the refresh frequency of the first mode (ie, the first refresh frequency) is greater than the refresh frequency of the second mode (ie, the second refresh frequency).

[0077] The driving method of the display panel provided in the embodiment of the present disclosure can be used in the application scenario of switching from high frequency to low frequency. It should be noted that in the embodiment of the present disclosure, high frequency and low frequency are relative concepts, which are used to illustrate the relative magnitude relationship between the two frequencies. The embodiment of the present disclosure does not specifically limit the specific values ​​of the first refresh frequency (i.e., high frequency) and the second refresh frequency (i.e., low frequency).

[0078] In some embodiments, the data write frames and the data hold frames are arranged in the same manner in each display cycle in the first mode; R1 consecutively arranged data write frames in each display cycle in the first mode are located before H1 consecutively arranged data hold frames.

[0079] Here, in each display period in the first mode, the data writing frame is located before the data holding frame, and all the data writing frames are arranged continuously, and all the data holding frames are arranged continuously.

[0080] Reference Figure 6 As shown, the refresh frequency of the first mode is 120 Hz, and each display period in the first mode includes one data writing frame and does not include a data holding frame.

[0081] In some embodiments, when H1 is 0, N data holding frames are spaced between the data writing frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode;

[0082] When H1 is greater than or equal to 1, N data holding frames are spaced between the last data holding frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode.

[0083] Here, the last display cycle in the first mode and the first display cycle in the second mode are adjacently arranged. The last frame in the last display cycle in the first mode can be either a data write frame or a data hold frame. This depends on the refresh frequency corresponding to the display cycle in the first mode. In the case where each display cycle in the first mode includes only a data write frame and does not include a data hold frame, of course, the data write frame in the last display cycle in the first mode and the first data hold frame in the first display cycle in the second mode are adjacently arranged, more specifically, the data write frame in the last display cycle in the first mode and the first data write frame in the first display cycle in the second mode are spaced by N data hold frames. In the case where each display cycle in the first mode includes a data write frame and a data hold frame, of course, the last data hold frame in the last display cycle in the first mode and the first data hold frame in the first display cycle in the second mode are adjacently arranged, more specifically, the last data hold frame in the last display cycle in the first mode and the first data write frame in the first display cycle in the second mode are spaced by N data hold frames.

[0084] Figure 5 and Figure 6 The example only illustrates the situation that each display period in the first mode only includes a data writing frame but does not include a data holding frame, which does not constitute a limitation on the protection scope of the present disclosure.

[0085] In some embodiments, an arrangement of data writing frames and data holding frames in a first display period in the second mode is different from an arrangement of data writing frames and data holding frames in other display periods in the second mode.

[0086] Here, during the process of switching from the first mode to the second mode, the brightness of the first display cycle of the second mode may flicker until the brightness of the second display cycle of the second mode remains stable. Therefore, it is necessary to adjust the arrangement of the data writing frame and the data holding frame in the first display cycle of the second mode to improve the flickering problem of the display panel during the process of switching from the first mode to the second mode.

[0087] Specifically, the arrangement of the data writing frame and the data holding frame in the first display cycle in the second mode is adjusted, and the first data writing frame in the first display cycle in the second mode is delayed, that is, the data writing frame in the first display cycle in the second mode is moved backward along the time axis. There is no need to adjust the arrangement of the data writing frame and the data holding frame in other display cycles in the second mode, that is, the data writing frame is located before the data holding frame, and all the data writing frames are arranged continuously, and all the data holding frames are arranged continuously.

[0088] In some embodiments, when R2 is 1, in the first display cycle of the second mode, one data write frame is located between H2 data hold frames, N data hold frames are located before the data write frame and (H2-N) data hold frames are located after the data write frame; in other display cycles of the second mode, one data write frame is located before the consecutively arranged H2 data hold frames.

[0089] Here, when the number of data writing frames in the display cycle in the second mode is 1, 1 data writing frame in the first display cycle in the second mode needs to be moved backward along the time axis, and at this time 1 data writing frame in the first display cycle in the second mode is located between H2 data holding frames, more specifically, N data holding frames are located before 1 data writing frame and (H2-N) data holding frames are located after 1 data writing frame. The positions of data writing frames in other display cycles in the second mode do not need to be adjusted, and at this time 1 data writing frame in other display cycles in the second mode is located before H2 data holding frames arranged continuously.

[0090] In some embodiments, when R2 is 1, the number of sorting bits for writing data to the frame in the first display cycle in the second mode is (N+1), wherein the range of the number of sorting bits (N+1) is 1 / 3*(H2+1) to 2 / 3*(H2+1).

[0091] Here, the number of data write frames in the display cycle in the second mode is 1, and the data write frame can be moved backward and inserted between the H2 data holding frames arranged continuously. It should be noted that the number of sorting bits of the data write frame in the first display cycle in the second mode mainly needs to consider two aspects comprehensively. On the one hand, as the N value increases, the buffer time between frequency switching becomes longer, and the probability of using the threshold voltage compensation in the low-frequency state when performing threshold voltage compensation on the data write frame is higher, which is conducive to improving the flicker problem of the display panel; on the other hand, as the N value increases, the number of data holding frames between the last frame of the last display cycle in the first mode (that is, the data write frame or the data holding frame) and the first data write frame in the first display cycle in the second mode increases, and the brightness of the display panel will gradually decrease, which is not conducive to improving the flicker problem of the display panel. Therefore, considering the impact of the above two aspects on the flicker problem of the display panel, the range of the sorting bit number (N+1) is set to 1 / 3*(H2+1) to 2 / 3*(H2+1).

[0092] In a specific example, the number R2 of data write frames in each display cycle in the second mode is 1, the number H2 of data hold frames is 11, and the number of sorting bits of data write frames in the first display cycle in the second mode ranges from 4 to 8.

[0093] Figure 7 FIG. 1 is a block diagram of a driving device for a display panel according to an exemplary embodiment. Figure 7 As shown, the device 700 mainly includes:

[0094] A first driving module 701 is configured to control the display panel to perform display driving in a first mode;

[0095] The second driving module 702 is configured to control the display panel to switch from the first mode to the second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data write frame; each display cycle of the second mode includes at least one data write frame and at least one data hold frame; N data hold frames in the first display cycle in the second mode are located before the first data write frame in the first display cycle in the second mode, and N is an integer greater than or equal to 1.

[0096] In some embodiments, each display cycle of the first mode includes R1 data write frames and H1 data hold frames, and each display cycle of the second mode includes R2 data write frames and H2 data hold frames; wherein R1 / (R1+H1) is greater than R2 / (R2+H2), R1, R2, H2 are all integers greater than or equal to 1, and H1 is an integer greater than or equal to 0.

[0097] In some embodiments, N is less than H2.

[0098] In some embodiments, an arrangement of data writing frames and data holding frames in a first display period in the second mode is different from an arrangement of data writing frames and data holding frames in other display periods in the second mode.

[0099] In some embodiments, when R2 is 1, in the first display cycle of the second mode, one data write frame is located between H2 data hold frames, N data hold frames are located before the data write frame and (H2-N) data hold frames are located after the data write frame; in other display cycles of the second mode, one data write frame is located before the consecutively arranged H2 data hold frames.

[0100] In some embodiments, when R2 is 1, the number of sorting bits for writing data to the frame in the first display cycle in the second mode is (N+1), wherein the range of the number of sorting bits (N+1) is 1 / 3*(H2+1) to 2 / 3*(H2+1).

[0101] In some embodiments, the data write frames and the data hold frames are arranged in the same manner in each display cycle in the first mode; R1 consecutively arranged data write frames in each display cycle in the first mode are located before H1 consecutively arranged data hold frames.

[0102] In some embodiments, when H1 is 0, N data holding frames are spaced between the data writing frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode;

[0103] When H1 is greater than or equal to 1, N data holding frames are spaced between the last data holding frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode.

[0104] Figure 8800 is a block diagram of an electronic device according to an exemplary embodiment. For example, the device 800 may be a mobile phone, a tablet computer, a computer, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, a wearable device (such as a smart watch, a smart bracelet, a smart ring, etc.), etc.

[0105] Reference Figure 8 , the device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0106] The processing component 802 generally controls the overall operation of the device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0107] The memory 804 is configured to store various types of data to support operations on the device 800. Examples of such data include instructions for any application or method operating on the device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0108] The power supply component 806 provides power to the various components of the device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device 800.

[0109] The multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0110] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the device 800 is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0111] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0112] The sensor assembly 814 includes one or more sensors for providing various aspects of the status assessment of the device 800. For example, the sensor assembly 814 can detect the open / closed state of the device 800, the relative positioning of components, such as the display and keypad of the device 800, and the sensor assembly 814 can also detect the position change of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, the orientation or acceleration / deceleration of the device 800, and the temperature change of the device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0113] The communication component 816 is configured to facilitate wired or wireless communication between the device 800 and other devices. The device 800 can access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0114] In an exemplary embodiment, the apparatus 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above method.

[0115] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by a processor 820 of the device 800 to complete the above-mentioned display panel driving method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0116] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor in an electronic device, enables the electronic device to perform a method for driving a display panel, the method comprising:

[0117] Controlling the display panel to perform display driving in a first mode;

[0118] Control the display panel to switch from the first mode to the second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data write frame; each display cycle of the second mode includes at least one data write frame and at least one data hold frame; N data hold frames in the first display cycle of the second mode are located before the first data write frame in the first display cycle of the second mode, and N is an integer greater than or equal to 1.

[0119] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0120] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for driving a display panel, characterized in that: The method comprises: Controlling the display panel to perform display driving in a first mode; Control the display panel to switch from the first mode to the second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data write frame; each display cycle of the second mode includes at least one data write frame and at least one data hold frame; N data hold frames in the first display cycle of the second mode are located before the first data write frame in the first display cycle of the second mode, and N is an integer greater than or equal to 1.

2. The driving method according to claim 1, characterized in that: Each display period of the first mode includes R1 data writing frames and H1 data holding frames, and each display period of the second mode includes R2 data writing frames and H2 data holding frames; wherein R1 / (R1+H1) is greater than R2 / (R2+H2), R1, R2, H2 are all integers greater than or equal to 1, and H1 is an integer greater than or equal to 0.

3. The driving method according to claim 2, characterized in that: N is smaller than H2.

4. The driving method according to claim 2, characterized in that: The arrangement of the data writing frame and the data holding frame in the first display period in the second mode is different from the arrangement of the data writing frame and the data holding frame in other display periods in the second mode.

5. The driving method according to claim 2, characterized in that: When R2 is 1, in the first display cycle of the second mode, one data write frame is located between H2 data hold frames, N data hold frames are located before the data write frame and (H2-N) data hold frames are located after the data write frame; in other display cycles of the second mode, one data write frame is located before the consecutively arranged H2 data hold frames.

6. The driving method according to claim 2, characterized in that: When R2 is 1, the number of sorting bits for data write frames in the first display cycle in the second mode is (N+1), wherein the range of the number of sorting bits (N+1) is 1 / 3*(H2+1) to 2 / 3*(H2+1).

7. The driving method according to claim 2, characterized in that: The data writing frames and the data holding frames are arranged in the same manner in each display period in the first mode; R1 data writing frames arranged continuously in each display period in the first mode are located before H1 data holding frames arranged continuously.

8. The driving method according to claim 2, characterized in that: When H1 is 0, N data holding frames are spaced between the data writing frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode; When H1 is greater than or equal to 1, N data holding frames are spaced between the last data holding frame in the last display cycle in the first mode and the first data writing frame in the first display cycle in the second mode.

9. A driving device for a display panel, characterized in that: The device comprises: A first driving module, configured to control the display panel to perform display driving in a first mode; A second driving module is configured to control the display panel to switch from the first mode to the second mode for display driving; wherein the refresh frequency of the first mode is greater than the refresh frequency of the second mode; each display cycle of the first mode includes at least one data write frame; each display cycle of the second mode includes at least one data write frame and at least one data hold frame; N data hold frames in the first display cycle in the second mode are located before the first data write frame in the first display cycle in the second mode, and N is an integer greater than or equal to 1.

10. An electronic device, characterized in that: The device comprises: processor; a memory for storing processor-executable instructions; The processor is configured to: implement the steps in the method for driving a display panel as claimed in any one of claims 1 to 8 when executed.

11. A non-transitory computer-readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor in an electronic device, the electronic device is enabled to execute the steps in the method for driving a display panel as claimed in any one of claims 1 to 8.

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