Pixel circuit, driving method thereof and display panel

Abstract

The invention discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving transistor which is an N-type transistor; the first end of the first write-in module is electrically connected with a data voltage end, and the second end is electrically connected with the grid of the driving transistor; the first end of the second write-in module is electrically connected with the first reference voltage end, and the second end is electrically connected with the grid electrode of the driving transistor; the first end of the compensation module and the gate of the driving transistor are electrically connected to a first node, and the second end and the first pole of the driving transistor are electrically connected to a second node; a first pole plate of the first capacitor is electrically connected with the first node, and a second pole plate and a second pole of the driving transistor are electrically connected to a third node; a first pole plate of the second capacitor is electrically connected with the third node, and a second pole plate is electrically connected with a first power supply voltage end; the first light emitting control module is electrically connected between the light emitting element and the second node; and the second light-emitting control module is electrically connected with the third node. By adopting the scheme, the problems of ghost shadow and splash screen can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display panel. Background Art

[0002] Organic light-emitting display is the mainstream technology for displays in mobile phones, televisions, computers, etc. Compared with traditional liquid crystal displays, organic light-emitting display has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed.

[0003] Organic light-emitting displays are driven by current and require a stable driving current to control their light emission. The magnitude and stability of the driving current of organic light-emitting displays mainly depend on the magnitude and stability of the gate-source voltage and threshold voltage of the driving transistor in the pixel circuit.

[0004] However, due to the hysteresis effect of the driving transistor, the threshold voltage may drift, resulting in unstable driving current, which may easily cause afterimage or screen flickering. Summary of the invention

[0005] The present invention provides a pixel circuit and a driving method thereof, and a display panel, so as to improve the afterimage and screen flickering problems caused by the hysteresis of the driving transistor.

[0006] According to one aspect of the present invention, there is provided a pixel circuit, comprising: a driving transistor, a light emitting element, a first writing module, a second writing module, a compensation module, a first capacitor, a second capacitor, a first light emitting control module and a second light emitting control module;

[0007] A first end of the first writing module is electrically connected to the data voltage end, and a second end of the first writing module is electrically connected to the gate of the driving transistor;

[0008] A first terminal of the second writing module is electrically connected to the first reference voltage terminal, and a second terminal of the second writing module is electrically connected to the gate of the driving transistor;

[0009] The first end of the compensation module is electrically connected to the gate of the driving transistor at a first node, and the second end of the compensation module is electrically connected to the first electrode of the driving transistor at a second node;

[0010] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor and the second electrode of the driving transistor are electrically connected to the third node;

[0011] The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first power supply voltage terminal;

[0012] The first light emitting control module is electrically connected between the light emitting element and the second node; the second light emitting control module is electrically connected to the third node;

[0013] The driving transistor is an N-type transistor.

[0014] According to another aspect of the present invention, a driving method of a pixel circuit is provided, for driving the above-mentioned pixel circuit; the driving method comprises:

[0015] In the initialization stage, the first reference voltage terminal is connected to the first node;

[0016] In the threshold compensation stage, the first reference voltage terminal is connected to the first node, and the first node is connected to the second node;

[0017] In the writing stage, the data voltage terminal is connected to the first node;

[0018] In the light emitting stage, the light emitting element is conductively connected to the third node, and the third node is conductively connected to the third power supply voltage terminal.

[0019] According to yet another aspect of the present invention, there is provided a display panel comprising: a plurality of the above pixel circuits arranged in an array.

[0020] The technical solution of the present invention sets the driving transistor as an N-type transistor so that the carriers in the driving transistor are electrons, which have higher mobility and lower threshold voltage sensitivity, thereby improving the hysteresis and threshold voltage drift of the driving transistor; at the same time, a light-emitting element is also set to be electrically connected to the first electrode of the driving transistor through a first light-emitting control module, which is beneficial to reducing the voltage fluctuation of the second electrode of the driving transistor, further improving the hysteresis and threshold voltage drift of the driving transistor, so that when the pixel circuit is applied to a display panel, it is beneficial to improve the problems of afterimage and low-frequency flicker of the display panel.

[0021] In addition, by setting a second writing module for receiving data signals to be electrically connected to the gate of the driving transistor, and the compensation module to be connected between the gate and the first electrode of the driving transistor, the threshold compensation stage and the writing stage can be separated, so that the threshold voltage compensation process has sufficient time, which is beneficial to improve the charging rate during the threshold voltage compensation process, so that the threshold voltage can be fully compensated to the third node. Even if the pixel circuit is in a fixed gray scale for a long time or the refresh frequency is low, the threshold voltage is offset, and the compensation module can fully compensate the threshold voltage to the third node, thereby improving the luminous accuracy and improving the problems of afterimage and low grayscale flicker. At the same time, a first capacitor and a second capacitor are also set, and the size of the driving current can be adjusted by the first capacitor and the second capacitor, so as to realize the regulation of the range of the data signal, which is beneficial to reduce the voltage drop of the gate of the driving transistor, further improve the hysteresis and threshold voltage drift of the driving transistor, and improve the display quality.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a circuit structure schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention;

[0026] Figure 3 is a timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0027] Figure 4 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of refreshing a pixel circuit provided by an embodiment of the present invention;

[0029] Figure 6 is a timing diagram of a display panel provided by an embodiment of the present invention;

[0030] Figure 7 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0031] Figure 8 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0032] Fig. 9 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0033] Fig.10 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0034] Fig.11 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0035] Fig.12 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0036] Fig.13 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0037] Fig.14 Schematic diagram of the circuit structure of another pixel circuit provided by an embodiment of the present invention

[0038] Fig.15 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention;

[0039] Fig.16 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0040] Fig.17 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0041] Fig.18 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0042] Fig.19 is a timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0043] Fig. 20 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present invention;

[0044] Fig.21 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0045] Fig. 22 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] Figure 1 is a circuit structure diagram of a pixel circuit provided by an embodiment of the present invention. Figure 1 The pixel circuit 10 includes a driving transistor M3, a light-emitting element OLED, a first writing module 11, a second writing module 12, a compensation module 13, a first capacitor C1, a second capacitor C2, a first light-emitting control module 14 and a second light-emitting control module 15, wherein the driving transistor M3 is an N-type transistor.

[0049] The first end of the first writing module 11 is electrically connected to the data voltage terminal, and the second end of the first writing module 11 is electrically connected to the gate of the driving transistor M3. The first end of the second writing module 12 is electrically connected to the first reference voltage terminal, and the second end of the second writing module 12 is also electrically connected to the gate of the driving transistor M3. The first end of the compensation module 13 is electrically connected to the gate of the driving transistor M3 at the first node N1, and the second end of the compensation module 13 is electrically connected to the first electrode of the driving transistor M3 at the second node N2. The first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate C2 of the first capacitor C1 is electrically connected to the second electrode of the driving transistor M3 at the third node N3. The first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate of the second capacitor C2 is electrically connected to the first power supply voltage terminal. The first light emitting control module 14 is electrically connected between the light emitting element OLED and the second node N2, and the second light emitting control module 15 is electrically connected to the third node N3.

[0050] Specifically, the first end of the first writing module 11 can be electrically connected to the data voltage end through the data line Data_L, and receive the data signal Data at the data voltage end; when the first writing module 11 is turned on, the data signal Data can be transmitted to the gate of the driving transistor M3 through the first writing module 11. The first end of the second writing module 12 can be electrically connected to the first reference voltage end through the first reference line VREF1_L, and receive the first reference signal VREF1 at the first reference voltage end; when the second writing module 12 is turned on, the first reference signal VREF1 can be transmitted to the gate of the driving transistor M3 through the second writing module 12. The second plate of the second capacitor C2 can be electrically connected to the first power supply voltage end through the first power supply line PV1_L, and receive the first power supply signal PV1 at the first power supply voltage end.

[0051] In addition, the control end of the first writing module 11 can be electrically connected to the first scanning line SP_L to receive the first scanning signal SP; the level of the first scanning signal SP can control the conduction and cutoff of the first writing module 11. The control end of the second writing module 12 can be electrically connected to the second scanning line S1N_L to receive the second scanning signal S1N; the level of the second scanning signal S1N can control the conduction and cutoff of the second writing module 12. The control end of the compensation module 13 can be electrically connected to the third scanning line S2N_L to receive the third scanning signal S2N; the level of the third scanning signal S2N can control the conduction and cutoff of the compensation module 13. The control end of the first light control module 14 can be electrically connected to the first light control line EM1_L to receive the first light control signal EM1; the level of the first light control signal EM1 can control the conduction and cutoff of the first light control module 14. The control end of the second light control module 15 can be electrically connected to the second light control line EM2_L to receive the second light control signal EM2; the level of the second light control signal EM2 can control the conduction and cutoff of the second light control module 15.

[0052] Exemplarily, the pixel circuit 10 may be applied to a display panel. Figure 2 is a schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention. Figure 2The display area AA of the display panel 01 may be provided with a plurality of pixel circuits 10 arranged in an array, a plurality of first scan lines SP_L, a plurality of second scan lines S1N_L, a plurality of third scan lines S2N_L, a plurality of first light emission control lines EM1_L, and a plurality of second light emission control lines EM2_L. The non-display area NA of the display panel 01 may be provided with a first driving circuit 20, and the first driving circuit 20 includes a first shift register VSR1, a second shift register VSR2, a third shift register VSR3, a fourth shift register VSR4, and a fifth shift register VSR5. The first shift register VSR1, the second shift register VSR2, the third shift register VSR3, the fourth shift register VSR4, and the fifth shift register VSR5 each include a plurality of cascaded shift register units.

[0053] refer to Figure 1 and Figure 2 , the first shift register VSR1 can output a first scan signal SP that is shifted sequentially, and at least one shift register unit of the first shift register VSR1 can be electrically connected to a first scan line SP_L, and the first scan line SP_L can be electrically connected to the control end of the first write module 11 of the pixel circuit 10. The second shift register VSR2 can output a second scan signal S1N that is shifted sequentially, and at least one shift register unit of the second shift register VSR2 can be electrically connected to a second scan line S1N_L, and the second scan line S1N_L can be electrically connected to the control end of the second write module 12 of the pixel circuit 10. The third shift register VSR3 can output a third scan signal S2N that is shifted sequentially, and at least one shift register unit of the third shift register VSR3 can be electrically connected to a third scan line S2N_L, and the third scan line S2N_L can be electrically connected to the control end of the compensation module 13 of the pixel circuit 10.

[0054] The fourth shift register VSR4 can output the first light control signal EM1 that is shifted sequentially, and at least one shift register unit of the fourth shift register VSR4 can be electrically connected to a first light control line EM1_L, and the first light control line EM1_L can be electrically connected to the control end of the first light control module 14 of the pixel circuit 10. The fifth shift register VSR5 can output the second light control signal EM2 that is shifted sequentially, and at least one shift register unit of the fifth shift register VSR5 can be electrically connected to a second light control line EM2_L, and the second light control line EM2_L can be electrically connected to the control end of the second light control module 15 of the pixel circuit 10.

[0055] The display area AA of the display panel 01 may further be provided with a plurality of data lines Data_L, and the non-display area NA may further be provided with a second driving circuit 30. The second driving circuit 30 includes a plurality of data voltage terminals Do, and the data voltage terminal Do may be electrically connected to at least one data line Data_L, and the data line Data_L may be electrically connected to the first terminal of the first writing module 11 of the pixel circuit 10.

[0056] In addition, the display area AA of the display panel 01 may further be provided with a plurality of first reference lines VREF1_L, a plurality of first power lines PV1_L, a plurality of second power lines PV2_L, and a plurality of third power lines PV3_L ( Figure 2 The display panel 01 may further include a first reference voltage terminal, a first power supply voltage terminal, a second power supply voltage terminal and a third power supply voltage terminal ( Figure 2 1_L, which may be electrically connected to the second plate of the second capacitor C2. The second power supply voltage terminal is used to provide a second power signal PV2 to the second power line PV2_L, which may be electrically connected to the light emitting element OLED. The third power supply voltage terminal is used to provide a third power signal PV3 to the third power line PV3_L, which may be electrically connected to the second light emitting control module 15.

[0057] It should be noted that the figure only exemplarily shows that the shift register unit in the shift register is electrically connected to only one scan line or one light-emitting control line, and the data voltage terminal is electrically connected to only one data line. In other embodiments, at least part of the shift register units in the shift register may be electrically connected to multiple scan lines or multiple light-emitting control lines, and the data voltage terminal may be electrically connected to multiple data lines via a gate switch ( Figure 2 are not shown).

[0058] It should also be noted that the figure only shows that the first shift register is located on both sides of the display area, and the second shift register, the third shift register, the fourth shift register and the fifth shift register are only located on one side of the display area. The embodiment of the present invention does not limit the setting position of the shift register. In an optional implementation, the second shift register, the third shift register, the fourth shift register and the fifth shift register may also be located on both sides of the display area. In another optional implementation, at least part of the shift registers may also be set in the display area.

[0059] The working principle of the pixel circuit provided in the embodiment of the present application is described below in conjunction with the timing.

[0060] For example, Figure 3 is a timing diagram of a pixel circuit provided by an embodiment of the present invention, Figure 3 Specific support Figure 1 The driving timing of the pixel circuit shown in the figure, wherein the second end of the first writing module 11 and the second end of the second writing module 12 can be directly electrically connected to the gate of the driving transistor M3 at the first node N1, that is, no device or element is set between the second end of the first writing module 11 and the gate of the driving transistor M3, and between the second end of the second writing module 12 and the gate of the driving transistor M3, but conductive structures such as metal wires, overlapping holes, and overlapping electrodes (used to achieve electrical connection between overlapping holes to avoid overlapping holes being too deep and reduce the difficulty of preparation) can be used. Figure 1 ) electrical connections.

[0061] like Figure 3 As shown, the working period of the pixel circuit 10 includes multiple refresh phases tf, and each refresh phase tf includes an initialization phase t1, a threshold compensation phase t2, a writing phase t3, and a light-emitting phase t4. For ease of understanding, this embodiment is described with a high level as an enable level and a low level as a non-enable level; in other implementations, each module can also have a low level as an enable level and a high level as a non-enable level. It should be noted that the enable level referred to here is the potential for controlling the conduction between the first end and the second end of each module, and the non-enable level is the potential for controlling the cutoff and disconnection between the first end and the second end of each module.

[0062] refer to Figure 1-Figure 3 In the initialization stage t1, the first light emitting control signal EM1 on the first light emitting control line EM1_L and the second light emitting control signal EM2 on the second light emitting control line EM2_L both jump to the non-enable level. The first light emitting control module 14 can be turned off under the control of the first light emitting control signal EM1, and the second light emitting control module 15 can be turned off under the control of the second light emitting control signal EM2, so that the connection between the light emitting element OLED and the driving transistor M3, and the connection between the driving transistor M3 and the third power supply voltage terminal are disconnected, and the pixel circuit 10 stops providing the driving current to the light emitting element OLED.

[0063] After the first light-emitting control signal EM1 and the second light-emitting control signal EM2 both jump to the non-enable level, the second scan signal S1N on the second scan line S1N_L can jump to the enable level. The second write module 12 can be turned on under the control of the second scan signal S1N, so that the first reference voltage terminal and the first node N1 are connected, and the first reference signal VREF1 on the first reference line VREF1_L can be transmitted to the first node N1 through the second write module 12, and the signal of the first node N1 is initialized to the first reference signal VREF1, that is, the voltage VN1 of the first node N1=VREF1.

[0064] In the threshold compensation stage t2, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 continue to be at the non-enable level, the second scan signal S1N continues to be at the enable level, and the third scan signal S2N on the third scan line S2N_L jumps to the enable level. The compensation module 13 can be turned on under the control of the third scan signal S2N, so that the first node N1 and the second node N2 are connected, and the signal of the first node N1 can be transmitted to the second node N2 through the compensation module 13. At this time, the voltage VN2 of the second node N2=VN1=VREF1. At the beginning of the threshold compensation stage t2, the compensation module 13 and the driving transistor M3 can be in the on state at the same time, the signals of the first node N1 and the second node N2 are the same, and the difference between the voltage VN1 of the first node N1 and the voltage VN3 of the third node N3 can be greater than the threshold voltage VTH of the driving transistor M3, that is, VN1=VN2>VN3+VTH, the gate-source voltage VGS of the driving transistor M3=VN1-VN3>VTH, the signal of the first node N1 can be transmitted to the third node N3 through the compensation module 13 and the driving transistor M3, and the gate-source voltage VGS of the driving transistor M3 is continuously reduced until VGS=VN1-VN3=VTH, the driving transistor M3 is in a transition state of on and off, the current in the driving transistor M3 is reduced to zero, the signal of the first node N1 is no longer transmitted to the third node N3, and the voltage of the third node N3 is stable. At this time, VN3=VN1-VTH=VREF1-VTH, and the threshold voltage is compensated to the third node N3.

[0065] In the writing stage t3, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 continue to be at the non-enable level, and the second scanning signal S1N and the third scanning signal S2N both jump to the non-enable level. The second writing module 12 can be cut off under the control of the second scanning signal S1N, so that the first reference voltage terminal and the first node N1 are cut off, and the first reference signal VREF1 on the first reference line VREF1_L stops transmitting to the first node N1. The compensation module 13 can be cut off under the control of the third scanning signal S2N, so that the first node N1 and the second node N2 are cut off, and the second node N2 and the third node N3 no longer receive the signal of the first node N1, and the voltage of the second node N2 and the third node N3 can maintain the voltage of the previous moment.

[0066] After the second scan signal S1N and the third scan signal S2N both jump to the non-enable level, the first scan signal SP on the first scan line SP_L jumps to the enable level. The first write module 11 can be turned on under the control of the first scan signal SP, so that the data voltage terminal Do is connected to the first node N1, and the data signal Data on the data line Data_L can be transmitted to the first node N1 through the first write module 11, and the signal of the first node N1 is written as the data signal Data, that is, the voltage VN1 of the first node N1 =Data. The first power signal PV1 on the first power line PV1_L connected to the second plate of the second capacitor C2 can be a fixed signal, and the second node N2 and the third node N3 stop receiving the signal of the first node N1. Through the first capacitor C1 and the second capacitor C2, the voltage change △VN1(t3) of the first node N1 can be partially coupled to the third node N3, △VN3(t3)=△VN1(t3)*C1 / (C1+C2), and at this time, the voltage VN3 of the third node N3=VREF1-VTH+△VN1(t3)*C1 / (C1+C2)=VREF1-VTH+(Data-VREF1)*C1 / (C1+C2).

[0067] In the light emitting stage t4, the second scanning signal S1N and the third scanning signal S2N continue to be at the non-enable level, and the first scanning signal SP jumps to the non-enable level. The first writing module 11 can be cut off under the control of the first scanning signal SP, so that the data voltage terminal Do is cut off from the first node N1, the data signal Data on the data line Data_L stops being transmitted to the first node N1, the first node N1 stops receiving the data signal Data, and the voltage of the first node N1 can maintain the voltage at the previous moment.

[0068] After the first scanning signal SP jumps to the non-enable level, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 both jump to the enable level. The first light-emitting control module 14 can be turned on under the control of the first light-emitting control signal EM1, so that the light-emitting element OLED is connected to the second node N2, and the driving transistor M3 is connected to the light-emitting element OLED. The second light-emitting control module 15 can be turned on under the control of the second light-emitting control signal EM2, so that the third node N3 is connected to the third power supply voltage terminal, and the third power supply signal PV3 on the third power line PV3_L can be transmitted to the third node N3 through the second light-emitting control module 15, and the voltage VN3 of the third node N3 = PV3, and the voltage VN3 of the third node N3 changes, and the change amount is △VN3(t4) = PV3-[VREF1-VTH+(Data-VREF1)*C1 / (C1+C2)]. The first node N1 stops receiving signals, and the voltage change △VN3(t4) of the third node N3 can be coupled to the first node N1 through the first capacitor C1, △VN1(t4)=△VN3(t4)=PV3-[VREF1-VTH+(Data-VREF1)*C1 / (C1+C2)], at this time, the voltage VN1 of the first node N1=Data+△VN1(t4)=Data+PV3-[VREF1-VTH+(Data-VREF1)*C1 / (C1+C2)].

[0069] The gate-source voltage of the driving transistor M3 is VGS=VN1-VN3=Data+PV3-[VREF1-VTH+(Data-VREF1)*C1 / (C1+C2)]-PV3=(Data-VREF1)*C2 / (C1+C2)+VTH. The driving current Id provided by the pixel circuit 10 to the light emitting element OLED is k*(VGS-VTH) 2 =k*[(Data-VREF1)*C2 / (C1+C2)] 2 , the light emitting element OLED can receive the driving current Id and display the corresponding brightness according to the driving current Id. By controlling the brightness and light emission duration of the light emitting element OLED, the display grayscale of the pixel circuit 10 can be controlled. Wherein, k is the current coefficient of the driving transistor M3, which is related to the material properties and size parameters of the driving transistor M3.

[0070] In an optional embodiment, continue to refer to Figure 1-Figure 3 , the first light emitting control signal EM1 and the second light emitting control signal EM2 can be switched to the non-enable level at the same time, and can be switched to the enable level at the same time.

[0071] Exemplarily, the control end of the first light emitting control module 14 and the control end of the second light emitting control module 15 can be electrically connected. The control end of the first light emitting control module 14 and the control end of the second light emitting control module 15 of the same pixel circuit 10 can be connected to the same light emitting control line ( Figure 2 ), receiving the same light-emitting control signal as the first light-emitting control signal EM1 and the second light-emitting control signal EM2; or, the control end of the first light-emitting control module 14 and the control end of the second light-emitting control module 15 of the same pixel circuit 10 can also be connected to different light-emitting control lines, but the shift register units ( Figure 2 ), receiving the same light emitting control signal as the first light emitting control signal EM1 and the second light emitting control signal EM2.

[0072] In this way, the first light-emitting control module 14 and the second light-emitting control module 15 of the same pixel circuit 10 can be turned on or off at the same time under the control of the same light-emitting control signal. When adjusting the light-emitting duration of the light-emitting element OLED of the pixel circuit 10, only one light-emitting control signal needs to be adjusted, which is beneficial to simplify the dimming process and dimming timing; in addition, it is also beneficial to reduce the number of shift registers in the display panel 01, thereby realizing the thinness of the display panel 01.

[0073] In another optional embodiment, in the same refresh phase tf, after the second scan signal S1N jumps to the non-enable level, the third scan signal S2N jumps to the non-enable level. In this way, the duration of the second writing module 12 and the compensation module 13 being turned on at the same time can be increased as much as possible. When the second writing module 12 and the compensation module 13 are turned on at the same time, the first reference signal VREF1 can be transmitted to the third node N3 through the second writing module 12, the compensation module 13 and the driving transistor M3, which is conducive to increasing the duration of compensating the threshold voltage of the driving transistor M3 to the third node N3 and improving the charging rate.

[0074] In another optional embodiment, the third shift register VSR3 includes M-stage shift register units, the second scan line S1N_L electrically connected to the same pixel circuit 10 can be electrically connected to the i-th stage shift register unit of the third shift register VSR3, the third scan line S2N_L can be electrically connected to the j-th stage shift register unit of the third shift register VSR3, and the i-th signal output by the third shift register VSR3 is received as the second scan signal S1N, and the j-th signal output by the third shift register VSR3 is received as the second scan signal S1N. is the third scanning signal S2N, wherein 1≤i≤j≤M, and i and j are both integers; in other words, the second scanning line S1N_L electrically connected to the j-th row of pixel circuits 10 and the third scanning line S2N_L electrically connected to the i-th row of pixel circuits 10 can be electrically connected and electrically connected to the output end of the same shift register unit of the third shift register VSR3, and the second scanning line S1N_L and the third scanning line S2N_L electrically connected to the same row of pixel circuits 10 can be electrically connected to different shift register units of the third shift register VSR3 ( Figure 2 In this way, the second scanning signal S2N and the third scanning signal S2N received by the pixel circuit 10 may both come from the third shift register VSR3, and the second shift register VSR2 may not be provided, which is conducive to the thinness of the display panel 01.

[0075] Based on the above embodiments, Figure 4 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Figure 4 Specific support Figure 1 The driving timing of the pixel circuit shown in FIG. Figure 4 As shown, the working period of the pixel circuit 10 also includes a plurality of display cycles DP, and the display cycle DP includes a refresh phase tf and a hold phase tk. For ease of understanding, this embodiment continues to be described with a high level as the enable level and a low level as the disable level.

[0076] Figure 4 Zhongyu Figure 3The similarities will not be repeated here, and only the differences will be described. In the holding stage tk, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 may be at the enable level at least in part of the time period, but the first scan signal SP, the second scan signal S1N and the third scan signal S2N are all at the non-enable level. Under the control of the first scan signal SP, the second scan signal S1N and the third scan signal S2N, the first write module 11, the second write module 12 and the compensation module 13 electrically connected to the first node N1 are all turned off, so that the first node N1 does not write a new signal, and the voltage of the first node N1 can remain unchanged. Under the control of the first light-emitting control signal EM1 and the second light-emitting control signal EM2, the first light-emitting control module 14 and the second light-emitting control module 15 can be turned on, so that the light-emitting element OLED continues to emit light, and the light-emitting brightness remains unchanged. In an optional embodiment, in the holding stage tk, the duration that the first light-emitting control module 14 and the second light-emitting control module 15 are simultaneously at the enable level is the first light-emitting duration; in the refresh stage tf, the duration that the first light-emitting control module 14 and the second light-emitting control module 15 are simultaneously at the enable level is the second light-emitting duration; the first light-emitting duration and the second light-emitting duration may be the same, so that the display grayscale of the pixel circuit 10 in the refresh stage tf and the holding stage tk is the same. In another optional embodiment, the first light-emitting duration and the second light-emitting duration may also be different, so that the display grayscale of the pixel circuit 10 in the refresh stage tf and the holding stage tk is different, so as to adjust the brightness of the display panel.

[0077] The display period DP refers to the refresh period of the display grayscale of the pixel circuit 10. In the refresh phase tf of the display period DP, the gate of the driving transistor M3 can be written with the data signal data, and the driving current Id can be adjusted by the data signal data to refresh the display grayscale; in the holding phase tk of the display period DP, the gate of the driving transistor M3 is no longer written with the data signal data, the driving current Id remains unchanged, and the display grayscale is not refreshed. In other optional embodiments, the display period DP may also include only the refresh phase tf, but not the holding phase tk.

[0078] Exemplarily, the duration of the refresh phase tf and the hold phase tk may both be 1 / 120 s, and 120 refresh phases tf and / or hold phases tk may be included within 1 s. The display period DP of the pixel circuit 10 may include one refresh phase tf and 0, 1, 3 or 119 hold phases tk, so that the refresh frequency of the pixel circuit 10 may be 120 Hz, 60 Hz, 30 Hz or 1 Hz, as shown in FIG. Figure 5When the pixel circuit 10 is in a fixed gray scale for a long time or the refresh frequency is low, the gate, the first electrode and the second electrode of the driving transistor M3 are in a fixed potential for a long time, and the driving transistor M3 may be delayed, resulting in a threshold voltage drift. The pixel circuit 10 provided by the embodiment of the present invention can compensate for the drifted threshold voltage in the threshold compensation stage t2 of the refresh stage tf of the next display cycle DP to improve the problems of afterimage and low-frequency flicker.

[0079] It can be understood that when the duration of the refresh phase tf and the hold phase tk are both 1 / 120s, the refresh frequency of the pixel circuit 10 can also be 40Hz, 24Hz, 20Hz, 15Hz, 12Hz, 10Hz, 8Hz, 6Hz, 4Hz, 3Hz, 2Hz, etc., which are no longer shown one by one in the embodiments of the present invention.

[0080] It can also be understood that in other optional implementations, the duration of the refresh phase tf and the hold phase tk can also be other values. In this case, the refresh frequency of the pixel circuit 10 can also be other frequencies, which will not be described one by one in the embodiments of the present invention.

[0081] For example, it is assumed that the display period DP of all pixel circuits 10 in the display panel 01 includes a refresh phase tf and a hold phase tk, and the refresh frequencies of all pixel circuits 10 are the same. Figure 6 is a timing diagram of a display panel provided by an embodiment of the present invention. Figure 6 , the display panel 01 includes a first display mode, in which the display panel 01 includes a refresh frame DAf and a hold frame DAk. The display panel 01 may also include M rows of pixel circuits 10. In the refresh frame DAF, each row of pixel circuits 10 may be initialized, threshold compensated, and written with a data signal Data, so that the display grayscale of each row of pixel circuits 10 is refreshed in sequence; in the hold frame DAk, each row of pixels 10 stops initialization, stops threshold compensation, and stops writing the data signal data, so that the display grayscale of each row of pixel circuits 10 is not refreshed, and the display grayscale of the previous frame can continue to be displayed, so as to achieve full-screen frequency reduction of the display panel 01.

[0082] In other embodiments, the display period DP of some pixel circuits 10 in the display panel 01 may include only the refresh phase tf, the display period DP of some pixel circuits 10 may include the refresh phase tf and the hold phase tk, and the refresh frequencies of the pixel circuits 10 in the same display panel 01 may be different. The display panel 01 may also include a second display mode. In the second display mode, the display panel 01 may include a refresh frame DAf and a frequency division frame ( Figure 6(not shown in the figure), in the frequency division frame, some rows of pixel circuits 10 can refresh the display grayscale, and some rows of pixel circuits 10 may not refresh the display grayscale, so as to realize the division and frequency division of the display panel 01.

[0083] The pixel circuit provided by the embodiment of the present invention sets the driving transistor as an N-type transistor so that the carriers in the driving transistor are electrons, which have higher mobility and lower threshold voltage sensitivity, and can improve the hysteresis and threshold voltage drift of the driving transistor; at the same time, a light-emitting element is also set to be electrically connected to the first electrode of the driving transistor through a first light-emitting control module, which is conducive to reducing the voltage fluctuation of the second electrode of the driving transistor, further improving the hysteresis and threshold voltage drift of the driving transistor, so that when the pixel circuit is applied to a display panel, it is conducive to improving the problems of afterimage and low-frequency flicker of the display panel. In an optional embodiment, the first electrode of the driving transistor can be a drain electrode, and the second electrode can be a source electrode, so that the light-emitting element is connected to the drain end of the driving transistor, which can separate the light-emitting element from the source electrode of the driving transistor, which is conducive to reducing the fluctuation of the source voltage of the driving transistor, thereby improving the effect of improving hysteresis and threshold voltage drift, and further improving the problems of afterimage and low-frequency flicker.

[0084] In addition, by setting a second writing module that receives a data signal to be electrically connected to the gate of the driving transistor, and the compensation module to be connected between the gate and the drain of the driving transistor, the threshold compensation stage and the writing stage can be separated, so that there is sufficient time for the threshold voltage compensation process, which is beneficial to improving the charging rate during the threshold voltage compensation process, thereby fully compensating the threshold voltage to the third node. Even if the pixel circuit is in a fixed gray scale for a long time or the refresh frequency is low, the threshold voltage is offset, and the compensation module can fully compensate the threshold voltage to the third node, thereby improving the luminescence accuracy and improving the problems of afterimage and low grayscale flicker. At the same time, a first capacitor and a second capacitor are also provided, and the size of the driving current can be adjusted by the first capacitor and the second capacitor, thereby realizing the regulation of the range of the data signal, which is beneficial to reducing the voltage drop of the gate of the driving transistor, further improving the hysteresis and threshold voltage drift of the driving transistor, and improving the display quality.

[0085] Optional, Figure 7 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention. Figure 7 The first writing module 11 includes a first writing transistor M2, the second writing module 12 includes a second writing transistor M5, the compensation module 13 includes a compensation transistor M4, the first light-emitting control module 14 includes a first light-emitting control transistor M1, and the second light-emitting control module 15 includes a second light-emitting control transistor M6; the first writing transistor M2, the second writing transistor M5, the compensation transistor M4, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are all N-type transistors.

[0086] Exemplarily, all transistors in the pixel circuit 10 are N-type transistors, and the active layers of all transistors in the pixel circuit 10 can be set on the same layer, reducing the preparation process and reducing the preparation cost; and the enable levels of the gates of all transistors are high levels, and when the pulse widths of the enable levels are the same, signal multiplexing between different transistors can also be performed.

[0087] Optionally, the active layer of the driving transistor M3 includes a metal oxide material.

[0088] The metal oxide material may include one or more oxide materials of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti) and zinc (Zn). In this way, when preparing the active layer of the driving transistor M3, it is not necessary to crystallize to form a crystal structure, so that the defect density of the active layer is small, and the carrier mobility of the active layer is high and the temperature sensitivity is low, so that the voltage stability and switching characteristics of the driving transistor M3 are better, and the hysteresis effect and threshold voltage drift can be further reduced.

[0089] In an optional embodiment, the active layers of all transistors in the pixel circuit 10 may include one or more oxide materials of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti) and zinc (Zn), for example, they may all include indium gallium zinc oxide (IGZO). In another optional embodiment, at least some transistors in the pixel circuit 10 may have a dual-gate structure, which is beneficial to improving the stability and mobility of the transistors.

[0090] Optional, continue to refer to Figure 7 , the first electrode of the light emitting element OLED is electrically connected to the second power supply voltage terminal; the second electrode of the light emitting element OLED is electrically connected to the first light emitting control module 14 at the fourth node N4. The second light emitting control module 15 is electrically connected between the third node N3 and the third power supply voltage terminal, and the voltage of the third power supply voltage terminal is less than the voltage of the second power supply voltage terminal.

[0091] Specifically, the first electrode of the light-emitting element OLED can be electrically connected to the second power supply voltage terminal through the second power supply line PV2_L. The first end of the second light-emitting control module 15 can be electrically connected to the third node N3, and the second end of the second light-emitting control module 15 can be electrically connected to the third power supply voltage terminal through the third power supply line PV3_L. In an optional embodiment, the second power supply signal PV2 provided by the second power supply voltage terminal can be a DC high-level signal, for example, the voltage of the second power supply voltage terminal can be the power supply voltage VDD, and the power supply voltage VDD is generally a positive value. The third power supply signal PV3 provided by the third power supply voltage terminal can be a DC low-level signal, for example, the voltage of the third power supply voltage terminal can be the negative power supply voltage VEE, and the negative power supply voltage VEE is generally grounded or a negative value.

[0092] Exemplarily, the first electrode of the light-emitting element OLED is the anode of the light-emitting element OLED, and the second electrode of the light-emitting element OLED is the cathode of the light-emitting element OLED, and the light-emitting element OLED can be unidirectionally conductive. When the first light-emitting control module 14, the driving transistor M3, and the second light-emitting control module 15 are turned on at the same time, a path can be formed between the second power supply voltage terminal and the third power supply voltage terminal, and a current can be formed in the light-emitting element OLED. The current can first pass through the light-emitting element OLED, and then pass through the first light-emitting control module 14, the driving transistor M3, and the second light-emitting control module 15 in sequence.

[0093] In an optional embodiment, the first power supply voltage terminal is electrically connected to the second power supply voltage terminal.

[0094] Exemplarily, the first electrode of the light-emitting element OLED and the second electrode plate of the second capacitor C2 can be connected to the same power line and receive the same power signal; or, the first electrode of the light-emitting element OLED of the same pixel circuit 10 and the second electrode plate of the second capacitor C2 can also be connected to different power lines, but are electrically connected to the same power voltage terminal through different power lines ( Figure 2 Alternatively, the first electrode of the light-emitting element OLED of the same pixel circuit 10 and the second electrode of the second capacitor C2 can be connected to different power lines, and electrically connected to different power supply voltage terminals through different power lines, but different power supply voltage terminals can be electrically connected or receive the same power supply signal ( Figure 2 This is beneficial to reducing signal lines and simplifying timing control.

[0095] In other optional implementations, the first power supply voltage terminal may also be electrically connected to the third power supply voltage terminal or the first reference voltage terminal, which will not be described one by one.

[0096] Optional, continue to refer to Figure 7The first writing module 11 includes a first writing transistor M2, and the second writing module 12 includes a second writing transistor M5. The first electrode of the first writing transistor M2 is electrically connected to the data voltage terminal, and the second electrode of the first writing transistor M2 is directly electrically connected to the gate of the driving transistor M3; the first electrode of the second writing transistor M5 is electrically connected to the first reference voltage terminal, and the second electrode of the second writing transistor M5 is directly electrically connected to the gate of the driving transistor M3.

[0097] There is no device or element between the second electrode of the first write transistor M2 and the gate of the drive transistor M3, and between the second electrode of the second write transistor M5 and the gate of the drive transistor M3, but conductive structures such as metal wires, bridging holes, and bridging electrodes ( Figure 7 ) electrical connections.

[0098] Exemplarily, the gate of the first write transistor M2 can be electrically connected to the first scan line SP_L, and receive the first scan signal SP on the first scan line SP_L; the first write transistor M2 can be turned on and off under the control of the first scan signal SP. The gate of the second write transistor M5 can be electrically connected to the second scan line S1N_L, and receive the second scan signal S1N on the second scan line S1N_L; the second write transistor M5 can be turned on and off under the control of the second scan signal S1N.

[0099] Optional, continue to refer to Figure 7 The compensation module 13 includes a compensation transistor M4 , a first electrode of the compensation transistor M4 is electrically connected to the first node N1 , and a second electrode of the compensation transistor M4 is electrically connected to the second node N2 .

[0100] Exemplarily, the gate of the compensation transistor M4 can be electrically connected to the third scan line S2N_L to receive the third scan signal S2N on the third scan line S2N_L; the compensation transistor M4 can be turned on and off under the control of the third scan signal S2N. When the compensation transistor M4 is turned on, the voltage of the first node N1 is equal to the voltage of the second node N2.

[0101] Based on the above embodiments, Figure 3 , Figure 4 and Figure 7 The pixel circuit 10 includes a refresh phase tf. In a threshold compensation phase t2 of the refresh phase tf, the first reference voltage terminal is conductively connected to the first node N1, and the first node N1 is conductively connected to the second node.

[0102] Exemplarily, the second writing module 12 includes a second writing transistor M5, and the gate of the second writing transistor M5 can receive the second scanning signal S1N; the compensation module 13 includes a compensation transistor M4, and the gate of the compensation transistor M4 can receive the third scanning signal S2N. In the threshold compensation phase t2 of the refresh phase tf, the second scanning signal S1N and the third scanning signal S2N can be at an enable level, so that the second writing transistor M5 and the compensation transistor M4 are turned on, the first reference signal VREF1 at the first reference voltage end can be transmitted to the first node N1 through the second writing transistor M5, and transmitted to the second node N2 through the second writing transistor M5 and the compensation transistor M4, and the driving transistor M3 is turned on, so that the threshold voltage can be compensated to the third node N3.

[0103] Optional, Figure 8 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Figure 8 Specific support Figure 7 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Figure 7 and Figure 8 The pixel circuit includes a refresh phase tf. In an initialization phase t1 of the refresh phase tf, the light emitting element OLED is cut off from the second node N2, and the third node N3 is connected to the third power supply voltage terminal.

[0104] Exemplarily, the first light-emitting control module 14 includes a first light-emitting control transistor M1, and the gate of the first light-emitting control transistor M1 can receive the first light-emitting control signal EM1; the second light-emitting control module 15 includes a second light-emitting control transistor M6, and the gate of the second light-emitting control transistor M6 can receive the second light-emitting control signal EM2. In the initialization phase t1 of the refresh phase tf, the first light-emitting control signal EM1 jumps to a non-enable level, and the second light-emitting control signal EM2 continues to be an enable level, so that the first light-emitting control transistor M1 is turned off, the second light-emitting control transistor M6 is turned on, and the light-emitting element OLED stops receiving the driving current. At the same time, the third power supply signal PV3 of the third power supply voltage terminal can be transmitted to the third node N3 through the second light-emitting control transistor M6. In this way, the voltage of the third node N3 can be reset before the threshold compensation phase t2, which is conducive to improving the light-emitting accuracy.

[0105] In an optional embodiment, continue to refer to Figure 7 and Figure 8 In the initialization phase t1 of the refresh phase tf, the third node N3 is connected to the third power supply voltage terminal, and the first node N1 is cut off from the second node N2; in the threshold compensation phase t2 of the refresh phase tf, the third node N3 is cut off from the third power supply voltage terminal, and the first node N1 is connected to the second node N2.

[0106] Specifically, in the refresh phase tf, the on-time period of the second light emitting control module 15 does not overlap with the on-time period of the compensation module 13. At this time, the on-time period of the second light emitting control module 15 can overlap with the on-time period of the second writing module 12. In this way, a short circuit between the first reference voltage terminal and the third power supply voltage terminal can be avoided to form an abnormally large current and damage the pixel circuit 10.

[0107] Exemplarily, in the initialization stage t1, the second scan signal S1N and the second light emission control signal EM2 are at the enable level, and the third scan signal S2N is at the non-enable level, so that the second write transistor M5 and the second light emission control transistor M6 are turned on, and the compensation transistor M4 is turned off. The first reference signal VREF1 at the first reference voltage end can be transmitted to the first node N1 through the second write transistor, and the third power signal PV3 at the third power voltage end can be transmitted to the third node N3 through the second light emission control transistor M6, and can also be transmitted to the second node N2 through the second light emission control transistor M6 and the driving transistor M3, but the second node N2 and the first node N1 are cut off, which can avoid the short circuit between the first reference signal VREF1 at the first reference voltage end and the third power signal PV3 at the third power voltage end, forming an abnormally large current and damaging the pixel circuit 10.

[0108] In the threshold compensation stage t2, the second light emitting control signal EM2 is at a non-enable level, the second scanning signal S1N and the third scanning signal S2N are at an enable level, so that the second writing transistor M5 and the compensation transistor M4 are turned on, and the second light emitting control transistor M6 is turned off. The first reference signal VREF1 of the first reference voltage terminal can be transmitted to the first node N1 through the second writing transistor, and the first reference signal VREF1 of the first node N1 can also be transmitted to the second node N2 through the compensation transistor M4, and can also be transmitted to the third node N3, but the third power supply voltage terminal and the third node N3 are cut off, and the first reference signal VREF1 of the first reference voltage terminal and the third power supply signal PV3 of the third power supply voltage terminal can be prevented from being short-circuited, forming an abnormally large current, and damaging the pixel circuit 10.

[0109] In other optional embodiments, in the refresh phase tf, the on-time period of the second light emitting control module 15 may not overlap with the on-time period of the second writing module 12. In this case, the on-time period of the second light emitting control module 15 may overlap with the on-time period of the compensation module 13 ( Figure 8 In this way, it is also possible to avoid a short circuit between the first reference signal VREF1 at the first reference voltage terminal and the third power signal PV3 at the third power voltage terminal, thereby preventing an abnormally large current from being generated and damaging the pixel circuit 10.

[0110] Based on the above embodiments, Fig. 9is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig. 9 Specific support Figure 7 The driving timing of the pixel circuit shown in FIG. Fig. 9 As shown, the working period of the pixel circuit 10 also includes a plurality of display cycles DP, and the display cycle DP includes a refresh phase tf and a hold phase tk. In the hold phase tk, the first node N1 and the second node N2 are cut off, and the third node N3 and the third power supply voltage terminal are connected in a partial period.

[0111] Specifically, in the holding stage tk, the compensation module 13 is turned off, and the second light emitting control module 15 can be turned on during the partial period when the pixel circuit 10 stops providing the driving current to the light emitting element OLED. When the first writing module 11 and the second writing module 12 are directly electrically connected to the gate of the driving transistor M3, in the holding stage tk, the first writing module 11 and the second writing module 12 are also turned off.

[0112] Exemplarily, in the holding stage tk, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can jump to the non-enable level in succession, just like in the refresh stage tf. When the first light-emitting control signal EM1 is at the non-enable level and the second light-emitting control signal EM2 is at the enable level, the first light-emitting control transistor M1 is turned off, the second light-emitting control transistor M6 is turned on, the pixel circuit 10 stops providing the driving current to the light-emitting element OLED, and the third node N3 receives the third power supply signal PV3 at the third power supply voltage terminal; at the same time, the gate-source voltage of the driving transistor M3 remains unchanged, and the driving transistor M3 continues to be turned on, so that VN2=VN3=PV3 can be made, and the first electrode and the second electrode of the driving transistor M3 can be biased and adjusted to avoid the driving transistor M3 being at a certain fixed potential for a long time, causing the threshold voltage of the driving transistor M3 to shift, causing the problem of low-frequency flicker.

[0113] In the holding stage tk, the first scan signal SP, the second scan signal S1N and the third scan signal S2N may all be at non-enable levels, and the first write transistor M2, the second write transistor M5 and the compensation transistor M4 may all be turned off, so that no new signal is written to the first node N1, and the voltage of the first node N1 may remain unchanged. When the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at the enable level at the same time, the driving current may not change, the light-emitting element OLED continues to emit light, and the light-emitting brightness remains unchanged.

[0114] In an optional embodiment, the fifth shift register VSR5 may include M-stage shift register units, the first light-emitting control line EM1_L electrically connected to the same pixel circuit 10 may be electrically connected to the i-th stage shift register unit of the fifth shift register VSR5, the second light-emitting control line EM2_L may be electrically connected to the j-th stage shift register unit of the fifth shift register VSR5, and the i-th signal output by the fifth shift register VSR5 is received as the first light-emitting control signal EM1, and the j-th signal output by the fifth shift register VSR5 is received as the second light-emitting control signal EM2, wherein 1≤i≤j≤M, and i and j are both integers. In other words, the first light-emitting control line EM1_L electrically connected to the pixel circuit 10 in the jth row and the second light-emitting control line EM2_L electrically connected to the pixel circuit 10 in the ith row can be electrically connected and electrically connected to the output end of the same shift register unit of the fifth shift register VSR5, and the first light-emitting control line EM1_L and the second light-emitting control line EM2_L electrically connected to the pixel circuit 10 in the same row can be electrically connected to different shift register units of the fifth shift register VSR5. In this way, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 received by the pixel circuit 10 can both come from the fifth shift register VSR5, and the fourth shift register VSR4 can be omitted, which is conducive to the thinness of the display panel 01.

[0115] Optional, Fig.10 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention. Fig.10 The pixel circuit 10 further includes a first reset module 16, a first end of the first reset module 16 is electrically connected to the second reference voltage end, and a second end of the first reset module 16 is electrically connected to the second node N2.

[0116] Exemplarily, the first reset module 16 includes a first reset transistor M7, a first electrode of the first reset transistor M7 can be connected to the second reference voltage terminal through the second reference line VREF2_L to receive the second reference signal VREF2; a second electrode of the first reset transistor M7 is electrically connected to the second node N3; a gate of the first reset transistor M7 can be electrically connected to the shift register unit of the sixth shift register through the fourth scan line SP*_L to receive the fourth scan signal SP*( Figure 2 The first reset transistor M7 can be turned on and off under the control of the fourth scan signal SP*. When the first reset transistor M7 is turned on, the second reference signal VREF2 at the second reference voltage end can be transmitted to the second node N2 through the first reset transistor M7 to reset the second node N2.

[0117] In an optional embodiment, Fig.11 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.11 Specific support Fig.10 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.10 and Fig.11 The pixel circuit 10 includes a refresh phase tf. In the initialization phase t1 of the refresh phase tf, the second reference voltage terminal and the second node N2 are connected, and the first node N1 and the second node N2 are cut off; in the threshold compensation phase t2 of the refresh phase tf, the second reference voltage terminal and the second node N2 are cut off, and the first node N1 and the second node N2 are connected.

[0118] Exemplarily, in the initialization stage t1, the second scan signal S1N and the fourth scan signal SP* are at the enable level, and the third scan signal S2N is at the non-enable level, so that the second write transistor M5 and the first reset transistor M7 are turned on, and the compensation transistor M4 is turned off. The first reference signal VREF1 at the first reference voltage end can be transmitted to the first node N1 through the second write transistor, and the second reference signal VREF2 at the second reference voltage end can be transmitted to the second node N2 through the first reset transistor M7, but the second node N2 and the first node N1 are cut off, which can avoid the short circuit between the first reference signal VREF1 at the first reference voltage end and the second reference signal VREF2 at the second reference voltage end, forming an abnormally large current and damaging the pixel circuit 10. The driving transistor M3 is turned on in the initialization stage t1, and the second reference signal VREF2 can also be transmitted to the third node N3 through the first reset transistor M7 and the driving transistor M3, and the third node N3 is reset. Before the threshold compensation stage t2, the second node N2 and the third node N3 are reset, which is conducive to accurately compensating the threshold voltage to N3 and improving the light emission accuracy.

[0119] In the threshold compensation stage t2, the fourth scan signal SP* is at a non-enable level, the second scan signal S1N and the third scan signal S2N are at an enable level, so that the first reset transistor M7 is turned off, the second write transistor M5 and the compensation transistor M4 are turned on, and the first reference signal VREF1 at the first reference voltage end can be transmitted to the first node N1 through the second write transistor, and the first reference signal VREF1 at the first node N1 can also be transmitted to the second node N2 through the compensation transistor M4, and the second reference signal VREF2 at the second reference voltage end stops being transmitted to the second node N2, and a short circuit between the first reference signal VREF1 at the first reference voltage end and the second reference signal VREF2 at the second reference voltage end can be avoided to form an abnormally large current and damage the pixel circuit 10.

[0120] In yet another optional embodiment, Fig.12 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.12 Specific support Fig.10 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.10 and Fig.12 The pixel circuit includes a plurality of display cycles DP, and the display cycle DP includes a refresh phase tf and a hold phase tk. In the hold phase tk, the first node N1 and the second node N2 are cut off, and the second reference voltage terminal and the second node N2 are connected in a partial period.

[0121] Specifically, in the holding stage tk, the compensation module 13 is turned off, and the first reset module 16 can be turned on during the partial period when the pixel circuit 10 stops providing the driving current to the light-emitting element OLED. When the first writing module 11 and the second writing module 12 are directly electrically connected to the gate of the driving transistor M3, in the holding stage tk, the first writing module 11 and the second writing module 12 are also turned off.

[0122] Exemplarily, in the holding stage tk, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 may be the same as in the refresh stage tf, and there is a partial period during which the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a non-enable level, and the fourth scanning signal SP* is at an enable level, so that the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned off, the first reset transistor M7 is turned on, the pixel circuit 10 stops providing the driving current to the light-emitting element OLED, and the second node N2 receives the second reference signal VREF2 at the second reference voltage end; at the same time, under the coupling effect of the first capacitor C1, the gate-source voltage of the driving transistor M3 remains unchanged, the driving transistor M3 continues to be turned on, and the second reference signal VREF2 of the second node N2 can also be transmitted to the third node N3 through the driving transistor M3, so that VN2=VN3=VREF2, and the first electrode and the second electrode of the driving transistor M3 can be biased and adjusted to avoid the driving transistor M3 being at a certain fixed potential for a long time, causing the threshold voltage of the driving transistor M3 to shift, causing the problem of low-frequency flicker. In one embodiment, the conduction period between the second reference voltage terminal and the second node N2 is the first reset duration; in the holding stage tk, the conduction period between the second reference voltage terminal and the second node N2 is the second reset duration; the second reset duration and the first reset duration can be the same, so the fourth scan signal SP* in the holding stage tk can be the same as the fourth scan signal SP* in the refresh stage tf, and there is no need to change the fourth scan signal SP* in the holding stage tk, which is conducive to simplifying timing control and reducing costs.

[0123] For example, Fig.13 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.13 Specific support Fig.10 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.10 and Fig.13In the refresh phase tf, the conduction period between the second reference voltage terminal and the second node N2 is the first reset duration; in the holding phase tk, the conduction period between the second reference voltage terminal and the second node N2 is the second reset duration; the second reset duration may be greater than the first reset duration. In this way, the pulse width of the enable level of the fourth scanning signal SP* may be adjusted in the holding phase tk to increase the duration of the bias adjustment, which is beneficial to improving the bias adjustment effect and reducing the hysteresis and threshold voltage drift of the driving transistor M3.

[0124] In other optional implementations, the second end of the first reset module 16 may also be electrically connected to the third node N3, such as Fig.14 As shown, before the threshold compensation stage t2, the second reference signal VREF2 at the second reference voltage terminal can be transmitted to the second node N2 and the third node N3 to reset the second node N2 and the third node N3; and in the holding stage tk, the first electrode and the second electrode of the driving transistor M3 can also be biased and adjusted.

[0125] Based on the above embodiments, Fig.15 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 11-13 ,as well as Fig.15 , the control end of the first light emitting control module 14 is electrically connected to the control end of the second light emitting control module 15 .

[0126] Specifically, there is no need to reset and bias the third node N3 through the second light-emitting control module 15. The first light-emitting control module 14 and the second light-emitting control module 15 of the same pixel circuit 10 can be turned on or off at the same time under the control of the same light-emitting control signal, which is beneficial to simplify the dimming process and dimming timing, and is also beneficial to achieving a thin and light display panel 01.

[0127] Exemplarily, the control end of the first light emitting control module 14 and the control end of the second light emitting control module 15 of the same pixel circuit 10 can be directly electrically connected to the same first light emitting control line EM1_L, and receive the same signal as the first light emitting control signal EM1 and the second light emitting control signal EM2; or, the control end of the first light emitting control module 14 and the control end of the second light emitting control module 15 of the same pixel circuit 10 can also be electrically connected through a signal line, respectively connected to different light emitting control lines, but connected to the shift register unit ( Figure 2 ), receiving the same light emitting control signal as the first light emitting control signal EM1 and the second light emitting control signal EM2.

[0128] Optional, Fig.16 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.16 The pixel circuit 10 further includes a second reset module 17, and the second reset module 17, the first light emitting control module 14, and the light emitting element OLED are electrically connected to a fourth node N4.

[0129] Exemplarily, the first end of the second reset module 17 can be electrically connected to the third reference voltage end through the third reference line VREF3_L, the second end of the second reset module 17 can be electrically connected to the fourth node N4, and the control end of the second reset module 17 can receive the fifth scan signal SPX through the fifth scan line SPX_L. When the light emitting element OLED is cut off from the fourth node N4, the second reset module 17 can transmit the third reference signal VREF3 of the third reference voltage end to the fourth node N4, reset the fourth node N4 using the third reference signal VREF3, and clear the electrical signal remaining in the light emitting element OLED in the previous light emitting stage, which is conducive to accurately controlling the light emitting brightness of the light emitting element OLED in the next light emitting stage.

[0130] Based on the above embodiments, continue to refer to Fig.16 The first light-emitting control module 14 includes a first light-emitting control transistor M1, a first electrode of the first light-emitting control transistor M1 is electrically connected to the light-emitting element OLED at the fourth node N4, and a second electrode of the first light-emitting control transistor M1 is electrically connected to the second node N2; the second reset module 17 includes a second reset transistor M8, a first electrode of the second reset transistor M8 is electrically connected to the third reference voltage terminal, and a second electrode of the second reset transistor M8 is electrically connected to the fourth node N4; a gate of the first light-emitting control transistor M1 is electrically connected to a gate of the second reset transistor M8, and a channel type of the first light-emitting control transistor M1 is different from a channel type of the second reset transistor M8.

[0131] Among them, the channel type of the first light-emitting control transistor M1 is different from the channel type of the second reset transistor M8, which means that the types of channel carriers in the transistors are different, that is, one of the threshold voltages of the two is positive and the other is negative. The active layers of the first light-emitting control transistor M1 and the second reset transistor M8 can be the same or different, and the embodiment of the present invention does not limit the material of the active layer.

[0132] Exemplarily, the first light emission control transistor M1 may be an N-type transistor, the second reset transistor M8 may be a P-type transistor, and the gate of the first light emission control transistor M1 and the gate of the second reset transistor M8 may receive the same signal. When the signal received by the gate of the first light emission control transistor M1 and the gate of the second reset transistor M8 is a high level, the first light emission control transistor M1 is turned on, the second reset transistor M8 is turned off, the light emitting element OLED is turned on with the fourth node N4, and the light emitting element OLED can emit light. At this time, the third reference voltage terminal is turned off with the fourth node N4, and the fourth node N4 is stopped from being reset; when the signal received by the gate of the first light emission control transistor M1 and the gate of the second reset transistor M8 is a low level, the first light emission control transistor M1 is turned off, the second reset transistor M8 is turned on, the light emitting element OLED is turned off with the fourth node N4, and the third reference voltage terminal is turned on with the fourth node N4, and the fourth node N4 can be reset.

[0133] In an optional embodiment, the gate of the first light emission control transistor M1 and the gate of the second reset transistor M8 of the same pixel circuit 10 can be directly electrically connected to the same first light emission control line EM1_L, and receive the same signal as the first light emission control signal EM1 and the fifth scanning signal SPX. In another optional embodiment, the gate of the first light emission control transistor M1 and the gate of the second reset transistor M8 of the same pixel circuit 10 can also be electrically connected through a signal line, respectively connected to different signal lines, but connected to the shift register unit (not shown in the figure) of the same shift register through different signal lines, and receive the same signal as the first light emission control signal EM1 and the fifth scanning signal SPX. In this way, it is conducive to simplifying the structural design and timing design.

[0134] Optional, Fig.17 is a circuit structure diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.17 , the first writing module 11 includes a first writing transistor M2, and the second writing module 12 includes a second writing transistor M5. The first electrode of the first writing transistor M2 is electrically connected to the data voltage terminal, and the second electrode of the first writing transistor M2 is electrically connected to the gate of the driving transistor M3 through the compensation module 13; and / or, the first electrode of the second writing transistor M5 is electrically connected to the first reference voltage terminal; the second electrode of the second writing transistor M5 is electrically connected to the gate of the driving transistor M3 through the compensation module 13.

[0135] The second electrode of the first write transistor M2 and the gate of the drive transistor M3 , as well as the second electrode of the second write transistor M5 and the gate of the drive transistor M3 , may be electrically connected via devices and / or elements, for example, via the compensation module 13 .

[0136] For example, Fig.18 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.18 Specific support Fig.17 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.17 and Fig.18 , the pixel circuit 10 includes a plurality of refresh phases tf. In the initialization phase t1 and the threshold compensation phase t2 of the refresh phase tf, the first scan signal SP is at a non-enable level, the second scan signal S1N and the third scan signal S2N are both at an enable level, the first write transistor M2 is turned off, and the second write transistor M5 and the compensation transistor M4 are both turned on. The first reference signal VREF1 at the first reference voltage terminal can be transmitted to the gate of the driving transistor M3 through the second write transistor M5 and the compensation transistor M4 to initialize the driving transistor M3. The first reference signal VREF1 can also be transmitted to the second node N2 through the second write transistor M5, so that the first reference signal VREF1 at the second node N2 can be transmitted to the third node N3 to perform threshold compensation on the driving transistor M3.

[0137] In the writing phase t3 of the refresh phase tf, the second scanning signal S1N is at a non-enable level, the first scanning signal SP and the third scanning signal S2N are both at an enable level, the second writing transistor M5 is turned off, and the first writing transistor M2 and the compensation transistor M4 are both turned on. The data signal Data at the data voltage end can be transmitted to the gate of the driving transistor M3 through the first writing transistor M2 and the compensation transistor M4. At the same time, the data signal Data is less than the first reference signal VREF1, which can turn off the driving transistor M3, and the third node N3 stops receiving the signal of the second node N2. The data signal Data will not be transmitted to the third node N3 through the second node N2, and the threshold voltage compensated to the third node N3 will not be cleared, and the voltage change of the first node N1 can be partially coupled to the third node N3, so that the gate-source voltage of the driving transistor M3 is related to the data signal Data, and has nothing to do with the threshold voltage.

[0138] Based on the above embodiments, Fig.19 is a timing diagram of another pixel circuit provided by an embodiment of the present invention. Fig.19 Specific support Fig.17 The driving timing of the pixel circuit shown in Figure 2 is shown in Figure 2. Fig.17 and Fig.19 The pixel circuit 10 includes a plurality of display cycles DP, and the display cycle DP includes a refresh phase tf and a hold phase tk. In the hold phase tk, the second node N2 is disconnected from the first node N1, and the data voltage terminal and / or the first reference voltage terminal are connected to the second node N2 in a partial period.

[0139] Specifically, in the holding phase tk, the compensation module 13 is turned off, the first write transistor M2 and / or the second write transistor M5 can be turned on during the partial period when the pixel circuit 10 stops providing the driving current to the light-emitting element OLED, and the first electrode and the second electrode of the driving transistor M3 can also be biased.

[0140] Exemplarily, in the holding stage tk, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 may be the same as the refresh stage tf, and there is a partial period during which the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a non-enable level, and the first scan signal SP and / or the second scan signal S1N are at an enable level, so that the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned off, the first write transistor M2 and / or the second write transistor M3 are turned on, the pixel circuit 10 stops providing the driving current to the light-emitting element OLED, and the second node N2 receives the first reference signal VREF1 at the first reference voltage end or the data signal Data at the data voltage end; at the same time, under the coupling effect of the first capacitor C1, the gate-source voltage of the driving transistor M3 remains unchanged, the driving transistor M3 is turned on, the first reference signal VREF1 at the first reference voltage end or the data signal Data at the data voltage end can be transmitted to the third node N3 through the driving transistor M3, so that VN2=VN3=VREF1 or VN2=VN3=Data can be made to bias the first electrode and the second electrode of the driving transistor M3, and at this time, the first reset module 16 may not be provided.

[0141] Based on the same inventive concept, an embodiment of the present invention further provides a method for driving a pixel circuit, which is used to drive the pixel circuit 10 provided by any embodiment of the present invention. Fig. 20 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present invention, with reference to Fig. 20 , the driving methods include:

[0142] S110, initialization stage, the first reference voltage terminal and the first node are connected.

[0143] S120, threshold compensation stage, the first reference voltage terminal is connected to the first node, and the first node is connected to the second node.

[0144] S130, writing stage, the data voltage terminal is connected to the first node.

[0145] S140, light emitting stage, the light emitting element is conductively connected to the third node, and the third node is conductively connected to the third power supply voltage terminal.

[0146] The driving method of the pixel circuit provided by the embodiment of the present invention, in the initialization stage, the second writing module can be controlled to be turned on by the second scanning signal, the first reference signal of the first reference voltage terminal can be transmitted to the first node by the second writing module, the potential of the first node is initialized, and the driving transistor is controlled to be in the on state; in the threshold compensation stage, the second writing module and the compensation module can be controlled to be turned on by the second scanning signal and the third scanning signal, and the threshold voltage of the driving transistor is compensated to the driving transistor; in the writing stage, the first writing module can be controlled to be turned on by the first scanning signal, the data signal of the data voltage terminal can be transmitted to the first node by the first writing module, and the third node is partially coupled under the action of the first capacitor and the second capacitor, wherein the first capacitor can also store the gate-source voltage of the driving transistor; in the light-emitting stage, the first light-emitting control module and the second light-emitting control module can be controlled to be turned on by the first light-emitting control signal and the second light-emitting control signal, and the driving current of the pixel circuit can be provided to the light-emitting element, so that the light-emitting element emits light. When the pixel circuit is applied to a display panel, the problems of afterimage and low-frequency flicker of the display panel can be improved.

[0147] The driving method of the pixel circuit provided in the embodiment of the present invention is used to drive the pixel circuit provided in any embodiment of the present invention, and has the corresponding technical features and beneficial effects of the pixel circuit. For the contents not fully described in the embodiment of the driving method of the pixel circuit, refer to the above description of the pixel circuit, and will not be repeated here; similarly, the pixel circuit of the embodiment of the present invention also has the functional modules and beneficial effects that can execute the driving method of the pixel circuit provided in the embodiment of the present invention. For the contents not fully described in the embodiment of the pixel circuit, refer to the above description of the driving method of the pixel circuit, and will not be repeated here.

[0148] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, Fig.21 is a schematic diagram of a display panel provided by an embodiment of the present invention, with reference to Fig.21 The display panel 01 includes a plurality of pixel circuits 10 arranged in an array. The pixel circuit 10 may be a pixel circuit 10 provided by any embodiment of the present invention.

[0149] Exemplarily, the display panel 01 further includes a plurality of first scan lines SP_L, a plurality of second scan lines S1N_L, a plurality of third scan lines S2N_L, a plurality of data lines Data_L, a plurality of first light emission control lines EM1_L, and a plurality of second light emission control lines EM2_L connected to the plurality of pixel circuits 10, and may further include a plurality of first reference lines, a plurality of first power supply lines, etc. ( Fig.21The first scan line SP_L can be connected to the control end of the first writing module in the pixel circuit 10, the second scan line S1N_L can be connected to the control end of the second writing module in the pixel circuit 10, the third scan line S2N_L can be connected to the control end of the compensation module in the pixel circuit 10, the first light-emitting control line EM1_L can be connected to the control end of the first light-emitting control module in the pixel circuit 10, and the second light-emitting control line EM2_L can be connected to the control end of the second light-emitting control module in the pixel circuit 10.

[0150] The display panel provided by an embodiment of the present invention includes a plurality of pixel circuits arranged in an array as provided by any embodiment of the present invention, and has the corresponding technical features and beneficial effects of the pixel circuit. For the contents not fully described in the embodiment of the display panel, refer to the above description of the pixel circuit and will not be repeated here.

[0151] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig. 22 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig. 22 As shown, the display device 02 includes a display panel 01 provided by any embodiment of the present invention. The display device 02 provided by the embodiment of the present invention can be Fig. 22 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0152] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that: include: A driving transistor, a light emitting element, a first writing module, a second writing module, a compensation module, a first capacitor, a second capacitor, a first light emitting control module and a second light emitting control module; A first end of the first writing module is electrically connected to the data voltage end, and a second end of the first writing module is electrically connected to the gate of the driving transistor; A first terminal of the second writing module is electrically connected to a first reference voltage terminal, and a second terminal of the second writing module is electrically connected to a gate of the driving transistor; The first end of the compensation module is electrically connected to the gate of the driving transistor at a first node, and the second end of the compensation module is electrically connected to the first electrode of the driving transistor at a second node; The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor and the second electrode of the driving transistor are electrically connected to a third node; The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first power supply voltage terminal; The first light emitting control module is electrically connected between the light emitting element and the second node; the second light emitting control module is electrically connected to the third node; The driving transistor is an N-type transistor.

2. The pixel circuit according to claim 1, characterized in that: The first writing module includes a first writing transistor, the second writing module includes a second writing transistor, the compensation module includes a compensation transistor, the first light emitting control module transistor includes a first light emitting control transistor, and the second light emitting control module includes a second light emitting control transistor; The first write transistor, the second write transistor, the compensation transistor, the first light emission control transistor, and the second light emission control transistor are all N-type transistors.

3. The pixel circuit according to claim 1, characterized in that: The active layer of the driving transistor includes a metal oxide material.

4. The pixel circuit according to claim 1, characterized in that: The first electrode of the light emitting element is electrically connected to the second power supply voltage terminal; the second electrode of the light emitting element is electrically connected to the first light emitting control module at a fourth node; The second light emitting control module is electrically connected between the third node and a third power supply voltage terminal; The voltage of the second power supply voltage terminal is greater than the voltage of the third power supply voltage terminal.

5. The pixel circuit according to claim 4, characterized in that: The first power supply voltage terminal is electrically connected to the second power supply voltage terminal.

6. The pixel circuit according to claim 1, characterized in that: The first writing module includes a first writing transistor; the second writing module includes a second writing transistor; The first electrode of the first write transistor is electrically connected to the data voltage terminal; the second electrode of the first write transistor is directly electrically connected to the gate of the drive transistor; The first electrode of the second write transistor is electrically connected to the first reference voltage terminal; the second electrode of the second write transistor is directly electrically connected to the gate of the drive transistor.

7. The pixel circuit according to claim 1, characterized in that: The first writing module includes a first writing transistor; the second writing module includes a second writing transistor; The first electrode of the first write transistor is electrically connected to the data voltage terminal; the second electrode of the first write transistor is electrically connected to the gate of the drive transistor through the compensation module; The first electrode of the second write transistor is electrically connected to the first reference voltage terminal; the second electrode of the second write transistor is electrically connected to the gate of the driving transistor through the compensation module.

8. The pixel circuit according to claim 1, characterized in that: The compensation module includes a compensation transistor; a first electrode of the compensation transistor is electrically connected to the first node; and a second electrode of the compensation transistor is electrically connected to the second node.

9. The pixel circuit according to claim 1, characterized in that: The pixel circuit includes a refresh phase; In the threshold compensation phase of the refresh phase, the first reference voltage terminal is conductively connected to the first node, and the first node is conductively connected to the second node.

10. The pixel circuit according to claim 1, characterized in that: The pixel circuit includes a refresh phase; In the initialization phase of the refresh phase, the light emitting element is cut off from the second node, and the third node is connected to the third power supply voltage terminal.

11. The pixel circuit according to claim 10, characterized in that: In the initialization phase of the refresh phase, the third node is connected to the third power supply voltage terminal, and the first node is disconnected from the second node; In the threshold compensation phase of the refresh phase, the third node and the third power supply voltage terminal are cut off, and the first node and the second node are connected.

12. The pixel circuit according to claim 10, characterized in that: The pixel circuit includes a plurality of display cycles; the display cycle includes the refresh phase and the hold phase; In the holding phase, the first node and the second node are cut off, and the third node and the third power supply voltage terminal are connected in a partial period.

13. The pixel circuit according to claim 1, characterized in that: Also includes: A first reset module; The first end of the first reset module is electrically connected to the second reference voltage end; the second end of the first reset module is electrically connected to the second node.

14. The pixel circuit according to claim 13, characterized in that: The pixel circuit includes a refresh phase; In the initialization phase of the refresh phase, the second reference voltage terminal is connected to the second node, and the first node is disconnected from the second node; In the threshold compensation phase of the refresh phase, the second reference voltage terminal and the second node are disconnected, and the first node and the second node are connected.

15. The pixel circuit according to claim 13, characterized in that: The pixel circuit includes a plurality of display cycles; the display cycle includes a refresh phase and a hold phase; In the holding phase, the first node and the second node are cut off, and the second reference voltage terminal and the second node are connected in a partial period.

16. The pixel circuit according to claim 13, characterized in that: The control end of the first light emitting control module is electrically connected to the control end of the second light emitting control module.

17. The pixel circuit according to claim 1, characterized in that: Also includes: A second reset module; The second reset module, the first light emitting control module, and the light emitting element are electrically connected to a fourth node.

18. The pixel circuit according to claim 17, characterized in that: The first light emitting control module comprises a first light emitting control transistor; a first electrode of the first light emitting control transistor is electrically connected to the light emitting element at the fourth node, and a second electrode of the first light emitting control transistor is electrically connected to the second node; The second reset module includes a second reset transistor; a first electrode of the second reset transistor is electrically connected to the third reference voltage terminal, and a second electrode of the second reset transistor is electrically connected to the fourth node; A channel type of the first light emission control transistor is different from a channel type of the second reset transistor; a gate of the first light emission control transistor is electrically connected to a gate of the second reset transistor.

19. A method for driving a pixel circuit, characterized in that: Used to drive the pixel circuit according to any one of claims 1 to 18; The driving method comprises: In the initialization stage, the first reference voltage terminal is connected to the first node; In the threshold compensation stage, the first reference voltage terminal is conductively connected to the first node, and the first node is conductively connected to the second node; In the writing stage, the data voltage terminal is connected to the first node; In the light emitting stage, the light emitting element is conductively connected to the third node, and the third node is conductively connected to the third power supply voltage terminal.

20. A display panel, characterized in that: include: A plurality of pixel circuits as described in any one of claims 1 to 18 are arranged in an array.

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