LCD (Liquid Crystal Display) pixel driving circuit for color sequence display

Abstract

The invention discloses an LCD (Liquid Crystal Display) pixel driving circuit for color sequence display, which comprises a first transistor, a pre-storage capacitor, a second transistor, a holding capacitor, a third transistor and a liquid crystal capacitor, and is characterized in that a first source drain electrode of the first transistor is coupled to a data signal line, and a grid electrode is coupled to a control signal line; the second source and drain electrode is coupled to the first source and drain electrode of the second transistor and one end of the pre-storage capacitor; the grid electrode of the second transistor is coupled to the transfer signal line, and the second source-drain electrode is coupled to the first source-drain electrode of the third transistor, one end of the holding capacitor and one end of the liquid crystal capacitor; one ends, far away from the transistor, of the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor are coupled to the first common electrode wire or the second common electrode wire; the grid electrode of the third transistor is coupled to the first reset signal line or the second reset signal line, and the second source drain electrode is coupled to the first common electrode line or the second common electrode line.

Description

Technical Field

[0001] The invention relates to the technical field of pixel driving, and in particular to an LCD pixel driving circuit for color sequential display. Background Art

[0002] In field sequential or color sequential display technology, the backlight can only be turned on after all the screen data is written and the liquid crystal is deflected to a stable state. Otherwise, the screen will be chaotic. Therefore, the data writing and liquid crystal deflection time will greatly compress the backlight turn-on time, resulting in difficulties in improving the brightness of the display, as well as difficulties in improving the refresh rate and resolution, increased power consumption and increased backlight material costs.

[0003] Conventional pixel driving circuit, refer to Figure 7 (Canon proposed a pixel driving circuit in its U.S. Patent No. 6181311). The difference between this circuit and the traditional 1T2C pixel design is that, in addition to the pixel signal writing switch TFT T1, there is an additional data storage capacitor Cs1, a signal transfer TFT T2, and a reset TFT T3. The signal storage capacitor Cs1 is used to pre-store the pixel data voltage required for the next picture, and the signal transfer TFT T2 is used to transfer the pixel data voltage pre-stored in the signal storage capacitor Cs1 to the corresponding pixel voltage storage capacitor Cs2 and the liquid crystal capacitor Clc. The reset TFT T3 is used to eliminate the charge originally remaining on the pixel capacitor to prevent the effects of color deviation and brightness difference caused by the residual charge. This circuit design can use the signal storage capacitor Cs1 to pre-store the pixel data voltage of the next frame during the backlight emission time, and when switching the picture, all pixels synchronously read the pixel data voltage in the corresponding Cs1. Through the design of this pixel data voltage register, the pixel number writing time can be saved and the backlight emission time can be correspondingly increased.

[0004] However, this pixel circuit design faces the problem of voltage reduction associated with charge sharing. Assuming that the pre-charge capacitor Cs1=Cs2+Clc, Vcom=0V (i.e., the pixel electrode is reset to 0V before charging), if Clc is to be charged to 5V, then according to the principle of charge conservation, Cs1 needs to be pre-charged to 10V to achieve this. Therefore, this driving method needs to increase the Data voltage supply range to meet the liquid crystal operating voltage range, put forward higher requirements on the Source IC output voltage range, and greatly increase power consumption. When the Source IC does not meet the requirements, a larger Cs1 capacitor is required. When Cs1 is much larger than Cs2+Clc, the voltage drop will be smaller during charge sharing, but this will reduce the aperture ratio and increase the difficulty of Cs1 pre-charging, which is not conducive to the realization of high refresh rate and high resolution.

[0005] In summary, the traditional pixel driving circuit has the problems of low aperture ratio and great driving difficulty. Summary of the invention

[0006] In view of this, the present invention provides an LCD pixel driving circuit for color sequential display, which solves the problems of low aperture ratio and great driving difficulty in traditional pixel driving circuits by improving the circuit structure and corresponding driving timing.

[0007] In order to solve the above problems, the technical solution of the present invention is to adopt an LCD pixel driving circuit for color sequential display, which at least includes: a first pixel driving unit and a second pixel driving unit, wherein the first pixel driving unit and the second pixel driving unit both include a first transistor, a pre-storage capacitor, a second transistor, a holding capacitor, a third transistor and a liquid crystal capacitor, wherein the first source and drain of the first transistor are coupled to the data signal line, the gate is coupled to the control signal line, the second source and drain are coupled to the first source and drain of the second transistor and one end of the pre-storage capacitor; the gate of the second transistor is coupled to the transfer signal line, the second source and drain are coupled to The first source and drain of the third transistor, one end of the holding capacitor and one end of the liquid crystal capacitor; the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor of the first pixel driving unit are coupled to the first common electrode line at one end away from the transistor, and the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor of the second pixel driving unit are coupled to the second common electrode line at one end away from the transistor; the gate of the third transistor of the first pixel driving unit is coupled to the first reset signal line, and the second source and drain are coupled to the second common electrode line; the gate of the third transistor of the second pixel driving unit is coupled to the second reset signal line, and the second source and drain are coupled to the first common electrode line.

[0008] Optionally, during the backlight on time, the first transistor is controlled to turn on based on a control signal, and the first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor until all pixels complete voltage pre-storage.

[0009] Optionally, when the backlight is turned off in the Nth frame: first, after the second common voltage jumps to a high potential, the first reset signal jumps to a high potential, and the liquid crystal capacitor and the holding capacitor of the first pixel driving unit are reset based on the third transistor; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, after the first common voltage jumps to a low potential, the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and the voltage required for the liquid crystal flip target angle is formed on the liquid crystal capacitor based on the second transistor; when entering the N+1th frame, the backlight is turned on.

[0010] Optionally, when the backlight is turned off in the N+1 frame: first, after the second common voltage jumps to a low potential, the first reset signal jumps to a high potential, and the liquid crystal capacitor and the holding capacitor of the first pixel driving unit are reset based on the third transistor; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, after the first common voltage jumps to a high potential, the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and the voltage required for the liquid crystal flip target angle is formed on the liquid crystal capacitor based on the second transistor; when entering the N+2 frame, the backlight is turned on.

[0011] Optionally, when the backlight is turned on in the Nth frame, the data signal of the first pixel driving unit is configured as a positive polarity potential, and the data signal of the second pixel driving unit is configured as a negative polarity potential; when the backlight is turned on in the N+1th frame, the data signal of the first pixel driving unit is configured as a negative polarity potential, and the data signal of the second pixel driving unit is configured as a positive polarity potential.

[0012] Optionally, the LCD pixel driving circuit may also be configured as follows: a gate of the third transistor of the first pixel driving unit and a gate of the third transistor of the second pixel driving unit are both coupled to the same reset signal line.

[0013] Optionally, when the second common voltage jumps to a high potential and the first common voltage jumps to a low potential, or when the second common voltage jumps to a low potential and the first common voltage jumps to a high potential, the first reset signal jumps to a high potential, synchronously completing the resetting of the liquid crystal capacitor and the holding capacitor of the first pixel driving unit and the second pixel driving unit.

[0014] Optionally, the LCD pixel driving circuit can also be configured as follows: the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor of the first pixel driving unit and the second pixel driving unit are coupled to the same common electrode line at one end away from the transistor; the second source and drain of the third transistor of the first pixel driving unit is coupled to the first global signal line, and the second source and drain of the third transistor of the second pixel driving unit is coupled to the second global signal line.

[0015] Optionally, when the data signal of the first pixel driving unit is configured as a positive polarity potential and the data signal of the second pixel driving unit is configured as a negative polarity potential, the first global signal under the frame is configured as a high potential and the second global signal is configured as a low potential; when the data signal of the first pixel driving unit is configured as a negative polarity potential and the data signal of the second pixel driving unit is configured as a positive polarity potential, the first global signal under the frame is configured as a low potential and the second global signal is configured as a high potential.

[0016] Optionally, the high potential of the global signal is configured as: common voltage+maximum operating voltage of liquid crystal; the low potential of the global signal is configured as: common voltage-maximum operating voltage of liquid crystal.

[0017] The primary improvement of the present invention is the LCD pixel driving circuit for color sequential display. Through the pre-storage capacitor design, the data signal voltage writing and light emission under color sequential display are realized at the same time, and the light emission time is increased. At the same time, the present invention optimizes the pixel electrode reset circuit, such as reusing the Vcom signal line, or adding an additional reset signal source to reset the pixel electrode, so as to achieve the reset of the pixel electrodes corresponding to the positive and negative polarities to different potentials, reduce the charge required for the Cs1 of each row of pixels to write the pixel data voltage separately, thereby reducing the required Data signal voltage range, reducing the driving difficulty and Source IC power consumption, and introducing fewer additional signal lines, without significantly increasing the complexity of the pixel layout (little impact on the aperture ratio), solving the problems of low aperture ratio and high driving difficulty in traditional pixel driving circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a simplified circuit diagram of an LCD pixel driving circuit for color sequential display of the present invention; Figure 2 It is a driving timing diagram of an LCD pixel driving circuit for color sequential display of the present invention; Figure 3 is a simplified circuit diagram of an LCD pixel driving circuit for color sequential display according to a preferred embodiment of the present invention; Figure 4 is a driving timing diagram of an LCD pixel driving circuit for color sequential display according to a preferred embodiment of the present invention; Figure 5 is a simplified circuit diagram of an LCD pixel driving circuit for color sequential display according to another preferred embodiment of the present invention; Figure 6 is a driving timing diagram of an LCD pixel driving circuit for color sequential display according to another preferred embodiment of the present invention; Figure 7 This is a circuit and driving timing diagram of the prior art shown in the background technology of the present invention. Implementation

[0019] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0024] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. Example

[0027] Specifically, Figure 1 As shown, an LCD pixel driving circuit for color sequential display is characterized in that it at least includes: a first pixel driving unit and a second pixel driving unit, wherein the first pixel driving unit and the second pixel driving unit both include a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a holding capacitor Cs2, a third transistor T3 and a liquid crystal capacitor Clc, wherein the first source and drain of the first transistor T1 are coupled to the data signal line Data, the gate is coupled to the control signal line Scan, the second source and drain are coupled to the first source and drain of the second transistor T2 and one end of the pre-storage capacitor Cs1; the gate of the second transistor T2 is coupled to the transfer signal line Tran, the second source and drain are coupled to the first source and drain of the third transistor T3, one end of the holding capacitor Cs2 and the liquid crystal capacitor Clc. one end of the capacitor Clc; the pre-storage capacitor Cs1, the holding capacitor Cs2 and the liquid crystal capacitor Clc of the first pixel driving unit are coupled to the first common electrode line Vcom-Odd, and the pre-storage capacitor Cs1, the holding capacitor Cs2 and the liquid crystal capacitor Clc of the second pixel driving unit are coupled to the second common electrode line Vcom-Even; the gate of the third transistor T3 of the first pixel driving unit is coupled to the first reset signal line Reset-Odd, and the second source and drain are coupled to the second common electrode line Vcom-Even; the gate of the third transistor T3 of the second pixel driving unit is coupled to the second reset signal line Reset-Even, and the second source and drain are coupled to the first common electrode line Vcom-Odd.

[0028] Specifically, to facilitate understanding of the working timing of the pixel driving circuit, as shown in FIG. Figure 7 As shown: During the backlight on time of the Nth frame (herein defined as an odd-numbered frame), the data signal of the first pixel driving unit is configured as a positive polarity potential, the data signal of the second pixel driving unit is configured as a negative polarity potential, the first transistor T1 is controlled to be turned on based on the control signal, and the first transistor T1 outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor Cs1 until all pixels complete voltage pre-storage; When the backlight of the Nth frame is turned off, first, after the second common voltage jumps to a high potential, the first reset signal jumps to a high potential, and the liquid crystal capacitor Clc and the holding capacitor Cs2 of the first pixel driving unit are reset based on the third transistor T3; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, after the first common voltage jumps to a low potential, the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and the voltage required for the liquid crystal to flip the target angle is formed on the liquid crystal capacitor Clc based on the second transistor T2; During the backlight on time of the N+1th frame (herein defined as an even frame), the data signal of the first pixel driving unit is configured as a negative polarity potential, the data signal of the second pixel driving unit is configured as a positive polarity potential, the first transistor T1 is controlled to be turned on based on the control signal, and the first transistor T1 outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor Cs1 until all pixels complete voltage pre-storage; During the backlight off time of the N+1th frame, first, after the second common voltage jumps to a low potential, the first reset signal jumps to a high potential, and the liquid crystal capacitor Clc and the holding capacitor Cs2 of the first pixel driving unit are reset based on the third transistor T3; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, after the first common voltage jumps to a high potential, the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and the voltage required for the liquid crystal to flip the target angle is formed on the liquid crystal capacitor Clc based on the second transistor T2; When entering the N+2th frame, the backlight is turned on and the driving timing of the Nth frame is cycled.

[0029] It should be noted here that N is an odd number and a positive integer, and can be configured as 1, 3, 5, 7... in the above embodiments. At the same time, in order to fully illustrate the signal changes required for different polarity reversals of the liquid crystal, the present invention limits the frames to N and N+1. Here, it is assumed that the liquid crystal needs to perform polarity reversal in every frame, but the technical solution claimed by the present invention is also applicable to the polarity reversal of the liquid crystal every M frames, M∈(2,+∞). Therefore, the descriptions of the Nth frame, the N+1th frame, etc. used to accurately illustrate the technical solution claimed by the present invention should not be regarded as limiting the scope of protection of the present application.

[0030] It should also be noted that the present invention is described in the embodiment circuit with an N-type TFT. When the gate control signal (control signal, reset signal and transfer signal) corresponds to the timing diagram, its high potential is turned on and the low potential is turned off. It can also be extended to a P-type TFT, in which case the low potential is turned on and the high potential is turned off, which are all included in the protection scope of the present invention. At the same time, the "high potential" and "low potential" of the common voltage recorded in the present invention refer to: the potential is higher or lower than the normal potential when emitting light; the "positive polarity potential" of the data signal recorded in the present invention is defined as: when the target potential of the pixel electrode -Vcom≥0V, the voltage range of the data signal, and the "negative polarity potential" of the data signal is defined as: when the target potential of the pixel electrode -Vcom≤0V, the voltage range of the data signal. At the same time, it should be noted that since the technical solution claimed for protection of the present invention uses a jumping common voltage to reset the liquid crystal capacitor Clc, the positive polarity potential and the negative polarity potential may overlap to a certain extent in range.

[0031] The primary improvement of the present invention is to provide an LCD pixel driving circuit for color sequential display, which realizes data signal voltage writing and light emission simultaneously under color sequential display through pre-storage capacitor design, thereby increasing the light emission time.

[0032] At the same time, the present invention sets the common voltage as two independent global signals and also sets the reset signal as two independent global signals. They are all provided by IC or other signal generating units. When resetting within a frame, the first pixel driving unit (odd column pixel node) uses the common voltage corresponding to the even column as the signal source for reset, and the second pixel driving unit (even column pixel node) uses the common voltage corresponding to the odd column as the signal source for reset. The odd column and the even column pixels are reset in time-sharing, and the common voltage signal of the corresponding signal source is jumped before resetting to reduce the maximum Pre-Charge node voltage required by the pre-storage capacitor during charge sharing, thereby reducing the data signal voltage range (Data Range) required to be provided by the Source IC, saving the power consumption of the Source IC and the power consumption of the Scan output unit (IC or GOA, etc.) of the control signal; it can also reduce the ratio limit of Cs1 and Clc. Improve the aperture ratio and reduce the difficulty of pre-charging. That is, the present invention can reset the pixel electrodes corresponding to the positive and negative polarities to different potentials by optimizing the pixel electrode reset circuit, such as reusing the Vcom signal line, or adding an additional reset signal source, etc., to reset the pixel electrode, thereby reducing the charge required for Cs1 of each subsequent row of pixels to write the pixel data voltage separately (reducing the driving difficulty), and introducing fewer additional signal lines without significantly increasing the complexity of the pixel layout (little impact on the aperture ratio), thereby solving the problems of low aperture ratio and high driving difficulty in traditional pixel driving circuits.

[0033] It should be noted here that the technical solution claimed to be protected above uses a column inversion method to achieve polarity inversion, that is, the pixel voltage polarity of each pixel is reversed according to a frame cycle (the reason is: the need for liquid crystal drive polarity inversion. If the liquid crystal is driven by DC voltage, it will cause polarization of the liquid crystal, resulting in problems such as DC afterimage and liquid crystal damage).

[0034] Further, Figure 7 (A pixel driving circuit proposed by Canon in its U.S. Patent No. 6181311) Description Figure 7 The Data signal voltage range required by the circuit. Assume that all pixels Cs1 is designed to be = Cs2 + clc. And under all grayscales, the operating voltage between the pixel electrode and the Vcom electrode required by the liquid crystal is 0~Vop_max (Vop_max is the maximum operating voltage of the liquid crystal, which is a positive value. The maximum voltage required by Vpixel for positive polarity is Vcom+Vop, and the minimum voltage required by Vpixel for negative polarity is Vcom-Vop), where Vpixel is the pixel electrode voltage.

[0035] Taking the odd columns as an example, suppose that in the Nth frame (N is a natural number) display stage, the odd columns (the first and third columns) are driven with negative polarity (Vpixel-Vcom≤0), then due to the requirement of liquid crystal polarity inversion, the N+1th frame should be driven with positive polarity (Vpixel-Vcom≥0), and according to the working principle of the pre-storage method ( Figure 7 ), at the display time of the Nth frame, the data signal voltage of the N+1th frame is written to Cs1, so a positive polarity voltage, i.e., a voltage ≥ Vcom, needs to be written. For a certain odd-numbered column pixel a, Figure 7 In the transfer phase (Transfer) within a frame, the Reset signal is used to open T3 to reset the pixel electrode to the Vcom voltage, and then the Transfer signal is used to control T2 to open and transfer the data signal voltage pre-stored on Cs1 to the pixel electrode. Assuming that the pre-written Cs1 voltage is Vcs1, the corresponding Figure 7In this mode, after transfer is turned on, if Vpixel needs to be equal to the maximum value Vop_max+Vcom, according to the principle of charge conservation, (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)-Vcom)*(Cs2+Clc), that is, Vcs1-Vop_max-Vcom=Vop_max, Vcs1= 2*Vop_max+Vcom. Similarly, when writing a negative polarity voltage to Cs1, if the minimum value -Vop_max is required, according to the principle of charge conservation, Vs1-(-Vop_max+Vcom)*Cs1=((-Vop_max+Vcom)-Vcom)*(Cs2+Clc), Vs1+Vop_max-Vcom=-Vop_max, Vs1=-2*Vop_max+Vcom. Therefore, the required Data voltage range is (2*Vop_max+Vcom)-(-2*Vop_max+Vcom)=4*Vop_max; and for the Normal 1T2C LCD pixel drive circuit, because there is no pre-storage design, there is no charge sharing, and the Data voltage range is -Vop_max~Vop_max, which is 2 times the Vop_max voltage. Therefore, use Figure 7 When driving the solution, the Vdata voltage range needs to be doubled.

[0036] When using the driving method claimed in the present application: after the transfer is turned on, if the maximum value of Vpixel is required to be equal to Vop_max+Vcom, the pixel electrode voltage has been reset to Vop_max+Vcom. According to the principle of conservation of charge, (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)- (Vop_max+Vcom))*(Cs2+Clc), that is, Vcs1-Vop_max-Vcom=0, Vcs1= Vop_max+Vcom. If Vpixel needs to be equal to Vcom, (Vcs1-Vcom)*Cs1=(Vcom- (Vop_max +Vcom))*(Cs2+Clc), Vcs1-Vcom=Vcom- (Vop_max +Vcom), Vcs1=Vcom-Vop_max, that is, the required Data voltage range is (Vop_max+Vcom)- (Vcom- Vop_max)=2*Vop_max.

[0037] Similarly, when a negative voltage is written to Cs1 in the next frame, the same formula can be used to deduce that the Data voltage range is still between Vop_max+Vcom and Vcom-Vop_max, so the overall Vdata range is 2*Vcop_max, which is equivalent to the Normal 1T2C circuit.

[0038] Therefore, by using the technical solution claimed in the present application, a significant reduction in the Data voltage range can be achieved by partially or completely overlapping the Vdata voltage range in terms of positive and negative polarities.

[0039] At the same time, the charge sharing formula also shows that Figure 7 In the driving circuit, when Cs1 is smaller or Clc+Cs2 is larger, the charge sharing effect is worse, and a larger Data voltage range is required. Therefore, this circuit has greater restrictions on the size of Cs1, Clc, and Cs2, requiring a larger Cs1 and a smaller Cs2+Clc. When Cs1 increases, it will affect the aperture ratio. When Cs2+Clc decreases, the pixel voltage leaks more within a frame, and flickering (Flicker) and other problems are prone to occur. Therefore, higher requirements are placed on TFT characteristics. The circuit and driving method claimed in this application do not have such restrictions and requirements. Therefore, it is more conducive to improving the aperture ratio and is conducive to the driving realization of high refresh rate and high resolution display products.

[0040] In addition, when the circuit and driving method of this proposal are used, when the ratio of Cs1 / (Clc+Cs2) is increased, when it is greater than 1, according to the charge sharing formula, the Data voltage range can be compressed and can be smaller than the voltage range 2*Vop_max required for Normal 1T2C. This can further reduce the power consumption of the Source IC and the Scan output unit (because the Scan signal switch voltage difference is reduced), and at the same time, the maximum Vds voltage difference when TFT T1 is turned off can also be reduced, so the leakage current when the TFT is turned off can be reduced, and the display quality of Flicker and the like is further improved. Example

[0041] This application also provides a preferred embodiment, such as Figure 3 As shown, the LCD pixel driving circuit may also be configured as follows: the gate of the third transistor T3 of the first pixel driving unit and the gate of the third transistor T3 of the second pixel driving unit are both coupled to the same reset signal line.

[0042] At this time, if Figure 4As shown, when the second common voltage jumps to a high potential and the first common voltage jumps to a low potential, or when the second common voltage jumps to a low potential and the first common voltage jumps to a high potential, the first reset signal jumps to a high potential, and the liquid crystal capacitor Clc and the holding capacitor Cs2 of the first pixel driving unit and the second pixel driving unit are reset synchronously.

[0043] In this embodiment, the first pixel driving unit and the second pixel driving unit use the same reset signal line, that is, use a common Reset signal, and use each other's Vcom signal as the signal source for simultaneous reset during reset, which can also achieve a similar effect. And because the Vcom itself also undergoes a reverse jump before reset, the optimal jump voltage of Vcom_Odd and Vcom_Even can also be reduced. The Vcom voltage as the Reset signal source can jump to Vop_max / 2+Vcom and Vcom-Vop_max_ / 2 respectively when the polarity is positive and negative. And because the Reset signal is merged into one, the layout is easier, the number of control signal channels is reduced, and the complexity of timing control is simplified. Example

[0044] like Figure 5 As shown, the present application also provides another preferred embodiment, the LCD pixel driving circuit can also be configured as follows: the pre-storage capacitor Cs1, the holding capacitor Cs2 and the end of the liquid crystal capacitor Clc away from the transistor of the first pixel driving unit and the second pixel driving unit are all coupled to the same common electrode line; the second source and drain of the third transistor T3 of the first pixel driving unit are coupled to the first global signal line VREF-Odd, and the second source and drain of the third transistor T3 of the second pixel driving unit are coupled to the second global signal line VREF-Even.

[0045] Further, in this embodiment, if Figure 6 As shown, when the data signal of the first pixel driving unit is configured as a positive polarity potential and the data signal of the second pixel driving unit is configured as a negative polarity potential, the first global signal in the frame is configured as a high potential and the second global signal is configured as a low potential; when the data signal of the first pixel driving unit is configured as a negative polarity potential and the data signal of the second pixel driving unit is configured as a positive polarity potential, the first global signal in the frame is configured as a low potential and the second global signal is configured as a high potential.

[0046] Furthermore, the high potential of the global signal is configured as: common voltage Vcom+maximum liquid crystal operating voltage Vop_max; the low potential of the global signal is configured as: common voltage Vcom-maximum liquid crystal operating voltage Vop_max.

[0047] In this embodiment, only separate VREF_Odd and VREF2_Even signal lines are used as the signal source for resetting the odd and even columns, respectively, and provided by the timing control IC or other signal generation units, and similar effects can also be achieved. The advantage of this embodiment is that the Vcom signal does not need to change during operation, and the stability is better. However, due to the addition of additional signal lines, the aperture ratio may be affected.

[0048] In summary, each embodiment of the present application describes the driving timing and mechanism in a column inversion manner, but it can also be expanded to row inversion, dot inversion, multi-column inversion, multi-row inversion and other polarity inversion methods. There is no obvious difference in the driving principle, which is to reset the pixels with positive and negative polarity inversion to different potentials, preferably Vop_max for positive polarity and -Vop_max for negative polarity, which will not be described in detail. Therefore, the adaptive settings of the circuit and driving timing in each embodiment brought about by the above-mentioned column inversion method should not be regarded as limiting the scope of protection of the present application.

[0049] The above is an LCD pixel driving circuit for color sequential display provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0050] Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented with a software module executed by a hardware or processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

Claims

1. An LCD pixel driving circuit for color sequential display, characterized in that: At least: A first pixel driving unit and a second pixel driving unit, each of which includes a first transistor (T1), a pre-storage capacitor (Cs1), a second transistor (T2), a holding capacitor (Cs2), a third transistor (T3) and a liquid crystal capacitor (Clc), wherein: The first source and drain of the first transistor (T1) are coupled to a data signal line (Data), the gate is coupled to a control signal line (Scan), and the second source and drain are coupled to the first source and drain of the second transistor (T2) and one end of a pre-storage capacitor (Cs1); the gate of the second transistor (T2) is coupled to a transfer signal line (Tran), and the second source and drain are coupled to the first source and drain of a third transistor (T3), one end of a holding capacitor (Cs2), and one end of a liquid crystal capacitor (Clc); The pre-storage capacitor (Cs1), the holding capacitor (Cs2) and the liquid crystal capacitor (Clc) of the first pixel driving unit are coupled to the first common electrode line (Vcom-Odd) at one end away from the transistor, and the pre-storage capacitor (Cs1), the holding capacitor (Cs2) and the liquid crystal capacitor (Clc) of the second pixel driving unit are coupled to the second common electrode line (Vcom-Even) at one end away from the transistor; The gate of the third transistor (T3) of the first pixel driving unit is coupled to the first reset signal line (Reset-Odd), and the second source and drain are coupled to the second common electrode line (Vcom-Even); the gate of the third transistor (T3) of the second pixel driving unit is coupled to the second reset signal line (Reset-Even), and the second source and drain are coupled to the first common electrode line (Vcom-Odd).

2. The LCD pixel driving circuit according to claim 1, characterized in that: During the backlight on time, the first transistor (T1) is controlled to be turned on based on a control signal, and the first transistor (T1) outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor (Cs1) until all pixels complete voltage pre-storage.

3. The LCD pixel driving circuit according to claim 1, characterized in that: When the backlight is turned off in frame N: First, after the second common voltage jumps to a high potential, the first reset signal jumps to a high potential, and the liquid crystal capacitor (Clc) and the holding capacitor (Cs2) of the first pixel driving unit are reset based on the third transistor (T3); After the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, after the first common voltage jumps to a low potential, the second reset signal jumps to a high potential, completing the resetting of the second pixel driving unit; After the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and a voltage required for the liquid crystal to flip a target angle is formed on the liquid crystal capacitor (Clc) based on the second transistor (T2); When entering the N+1th frame, the backlight is turned on.

4. The LCD pixel driving circuit according to claim 3, characterized in that: When the backlight is turned off in the N+1th frame: First, after the second common voltage jumps to a low potential, the first reset signal jumps to a high potential, and the liquid crystal capacitor (Clc) and the holding capacitor (Cs2) of the first pixel driving unit are reset based on the third transistor (T3); After the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, after the first common voltage jumps to a high potential, the second reset signal jumps to a high potential, completing the resetting of the second pixel driving unit; After the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and a voltage required for the liquid crystal to flip a target angle is formed on the liquid crystal capacitor (Clc) based on the second transistor (T2); When entering the N+2th frame, the backlight is turned on.

5. The LCD pixel driving circuit according to claim 3 or 4, characterized in that: When the backlight is turned on in the Nth frame, the data signal of the first pixel driving unit is configured as a positive polarity potential, and the data signal of the second pixel driving unit is configured as a negative polarity potential; When the backlight is turned on in the (N+1)th frame, the data signal of the first pixel driving unit is configured as a negative polarity potential, and the data signal of the second pixel driving unit is configured as a positive polarity potential.

6. The LCD pixel driving circuit according to claim 1, characterized in that: The LCD pixel driving circuit may also be configured as: The gate of the third transistor (T3) of the first pixel driving unit and the gate of the third transistor (T3) of the second pixel driving unit are both coupled to the same reset signal line.

7. The LCD pixel driving circuit according to claim 6, characterized in that: When the second common voltage jumps to a high potential and the first common voltage jumps to a low potential, or when the second common voltage jumps to a low potential and the first common voltage jumps to a high potential, The first reset signal jumps to a high potential, and synchronously completes the resetting of the liquid crystal capacitor (Clc) and the holding capacitor (Cs2) of the first pixel driving unit and the second pixel driving unit.

8. The LCD pixel driving circuit according to claim 1, characterized in that: The LCD pixel driving circuit may also be configured as: The pre-storage capacitor (Cs1), the holding capacitor (Cs2) and the liquid crystal capacitor (Clc) of the first pixel driving unit and the second pixel driving unit are coupled to the same common electrode line at one end away from the transistor; The second source and drain of the third transistor (T3) of the first pixel driving unit is coupled to the first global signal line (VREF-Odd), and the second source and drain of the third transistor (T3) of the second pixel driving unit is coupled to the second global signal line (VREF-Even).

9. The LCD pixel driving circuit according to claim 8, characterized in that: When the data signal of the first pixel driving unit is configured as a positive polarity potential and the data signal of the second pixel driving unit is configured as a negative polarity potential, the first global signal in the frame is configured as a high potential and the second global signal is configured as a low potential; When the data signal of the first pixel driving unit is configured as a negative polarity potential and the data signal of the second pixel driving unit is configured as a positive polarity potential, the first global signal in this frame is configured as a low potential and the second global signal is configured as a high potential.

10. The LCD pixel driving circuit according to claim 1, characterized in that: The high potential of the global signal is configured as: common voltage (Vcom) + maximum liquid crystal operating voltage (Vop-max); the low potential of the global signal is configured as: common voltage (Vcom) - maximum liquid crystal operating voltage (Vop-max).

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