Address processing system and address adjusting method

Abstract

The invention relates to the field of memorizers, in particular to an address processing system and an address adjusting method.The address processing system comprises a controller and a storage array; the selection circuit is provided with a selection end, two input ends and an output end; the selection end is used for receiving a bypass control signal transmitted by the controller, one of the two input ends is used for receiving an initial address, the other one of the two input ends is used for receiving a replacement address, and the output end is used for outputting an addressing address to the storage array; the selection circuit is configured to output the initial address or the replacement address as the addressing address according to the bypass control signal. The address processing system provided by the embodiment of the invention is used for shortening the read-write time of the storage controller.

Description

Technical Field

[0001] The present disclosure relates to the field of memory, and in particular to an address processing system and an address adjustment method. Background Art

[0002] Memory is a component of a computer that implements memory functions and is used to store programs and data. It is an important component of a microcomputer system. The larger the memory capacity, the more information can be stored, and the more fully the computer's processing capabilities can be demonstrated.

[0003] Each storage particle includes a plurality of storage units. However, due to the limitation of production technology, the performance of each storage unit in the storage particle is different. The storage function of some storage units is abnormal, which reduces the yield of the storage particle.

[0004] In order to improve the yield of storage particles, some redundant storage cells are usually added to the storage particles, and the addresses of failed storage cells in the storage array are replaced with the addresses of redundant storage cells. Before leaving the factory, each storage cell of the storage particle will be scanned, and the address of the failed storage cell will be stored in the content-addressable memory (CAM). All addresses input by the storage controller when performing read / write operations must be processed by the content-addressable memory, that is, the address replacement of the failed storage cell is completed. Summary of the invention

[0005] The purpose of the embodiments of the present disclosure is to provide an address processing system and an address adjustment method to shorten the read and write time of a storage controller.

[0006] An embodiment of the present disclosure provides an address processing system, comprising: a controller and a storage array; a selection circuit having a selection end, two input ends, and an output end; the selection end is used to receive a bypass control signal transmitted by the controller, one of the two input ends is used to receive an initial address, the other of the two input ends is used to receive a replacement address, and the output end is used to output an addressing address to the storage array; the selection circuit is configured to: output the initial address or the replacement address as the addressing address according to the bypass control signal.

[0007] In some embodiments, the address processing system further includes: a mode register connected to the selection end and configured to: receive a bypass configuration command transmitted by the controller, and output the bypass control signal according to the bypass configuration command.

[0008] In some embodiments, the controller is configured to output the bypass control signal to the output terminal according to the initial address.

[0009] In some embodiments, the controller is configured to: determine whether the initial address belongs to a preset address range; when the initial address belongs to the preset address range, send the bypass control signal to configure the selection circuit to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, send the bypass control signal to configure the selection circuit to output the addressing address based on the initial address.

[0010] In some embodiments, the controller is configured to: obtain the original bit error rate that the system requires to be controlled; when the original bit error rate is greater than a preset value, send the bypass control signal to configure the selection circuit to output the addressing address based on the initial address; when the original bit error rate is less than a preset value, send the bypass control signal to configure the selection circuit to output the addressing address based on the replacement address.

[0011] In some embodiments, the selection circuit is disposed in a memory chip.

[0012] In some embodiments, the address processing system further includes: an address processing circuit, wherein the address processing circuit is configured to: receive an initial address, and output the replacement address corresponding to the initial address based on an address mapping relationship.

[0013] The presently disclosed embodiment also provides an address adjustment method, which is applied to the address processing system provided in the above embodiment, including: outputting an initial address and a bypass control signal to a storage chip through a controller; a selection circuit of the storage chip selects, based on the bypass control signal, to output an addressing address to a storage array of the storage chip based on the initial address or a replacement address mapped from the initial address.

[0014] In some embodiments, the address adjustment method also includes: the controller outputs the bypass control signal based on the address interval to which the initial address belongs; when the initial address belongs to the preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address; when the initial address does not belong to the preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the initial address.

[0015] In some embodiments, the address adjustment method also includes: the controller outputs the bypass control signal based on the original bit error rate controlled by the system requirement; when the original bit error rate is greater than a preset value, the bypass control signal controls the selection circuit to output the addressing address based on the initial address; when the original bit error rate is less than a preset value, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address.

[0016] The address processing system provided by the present disclosure determines whether to output a replacement address as an addressing address through a bypass control signal, or determines whether to output an initial address as an addressing address through a bypass control signal, thereby improving the flexibility of addressing of a storage array. For example, in the case where the accuracy of data reading and writing needs to be ensured, the replacement address is output as the addressing address; in the case where the data reading and writing rate needs to be ensured, the initial address is output as the addressing address to shorten the reading and writing time of the storage controller.

[0017] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of the structure of an address processing system provided in an embodiment of the present disclosure;

[0020] Figure 2 It is a structural schematic diagram of an address processing system for obtaining a replacement address based on a content addressable memory provided by an embodiment of the present disclosure;

[0021] Figure 3 It is a structural schematic diagram corresponding to a bypass control signal generation method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0023] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0024] In this disclosure, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this disclosure as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the invention can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this disclosure.

[0025] At the same time, the present disclosure uses specific words to describe the embodiments of the present disclosure. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics in one or more embodiments of the present disclosure may be appropriately combined.

[0026] Similarly, it should be noted that in order to simplify the description of the disclosure and thus facilitate the understanding of one or more disclosed embodiments, in the foregoing description of the embodiments of the disclosure, multiple features are sometimes grouped into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the disclosed object requires more features than those mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0027] In some embodiments, numbers are used to describe the number of components and attributes. It should be understood that such numbers used to describe the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, numerical parameters should consider specifying significant digits and adopting a general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present disclosure are approximate values, in specific embodiments, such numerical values ​​are set as accurately as possible within the feasible range.

[0028] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, etc., cited in this disclosure are hereby incorporated by reference in their entirety, except for application history documents that are inconsistent with or conflicting with the content of this disclosure, and documents that limit the broadest scope of the claims of this disclosure (currently or later attached to this disclosure). It should be noted that if the descriptions, definitions, and / or use of terms in the accompanying materials of this disclosure are inconsistent or conflicting with the examples of this disclosure, the descriptions, definitions, and / or use of terms in this disclosure shall prevail.

[0029] Based on the background technology, it is known that each storage particle includes multiple storage units, and due to the limitation of production technology, the performance of each storage unit in the storage particle is different, and the storage function of some storage units is abnormal, which reduces the yield of the storage particles. In order to improve the yield of storage particles, some redundant storage units are usually added to the storage particles, and the addresses of the failed storage units in the storage array are replaced with the addresses of the redundant storage units.

[0030] When the storage controller sends a read command or a write command, the storage particle will transmit the received address to the content-addressable memory (CAM) for processing, and the content-addressable memory will determine whether the address is mapped to a new storage unit. If the address is mapped to a new address, the content-addressable memory will replace the address with the address of the new storage unit and transmit the processed address to the storage array, which reads and writes based on the processed address.

[0031] Since all addresses input by the storage controller to the storage particles are processed by the content-addressable memory, this increases the waiting time for the storage array to receive the address, increases the read latency or write latency of all storage units, and also reduces the data bandwidth when continuously reading / writing the same storage block.

[0032] An embodiment of the present disclosure provides an address processing system, comprising: a controller and a storage array; a selection circuit having a selection end, two input ends, and an output end; the selection end is used to receive a bypass control signal transmitted by the controller, one of the two input ends is used to receive an initial address, the other of the two input ends is used to receive a replacement address, and the output end is used to output an addressing address to the storage array; the selection circuit is configured to: output the initial address or the replacement address as the addressing address according to the bypass control signal.

[0033] The address processing system provided by the embodiment of the present disclosure determines whether to output the replacement address as the addressing address through the bypass control signal, or determines whether to output the initial address as the addressing address through the bypass control signal, thereby improving the flexibility of storage array addressing. For example, in the case where the accuracy of data reading and writing needs to be guaranteed, the replacement address is output as the addressing address; in the case where the data reading and writing rate needs to be guaranteed, the initial address is output as the addressing address to shorten the reading and writing time of the storage controller.

[0034] The address processing system provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows.

[0035] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the address processing system provided in this embodiment. The address processing system 100 includes: a controller 201 , a storage array 102 and a selection circuit 101 .

[0036] Among them, the controller 201 is a storage controller (Control store). The storage controller is a device that performs necessary control on the access to the memory according to certain timing rules, including the control of address signals, data signals and various command signals, so that the master device (the device accessing the memory) can use the storage resources on the memory according to its own requirements. The main function of the storage controller is to convert the interface, convert the read and write commands issued by the master device into signals that the memory can recognize, and complete the address decoding and data format conversion (such as data bit width) between the master device and the memory.

[0037] The memory array 102 includes a plurality of memory cells arranged in an array, and also includes a plurality of word lines and a plurality of bit lines. The word lines are used to locate the rows of the memory cells, and the bit lines are used to locate the columns of the memory cells. Each word line corresponds to a corresponding word line address, and each bit line corresponds to a corresponding bit line address. A memory cell can be accurately located by a word line address and a bit line address, so that data can be written or read from the memory cell. The memory array 102 drives the row driver and the column driver through the word line address and the bit line address in the addressing address to select the target memory cell.

[0038] Ideally, after all the memory cells in the memory array 102 are formed based on the same process, the performance of the memory cells is consistent. However, due to the limitations of actual production technology, defective memory cells may exist in the formed memory array 102. The performance of the defective memory cells is lower than that of normal memory cells in terms of data storage capability, which greatly affects the yield of the memory.

[0039] In order to improve the yield of storage particles, some redundant storage cells are usually added to the storage particles, and the addresses of failed storage cells in the storage array 102 are replaced with the addresses of redundant storage cells. After the address replacement, the array composed of redundant storage cells replacing defective storage cells improves the yield of the memory, but correspondingly increases the read latency or write latency of all storage cells, and also reduces the data bandwidth when continuously reading and writing the same storage block.

[0040] The selection circuit 101 has a selection terminal and two input terminals; the selection terminal is used to receive a bypass control signal, one of the two input terminals is used to receive an initial address, and the other of the two input terminals is used to receive a replacement address. The replacement address is used to adjust the address of the defective storage unit to the initial address. The selection circuit 101 is configured to output an addressing address based on the initial address or the replacement address according to the bypass control signal.

[0041] The address processing system 100 provided in this embodiment determines whether to output the replacement address as the addressing address through the bypass control signal, or determines whether to output the initial address as the addressing address through the bypass control signal, thereby improving the flexibility of the storage array addressing. For example, when the accuracy of data reading and writing needs to be guaranteed, the replacement address is output as the addressing address; when the data reading and writing rate needs to be guaranteed, the initial address is output as the addressing address to shorten the reading and writing time of the storage controller.

[0042] In some embodiments, the selection circuit 101 includes a selector, whose first input terminal S1 and second input terminal S2 are respectively connected to two input terminals of the selection circuit 101, whose output terminal is connected to the output terminal of the selection circuit 101, and whose control terminal S0 is connected to the selection terminal of the selection circuit.

[0043] It should be noted that, for clarity of description, in the subsequent description, the first input terminal S1 of the selector is used to receive the initial address, and the second input terminal S2 of the selector is used to receive the replacement address.

[0044] In some embodiments, the initial address is output by the controller 201, that is, the first input terminal S1 is connected to the controller 201 to obtain the initial address; the replacement address can be understood as the address generated after the content addressable memory processes the initial address, and the addressing address is used to address the storage array 102 to perform a read operation or a write operation on a specific storage unit.

[0045] Continue to refer Figure 1In one example, when the bypass control signal is "1", the selector outputs the addressing address based on the initial address inputted by the first input terminal S1; when the bypass control signal is "0", the selector outputs the addressing address based on the replacement address inputted by the second input terminal S2. Alternatively, when the bypass control signal is "0", the selector outputs the addressing address based on the initial address inputted by the first input terminal S1; when the bypass control signal is "1", the selector outputs the addressing address based on the replacement address inputted by the second input terminal S2.

[0046] In some embodiments, the address processing system 100 further includes an address processing circuit configured to receive an initial address and output a replacement address based on the initial address.

[0047] In one example, the address processing circuit may process the initial address based on a preset processing method to obtain the replacement address. The preset processing method may be to increase or decrease the initial address by a preset value, or to invert one or more bits of the initial address.

[0048] In some embodiments, the address processing circuit is configured to output a replacement address corresponding to the initial address based on an address mapping relationship.

[0049] In one example, the address processing circuit stores an address mapping relationship between the initial address and the replacement address. The address processing circuit outputs the replacement address corresponding to the initial address based on the received initial address and the address mapping relationship.

[0050] refer to Figure 2 , Figure 2 The address processing circuit is set based on the content addressable memory (CAM, 103), and the content addressable memory 103 is used to replace the initial address to obtain the replacement address.

[0051] It should be noted that in the subsequent description of this embodiment, based on Figure 2 The address processing system 100 is specifically described based on examples, and does not constitute a limitation on the method of generating replacement addresses. In other embodiments, the replacement addresses can also be generated by the controller 201, or address replacement can be achieved by registers.

[0052] In some embodiments, reference Figure 3 , Figure 3The address processing system 100 further includes a mode register 104, which is connected to the selection end of the selection circuit 101, and is configured to receive a bypass configuration command transmitted by the controller 201, and output a bypass control signal according to the bypass configuration command.

[0053] The bypass configuration command is output based on the output terminal of the controller 201 . The bypass configuration command is used to control the mode register 104 to output the value of the bypass control signal, thereby realizing the control of the selection circuit 101 .

[0054] Wherein, when the bypass configuration command is "0", the value of the bypass control signal output by the configuration mode register 104 is "1", thereby controlling the selector to output the addressing address based on the initial address input by the first input terminal S1; when the bypass configuration command is "1", the value of the bypass control signal output by the configuration mode register 104 is "0", thereby controlling the selector to output the addressing address based on the replacement address input by the second input terminal S2. Alternatively, when the bypass configuration command is "1", the value of the bypass control signal output by the configuration mode register 104 is "1", thereby controlling the selector to output the addressing address based on the initial address input by the first input terminal S1; when the bypass configuration command is "0", the value of the bypass control signal output by the configuration mode register 104 is "0", thereby controlling the selector to output the addressing address based on the replacement address input by the second input terminal S2.

[0055] In some embodiments, the controller 201 is configured to output a bypass control signal to the output terminal according to the initial address.

[0056] In some embodiments, the controller 201 determines whether to send a bypass control signal based on whether the initial address meets a preset condition, wherein the preset condition may include whether the initial address belongs to a preset address interval, the raw bit error rate (RBER) required to be controlled by the system, whether an external command is received, etc.

[0057] In one example, the controller 201 is configured to: determine whether the initial address belongs to a preset address range; when the initial address belongs to the preset address range, send a bypass control signal to configure the selection circuit 101 to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, send a bypass control signal to configure the selection circuit 101 to output the addressing address based on the initial address.

[0058] In this example, the preset address interval is set based on the abnormal address interval, and the amount of data in the abnormal address interval is generally smaller than the amount of data between normal address areas, so as to reduce the difficulty of judgment of the controller 201 and reduce the judgment time of the controller 201. In one example, the preset address interval can also be set based on the normal address interval. In this case, the controller 201 is configured to: determine whether the initial address belongs to the preset address interval; when the initial address belongs to the preset address interval, send a bypass control signal to configure the selection circuit 101 to output the addressing address based on the initial address; when the initial address does not belong to the preset address interval, send a bypass control signal to configure the selection circuit 101 to output the addressing address based on the replacement address.

[0059] For some storage particles with abnormal performance, the storage units are concentrated in an address range, or the storage units with abnormal performance are concentrated in an address range through address remapping. When accessing the storage particles, the storage controller can first determine whether the access address is in this address range. If it is not in this address range, the selection circuit 101 can be controlled by the command or mode register. The selection circuit 101 generates an addressing address based on the initial address, which reduces the address processing time and reduces the read latency or write latency.

[0060] In one example, the controller 201 is configured to: obtain the original bit error rate RBER required to be controlled by the system; when the original bit error rate RBER is greater than a preset value, send a bypass control selection to configure the selection circuit 101 to output an addressing address based on the initial address; when the original bit error rate RBER is less than a preset value, send a bypass control selection to configure the selection circuit 101 to output an addressing address based on a replacement address.

[0061] By obtaining the original bit error rate RBER required by the system, when the original bit error rate RBER required by the system is high, the addressing address is directly output through the initial address to improve the addressing speed of the memory, greatly reducing the read latency time or write latency time; when the original bit error rate RBER required by the system is low, the addressing address is output through the preferred address to ensure the processing accuracy of the memory.

[0062] In one example, the controller 201 is configured to send a bypass control signal based on an external command to configure the selection circuit 101 to output an addressing address based on the initial address.

[0063] Specifically, the user can directly control the selection circuit 101 through commands or mode registers. The selection circuit 101 generates an addressing address based on the initial address, which reduces the address processing time, reduces the read latency or write latency, and can improve the bandwidth of read data.

[0064] By avoiding the content-addressable memory from processing and replacing the initial address, the time for a single read or write operation can be shortened by at least about 5ns. For scenarios of continuous read or write operations, the read latency or write latency is greatly reduced.

[0065] In some embodiments, the selection circuit 101 is disposed in a memory chip.

[0066] As for the memory, the memory includes a first memory controller and a plurality of memory chips. By setting the selection circuit 101 in the memory chip, different control logics of different memory chips are implemented, which greatly improves the flexibility of data storage in the memory.

[0067] In addition, for the memory mentioned in this embodiment, the memory can be a random access memory (Random Access Memory, RAM), for example, a static random access memory (Static Random Access Memory, SRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a synchronous dynamic memory SDRAM, etc., a read only memory (Read Only Memory, ROM), a flash memory (flash memmory) or a phase change memory PCM, etc.

[0068] The address processing system provided in this embodiment determines whether to output the replacement address as the addressing address through the bypass control signal, or determines whether to output the initial address as the addressing address through the bypass control signal, thereby improving the flexibility of storage array addressing. For example, in the case where the accuracy of data reading and writing needs to be guaranteed, the replacement address is output as the addressing address; in the case where the data reading and writing rate needs to be guaranteed, the initial address is output as the addressing address to shorten the reading and writing time of the storage controller.

[0069] It should be noted that, in the absence of conflict, the features disclosed in the address processing system 100 provided in the above embodiments may be randomly combined to obtain a new embodiment of the address processing system 100 .

[0070] Another embodiment of the present disclosure further provides an address adjustment method to shorten the read and write time of a storage controller.

[0071] Specifically, the address adjustment method is applied to the address processing system 100 provided in the above embodiment, and includes step S1 and step S2.

[0072] Step S1, outputting an initial address and a bypass control signal to a memory chip through a controller.

[0073] The initial address is output by the controller 201. The bypass control signal is used to configure the selection circuit to output the addressing address based on the initial address or the replacement address. In one example, the bypass control signal is output by the controller 201. In one example, the mode register 104 outputs the bypass control signal according to the bypass configuration command. For example, when the bypass configuration command is "0", the value of the bypass control signal output by the configuration mode register 104 is "1"; when the bypass configuration command is "1", the value of the bypass control signal output by the configuration mode register 104 is "0". Alternatively, when the bypass configuration command is "1", the value of the bypass control signal output by the configuration mode register 104 is "1"; when the bypass configuration command is "0", the value of the bypass control signal output by the configuration mode register 104 is "0".

[0074] Step S2, the selection circuit of the memory chip selects, based on the bypass selection signal, to output an addressing address to the memory array of the memory chip based on the initial address or the replacement address mapped from the initial address.

[0075] The replacement address is obtained after the address processing circuit replaces the initial address, and can be understood as an address generated after the content addressable memory processes the initial address.

[0076] For example, when the bypass control signal is "1", the control selector generates an addressing address based on the initial address inputted from the first input terminal S1; when the bypass control signal is "0", the control selector generates an addressing address based on the replacement address inputted from the second input terminal S2. Alternatively, when the bypass control signal is "0", the control selector generates an addressing address based on the initial address inputted from the first input terminal S1; when the bypass control signal is "1", the control selector generates an addressing address based on the replacement address inputted from the second input terminal S2.

[0077] In some embodiments, before executing step S1, the address adjustment method further includes step S0-1, obtaining a bypass control signal based on a preset address interval.

[0078] Specifically, the controller outputs a bypass control signal based on the address interval to which the initial address belongs; when the initial address belongs to the preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address; when the initial address does not belong to the preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the initial address.

[0079] In one example, it is determined whether the initial address belongs to a preset address range; when the initial address belongs to the preset address range, a bypass control signal is sent to configure the selection circuit 101 to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, a bypass control signal is sent to configure the selection circuit 101 to output the addressing address based on the initial address.

[0080] In one example, the storage units with abnormal performance of some storage particles are concentrated in an address range, or the storage units with abnormal performance are concentrated in an address range through address remapping. When accessing the storage particles, the storage controller can first determine whether the access address is in this address range. If it is not in this address range, the selection circuit 101 can be controlled by a command or mode register. The selection circuit 101 generates an addressing address based on the initial address, which reduces the address processing time and reduces the read latency or write latency.

[0081] In some embodiments, before executing step S1, the address adjustment method further includes step S0-2, obtaining a bypass control signal based on an original bit error rate RBER controlled by the system.

[0082] Specifically, the controller outputs a bypass control signal based on the original bit error rate controlled by the system; when the original bit error rate is greater than a preset value, the bypass control signal controls the selection circuit to output an addressing address based on an initial address; when the original bit error rate is less than a preset value, the bypass control signal controls the selection circuit to output an addressing address based on a replacement address.

[0083] In one example, an original bit error rate RBER required to be controlled by the system is obtained; when the original bit error rate RBER is greater than a preset value, a bypass control selection is sent to configure the selection circuit 101 to output an addressing address based on the initial address; when the original bit error rate RBER is less than a preset value, a bypass control selection is sent to configure the selection circuit 101 to output an addressing address based on a replacement address.

[0084] By obtaining the original bit error rate RBER required by the system, when the original bit error rate RBER required by the system is high, the addressing address is directly output through the initial address to improve the addressing speed of the memory, greatly reducing the read latency time or write latency time; when the original bit error rate RBER required by the system is low, the addressing address is output through the preferred address to ensure the processing accuracy of the memory.

[0085] In one example, a bypass control signal is sent based on an external command to configure the selection circuit 101 to output an addressing address based on the initial address.

[0086] Specifically, the user can directly control the selection circuit 101 through commands or mode registers. The selection circuit 101 generates an addressing address based on the initial address, which reduces the address processing time, reduces the read latency or write latency, and can improve the bandwidth of read data.

[0087] By avoiding the content-addressable memory from processing and replacing the initial address, the time for a single read or write operation can be shortened by at least about 5ns. For scenarios of continuous read or write operations, the read latency or write latency is greatly reduced.

[0088] Ideally, after all the memory cells in the memory array 102 are formed based on the same process, the performance of the memory cells is consistent. However, due to the limitations of actual production technology, defective memory cells may exist in the formed memory array 102. The performance of the defective memory cells is lower than that of normal memory cells in terms of data storage capability, which greatly affects the yield of the memory.

[0089] In order to improve the yield of storage particles, some redundant storage cells are usually added to the storage particles, and the addresses of failed storage cells in the storage array are replaced with the addresses of redundant storage cells. After address replacement, the array composed of redundant storage cells replacing defective storage cells improves the yield of the memory, but it also increases the read latency or write latency of all storage cells accordingly, and also reduces the data bandwidth when continuously reading and writing the same storage block.

[0090] The address adjustment method provided in this embodiment determines whether to output the replacement address as the addressing address through the bypass control signal, or determines whether to output the initial address as the addressing address through the bypass control signal, thereby improving the flexibility of the storage array addressing. For example, when the accuracy of data reading and writing needs to be guaranteed, the replacement address is output as the addressing address; when the data reading and writing rate needs to be guaranteed, the initial address is output as the addressing address to shorten the reading and writing time of the storage controller.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0092] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present disclosure. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present disclosure. Such modifications, improvements and corrections are suggested in the present disclosure, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present disclosure.

[0093] The above is a detailed introduction to an address processing system and an address adjustment method provided by an embodiment of the present disclosure. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present disclosure, there will be changes in the specific implementation method and application scope. In summary, it can be seen that the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. An address processing system, characterized in that: include: controllers and storage arrays; A selection circuit having a selection terminal, two input terminals, and an output terminal; The selection end is used to receive a bypass control signal transmitted by the controller, one of the two input ends is used to receive an initial address, the other of the two input ends is used to receive a replacement address, and the output end is used to output an addressing address to the storage array; The selection circuit is configured to output the initial address or the replacement address as the addressing address according to the bypass control signal.

2. The address processing system according to claim 1, characterized in that: Also includes: The mode register is connected to the selection end and is configured to: receive a bypass configuration command transmitted by the controller, and output the bypass control signal according to the bypass configuration command.

3. The address processing system according to claim 1, characterized in that: The controller is configured to output the bypass control signal to the output terminal according to the initial address.

4. The address processing system according to any one of claims 1 to 3, characterized in that: The controller is configured to: Determining whether the initial address belongs to a preset address range; When the initial address belongs to the preset address interval, sending the bypass control signal to configure the selection circuit to output the addressing address based on the replacement address; When the initial address does not belong to the preset address interval, the bypass control signal is sent to configure the selection circuit to output the addressing address based on the initial address.

5. The address processing system according to any one of claims 1 to 3, characterized in that: The controller is configured to: Obtain the original bit error rate that the system requires to control; When the original bit error rate is greater than a preset value, sending the bypass control signal to configure the selection circuit to output the addressing address based on the initial address; When the original bit error rate is less than a preset value, the bypass control signal is sent to configure the selection circuit to output the addressing address based on the replacement address.

6. The address processing system according to claim 1, characterized in that: The selection circuit is arranged in the memory chip.

7. The address processing system according to claim 1, characterized in that: Also includes: The address processing circuit is configured to: receive an initial address, and output the replacement address corresponding to the initial address based on an address mapping relationship.

8. An address adjustment method, applied to the address processing system according to any one of claims 1 to 7, characterized in that: include: Outputting an initial address and a bypass control signal to the memory chip through the controller; The selection circuit of the memory chip selects, based on the bypass control signal, to output an addressing address to a memory array of the memory chip based on the initial address or a replacement address mapped from the initial address.

9. The address adjustment method according to claim 8, characterized in that: The address adjustment method further includes: The controller outputs the bypass control signal based on the address interval to which the initial address belongs; When the initial address belongs to the preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address; When the initial address does not belong to the preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the initial address.

10. The address adjustment method according to claim 8, characterized in that: The address adjustment method further includes: The controller outputs the bypass control signal based on the original bit error rate controlled by the system; When the original bit error rate is greater than a preset value, the bypass control signal controls the selection circuit to output the addressing address based on the initial address; When the original bit error rate is less than a preset value, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address.

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