Memory, access method thereof and electronic equipment

Abstract

The embodiment of the invention provides a memory, an access method thereof and electronic equipment. A read transistor of the memory comprises a first semiconductor layer, a first gate insulating layer comprising a ferroelectric material layer, and a first gate electrode; the write transistor comprises a second grid electrode and a second semiconductor layer; the read word line and the read bit line are respectively connected with the first semiconductor layer; the writing bit line and the first grid electrode are respectively connected with the second semiconductor layer, and the writing word line is connected with the second grid electrode; when data are written, the write transistor is controlled to be conducted through the write word line, the data are written into the ferroelectric material layer through the write bit line, and the read word line and the read bit line have the same voltage; before reading operation, all the write transistors are turned on, first voltage is applied to all the first grids through the corresponding write bit lines, and all the read transistors are turned off; when the data is read, different voltages are applied to the read word line and the read bit line, and the written data is determined according to the data sensed on the read bit line. The embodiment of the invention can effectively improve the current sharing problem.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a memory and an access method thereof, and an electronic device. Background Art

[0002] Memory is the main medium for storing data in computers. With the development and progress of storage technology, storage devices are constantly moving towards miniaturization and high integration, and higher requirements are placed on the performance of storage devices. Summary of the invention

[0003] The present application proposes a memory and an access method thereof, and an electronic device, based on a read transistor whose gate insulating layer is a ferroelectric material, combined with the read-write operation method proposed in the present application, to effectively improve or solve the current sharing problem.

[0004] In a first aspect, an embodiment of the present application provides a memory, comprising a substrate and a plurality of memory cells arranged in an array on the substrate, a plurality of read word lines, a plurality of read bit lines, a plurality of write word lines, and a plurality of write bit lines, wherein the memory cells comprise read transistors and write transistors;

[0005] The read transistor includes a first semiconductor layer, a first gate insulating layer connected to the first semiconductor layer, and a first gate connected to the first gate insulating layer, wherein the first gate insulating layer includes a ferroelectric material layer; the write transistor includes a second gate and a second semiconductor layer, wherein the second semiconductor layer is insulated from the second gate;

[0006] The read word line and the read bit line are respectively connected to the first semiconductor layer; the write bit line and the first gate are respectively connected to the second semiconductor layer, and the write word line is connected to the second gate;

[0007] When a data writing operation is performed on a storage unit to be written with data, the write transistor is turned on by controlling the write word line corresponding to the storage unit, and the data is written into the ferroelectric material layer by the write bit line corresponding to the storage unit, wherein the voltage of the read word line and the read bit line are the same voltage;

[0008] Before the read operation, at least apply a turn-on voltage to all other write word lines except the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and apply a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off;

[0009] When performing a data reading operation, different voltages are applied to a read word line and a read bit line connected to a storage cell to be written with data, and the write data of the storage cell is determined according to data sensed on the read bit line.

[0010] In some optional embodiments of the present application, after applying a turn-on voltage to all write word lines other than the write word line connected to at least the storage unit to which data is to be written, so that the corresponding write transistors are turned on, a first voltage is applied to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off, and before performing a data reading operation, the write transistor is controlled to be turned on through the write word line of the storage unit to which data is to be written, so that a second voltage is applied to the first gate of the read transistor through the write bit line, so that during the reading operation phase, when the written data is 1, the read transistor is turned on, and when the written data is 0, the read transistor is turned off.

[0011] In some optional embodiments of the present application, before performing a data read operation, a turn-on voltage is applied to all write word lines to turn on the corresponding write transistors, and a first voltage is applied to the first gate of each read transistor through the write bit line corresponding to each write transistor to turn off the read transistors of all storage cells.

[0012] In some optional embodiments of the present application,

[0013] A write word line connects the write transistors of the plurality of memory cells;

[0014] A read word line connects the read transistors of the plurality of memory cells;

[0015] Each write transistor is connected to a different write bit line;

[0016] Each of the read transistors is connected to a different read bit line;

[0017] Each read bit line of each memory cell on a read word line can read data of the corresponding memory cell at the same time.

[0018] In some optional embodiments of the present application, the read transistor and the write transistor are arranged sequentially in a direction parallel to the substrate, or are stacked in a direction perpendicular to the substrate.

[0019] In some optional embodiments of the present application, the first semiconductor layer and the second semiconductor layer are both surrounding semiconductor layers, the first gate insulation layer and the first semiconductor layer are sequentially arranged around the side wall of the first gate; the second semiconductor layer is arranged around the side wall of the second gate.

[0020] In some optional embodiments of the present application, the first gate extends along a first direction parallel to the substrate, the second gate extends along a direction perpendicular to the substrate, and an orthographic projection of the first gate on the substrate does not overlap with an orthographic projection of the second gate on the substrate;

[0021] The first gate insulating layer and the first semiconductor layer sequentially wrap at least one end portion of the first gate along the first direction.

[0022] In some optional embodiments of the present application, the first gate insulating layer is in contact with the first gate and the first semiconductor layer respectively;

[0023] The ferroelectric material of the first gate insulating layer includes doped hafnium oxide, and the doping element in the doped hafnium oxide includes at least one of zirconium, silicon, yttrium, aluminum, and lanthanum.

[0024] In some optional embodiments of the present application, a material of at least one of the first semiconductor layer and the second semiconductor layer includes a metal oxide semiconductor material, and the metal element in the metal oxide semiconductor material includes at least one of indium, gallium, zinc, and tin.

[0025] In some optional embodiments of the present application, the write transistor further includes a second gate insulating layer, and the second gate insulating layer is disposed between the second gate electrode and the second semiconductor layer;

[0026] The material of the second gate insulating layer includes a high dielectric constant material, and the high dielectric constant material includes any dielectric material with a dielectric constant value greater than 3.9.

[0027] In some optional embodiments of the present application, the first semiconductor layer and the second semiconductor layer in a memory cell are not connected; and / or,

[0028] The second semiconductor layers of adjacent write transistors on one write word line are not connected to each other.

[0029] In some optional embodiments of the present application, the read word line and the read bit line are both located on a side of the first semiconductor layer away from the first gate, the read bit line is connected to an end of the first semiconductor layer and extends along a second direction parallel to the substrate, and the read word line is disposed around an outer side wall of the first semiconductor layer and extends along a direction perpendicular to the substrate;

[0030] The write bit line and the first gate are arranged at intervals in the first direction and are respectively connected to different regions of the side wall of the second semiconductor layer. The write bit line extends along the second direction, and the write word line extends along a direction perpendicular to the substrate.

[0031] The second direction intersects the first direction.

[0032] In some optional embodiments of the present application, the memory includes multiple layers of first memory cell arrays, each layer of the first memory cell array includes multiple memory cells arranged in an array along a first direction and a second direction;

[0033] One of the read bit lines is connected to a plurality of read transistors in a column of a first memory cell array spaced apart along a second direction;

[0034] One of the write bit lines is connected to a plurality of write transistors in a column spaced apart and distributed along a second direction in a first memory cell array of a layer;

[0035] One of the read word lines connects a plurality of read transistors stacked along a direction perpendicular to the substrate;

[0036] One of the write word lines connects a plurality of write transistors stacked along a direction perpendicular to the substrate;

[0037] The read bit lines corresponding to the read transistors connected to one of the read word lines can read the data of the storage cells in parallel.

[0038] In a second aspect, an embodiment of the present application provides a method for accessing a memory, wherein the memory includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, a plurality of write word lines, and a plurality of storage cells arranged in an array; the storage cell includes a read transistor and a write transistor, the read word line and the read bit line are respectively connected to a first semiconductor layer of the read transistor, the write bit line and a first gate of the read transistor are respectively connected to a second semiconductor layer of the write transistor, the write word line is connected to a second gate of the write transistor, a first gate insulating layer is provided between the first gate and the first semiconductor layer, and the first gate insulating layer includes a ferroelectric material layer;

[0039] The access method of the memory includes a data writing operation and a data reading operation; after the data writing operation and before the data reading operation, the access method further includes:

[0040] Applying a turn-on voltage to at least all other write word lines except the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off;

[0041] Data read operations include:

[0042] Different voltages are applied to a read word line and a read bit line connected to a memory cell to be written with data, and the write data of the memory cell is determined according to data sensed on the read bit line.

[0043] In some optional embodiments of the present application, at least applying a turn-on voltage to all other write word lines other than the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off, including:

[0044] An on voltage is applied to all write word lines to turn on the corresponding write transistors, and a first voltage is applied to the first gate of each read transistor through the write bit line corresponding to each write transistor to turn off the read transistors of all memory cells.

[0045] In some optional embodiments of the present application, after applying a turn-on voltage to all other write word lines other than the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off, and before performing the data reading operation, the access method further includes:

[0046] The write transistor is controlled to be turned on through the write word line of the storage unit to which data is to be written, so as to apply a second voltage to the first gate of the read transistor through the write bit line, so that when the data written in the read operation phase is 1, the read transistor is turned on, and when the data written is 0, the read transistor is turned off.

[0047] In some optional embodiments of the present application, after applying a turn-on voltage to all other write word lines other than the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off, and before performing the data reading operation, the access method further includes:

[0048] A shutdown voltage is applied to at least all other write word lines except the write word line connected to the storage unit to be written with data, so as to shut down the corresponding write transistors and lock the voltage of the first gate of the corresponding read transistors.

[0049] In some optional embodiments of the present application, after controlling the write transistor to be turned on through the write word line of the storage unit to be written with data so as to apply the second voltage to the first gate of the read transistor through the write bit line and before performing the data reading operation, the access method further includes:

[0050] A shutdown voltage is applied to the write word line of the memory cell to be written with data, so as to shut down the corresponding write transistors and lock the voltage of the first gate of the corresponding read transistors.

[0051] In some optional implementations of the present application, the data writing operation includes:

[0052] Applying a turn-on voltage to a write word line shared by a plurality of storage cells to be written with data, so that the write transistors of the plurality of storage cells to be written with data are all turned on;

[0053] Applying a first write voltage or a second write voltage to a plurality of write bit lines connected to a plurality of storage cells to be written with data in a one-to-one correspondence, respectively, so as to write the first data or the second data into the ferroelectric material layer of the corresponding storage cells to be written with data;

[0054] Applying a turn-off voltage to the write word line to turn off the write transistors of the plurality of storage cells to be written with data; the read transistor and the write transistor are n-type transistors;

[0055] in:

[0056] The voltage value of the second voltage is smaller than the voltage value of the first write voltage, and smaller than the voltage value of the second write voltage;

[0057] The voltage value of the first voltage is smaller than the voltage value of the first write voltage, and smaller than the voltage value of the second write voltage.

[0058] In some optional implementations of the present application, the data writing operation includes:

[0059] Applying a conduction voltage one by one to a plurality of write word lines respectively connected to at least a portion of the storage cells to be written that do not overlap with the orthographic projection on the substrate, so as to turn on the write transistors of one or more storage cells to be written that are connected to the write word lines to which the conduction voltage is currently applied;

[0060] Applying a first write voltage or a second write voltage to one or more write bit lines connected one by one to one with one or more storage cells to be written in which the current write transistor is turned on, so as to write the first data or the second data into the first gate insulating layer of the corresponding storage cells to be written;

[0061] Applying a turn-off voltage to a write word line currently applying a turn-on voltage, so as to turn off the write transistors of one or more storage cells to be written with data connected to the write word line currently applying the turn-off voltage; the read transistor and the write transistor are n-type transistors;

[0062] in:

[0063] The voltage value of the second voltage is smaller than the voltage value of the first write voltage, and smaller than the voltage value of the second write voltage;

[0064] The voltage value of the first voltage is smaller than the voltage value of the first write voltage, and smaller than the voltage value of the second write voltage.

[0065] In a third aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned memory; or, comprising a memory accessed using the above-mentioned memory access method.

[0066] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0067] In the embodiment of the present application, the second gate is connected to the write word line, and the voltage applied to the second gate can control the write transistor to be turned on or off, the second semiconductor layer is connected to the write bit line, and the second semiconductor layer is connected to the first gate, and data can be written into the storage unit through the write bit line and stored in the ferroelectric material layer. The first semiconductor layer is connected to the read word line, and the first semiconductor layer is connected to the read bit line. By regulating the threshold voltage of the read transistor, the data stored in the storage unit determines whether the read transistor is turned on or off. After a voltage difference is formed between the read word line and the read bit line, the write data of the storage unit is determined according to the data change of the read bit line.

[0068] In the embodiment of the present application, the read transistor and the write transistor form a dual-transistor capacitor-free storage unit, the first gate of the read transistor is connected to the second semiconductor layer of the write transistor, and the ferroelectric dielectric layer can be used as a gate capacitor to store charge and change the transistor storage information. The storage unit is a 2T0C storage unit, with read and write separation, and the data is not destroyed after reading.

[0069] Between the 2T0C type semiconductor memory cells provided in the embodiment of the present application, the characteristic of storing charges of ferroelectric materials is utilized to positively shift the threshold voltage of the read transistor of the memory cells that do not need to be read, thereby locking the data stored in these memory cells that do not need to be read, so that no matter whether the data stored in the memory cells that do not need to be read is 1 or 0, it cannot be read, and only the data stored in the memory cells to be read can be read. Therefore, when reading the data stored in the memory cells to be read, the data stored in all the memory cells that do not need to be read will not affect the reading of the memory cells to be read. Based on the read transistor whose gate insulating layer is a ferroelectric material, combined with the read-write operation method proposed in the present application, the current sharing problem is effectively improved or solved.

[0070] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0072] Figure 1 It is a schematic diagram of the structure of FeRAM (Ferroelectric Random Access Memory) in the related art;

[0073] Figure 2 A circuit diagram of FeRAM in the related art;

[0074] Figure 3 for Figure 2 The timing waveform diagram of the FeRAM circuit;

[0075] Figure 4 It is a schematic diagram of the structure of FeFET (Metal Ferroelectric Semiconductor Field Effect Transistor) in the related art;

[0076] Figure 5 A schematic diagram of a polarization reversal of FeFET in the related art;

[0077] Figure 6 Another schematic diagram of polarization reversal of FeFET in related art;

[0078] Figure 7 It is a characteristic curve diagram of drain current and gate voltage of FeFET in the related art;

[0079] Figure 8 A schematic side structural diagram of an optional example of a memory provided in an embodiment of the present application;

[0080] Fig. 9 A schematic cross-sectional structure diagram of an optional example of a memory provided in an embodiment of the present application;

[0081] Fig.10 A circuit diagram of an optional example of a memory provided in an embodiment of the present application;

[0082] Fig.11 A schematic cross-sectional structural diagram of another optional example of a memory provided in an embodiment of the present application;

[0083] Fig.12 A schematic diagram of a cross-sectional structure of a memory provided in an embodiment of the present application;

[0084] Fig.13 A circuit diagram of a memory provided in an embodiment of the present application;

[0085] Fig.14 A schematic diagram of the flow of pre-reading and reading operations in a memory access method provided in an embodiment of the present application;

[0086] Fig.15 A schematic flow chart of a write operation of an optional example in a memory access method provided in an embodiment of the present application;

[0087] Fig.16 A flowchart of a write operation of another optional example in a memory access method provided in an embodiment of the present application.

[0088] Reference numerals:

[0089] 1000-memory; 100-storage cell; 10-read transistor; 11-first gate; 111-first end wall; 112-first side wall; 113-second end wall; 12-first gate insulating layer; 13-first semiconductor layer; 131-first electrode region; 132-second electrode region; 20-write transistor; 21-second gate; 211-second side wall; 22-second gate insulating layer; 23-second semiconductor layer; 231-third electrode region; 232-fourth electrode region; 30-read bit line; 40-read word line; 50-write bit line; 60-write word line. DETAILED DESCRIPTION

[0090] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0091] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or may refer to the connection relationship between the element and the other element established through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0092] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0093] The following is an explanation of the relevant technologies:

[0094] FeRAM (Ferroelectric Random Access Memory) has advantages in speed, power consumption and reliability, but there is room for improvement in size miniaturization and three-dimensional integration.

[0095] Figure 1 It is the structural diagram of FeRAM. Figure 2 This is the circuit diagram of FeRAM. Figure 3For the corresponding Figure 2 The timing waveform diagram of the FeRAM circuit in FIG. Figures 1 to 3 As shown, the FeRAM (reversed current type) memory device includes a ferroelectric capacitor 250 (Ferroelectric capacitor) and a transistor 220 arranged on a substrate 210, and the transistor 220 includes a first electrode 221, a channel 223, a second electrode 222 and a gate ( Figure 1 The gate is a part of the word line 240. One end of the ferroelectric capacitor 250 is connected to the bit line BL 230 through a MOS tube (Metal-Oxide Semiconductor Field Effect Transistor), and the other end is connected to the driving line PL 260.

[0096] FeRAM has the following disadvantages:

[0097] When reading information 1, the polarization of the ferroelectric capacitor is reversed, destroying the original storage state, which is destructive storage.

[0098] Figure 4 It is a schematic diagram of the structure of FeFET (Metal Ferroelectric Semiconductor Field Effect Transistor). Figure 5 A schematic diagram of a polarization reversal of FeFET. Figure 6 Another polarization reversal diagram of FeFET. Figure 7 is the drain current of FeFET (I d ) and gate voltage (V g )Characteristic curve( Figure 7 MW (Memory Window) represents the memory window of FeFET, V T,L Indicates the low threshold voltage, V T,H represents a high threshold voltage). Figures 4 to 7 As shown, FeFET220 is arranged on a substrate 210, and includes a first electrode 221, a channel 223, a second electrode 222, a first gate insulating layer 270 and a gate, the gate is part of the word line WL240, the bit line BL230 is connected to the first electrode 221, and the second electrode 222 is connected to an external device through a lead 280.

[0099] The ferroelectric oxide surface of the FeFET has a large trap density (10 20 cm -3), which causes the measurable switching charge to gradually decrease. Therefore, the data retention capability is low.

[0100] There are signal crosstalk or current sharing issues between 2T0C memory cells.

[0101] The memory and access method thereof, and the electronic device provided in the present application are based on a read transistor whose gate insulating layer is a ferroelectric material, and combined with the read and write operation method proposed in the present application, effectively improve or solve the current sharing problem.

[0102] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application improves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0103] The present application embodiment provides a memory, and the structural diagram of the storage unit in the memory 1000 is as follows Figure 8 , Fig. 9 , Fig.11 and Fig.12 As shown, the circuit diagram is as Fig.10 and Fig.13 As shown, the memory 1000 includes a substrate and a plurality of memory cells 100 arranged in an array on the substrate, a plurality of read bit lines 30, a plurality of read word lines 40, a plurality of write bit lines 50 and a plurality of write word lines 60; the memory cell 100 includes a read transistor 10 and a write transistor 20, wherein:

[0104] The read transistor 10 includes a first semiconductor layer 13 , a first gate insulating layer 12 connected to the first semiconductor layer 13 , and a first gate electrode 11 connected to the first gate insulating layer 12 , wherein the first gate insulating layer 12 includes a ferroelectric material layer.

[0105] like Fig.12 and Fig.13 , the write bit lines 50 of the memory cells in different rows are shared, and the write bit lines of the memory cells in different layers are not shared; the read bit lines of the memory cells in two adjacent columns are shared, and the read bit lines of the memory cells in different layers are not shared;

[0106] The write transistor 20 includes a second gate electrode 21 and a second semiconductor layer 23 , and the second semiconductor layer 23 is insulated from the second gate electrode 21 .

[0107] The read word line 40 and the read bit line 30 are connected to the first semiconductor layer 13 , respectively. The write bit line 50 and the first gate 11 are connected to the second semiconductor layer 23 , respectively. The write word line 60 is connected to the second gate 21 .

[0108] When a data writing operation is performed on a storage unit 100 to which data is to be written, the write transistor 20 is controlled to be turned on through the write word line 60 corresponding to the storage unit 100, and the data is written into the ferroelectric material layer (first gate insulating layer 12) through the write bit line 50 corresponding to the storage unit 100, wherein before the reading operation, the voltages of the read word line 40 and the read bit line 30 are the same voltage. Before the reading operation, at least all other write word lines 60 other than the write word line 60 connected to the storage unit 100 to which data is to be written are applied with a turn-on voltage, or the write word lines 60 connected to the storage unit 100 to which data is to be written are simultaneously applied with a turn-on voltage, so that the corresponding write transistors 20 are turned on, and the first voltage is applied to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, so that each read transistor 10 is turned off. When a data reading operation is performed, different voltages are applied to the read word line 40 and the read bit line 30 connected to the storage unit 100 to which data is to be written, and the write data of the storage unit 100 is determined according to whether the data of the read bit line 30 changes.

[0109] In the embodiment of the present application, the substrate supports the memory cell 100 , the read bit line 30 , the read word line 40 , the write bit line 50 , and the write word line 60 .

[0110] In the embodiment of the present application, the second gate 21 is connected to the write word line 60, and the voltage applied to the second gate 21 can control the write transistor 20 to be turned on or off, the second semiconductor layer 23 is connected to the write bit line 50, and the second semiconductor layer 23 is connected to the first gate 11, and data can be written into the storage unit 100 through the write bit line 50 and stored in the ferroelectric material layer. The first semiconductor layer 13 is connected to the read word line 40, and the first semiconductor layer 13 is connected to the read bit line 30. By regulating the threshold voltage of the read transistor 10, the data stored in the storage unit 100 determines whether the read transistor 10 is turned on or off. After a voltage difference is formed between the read bit line 30 and the read word line 40, the write data of the storage unit 100 is determined according to the data change sensed on the read bit line 30.

[0111] For example, the sense amplifier (SA) is connected to the read bit line, turned on when the read transistor stores 1, and turned off when it stores 0. When turned on, charge is shared between the read bit line and the read word line, and then the voltage or current signal on the read bit line changes compared to before charge sharing. After the signal is amplified, it is determined that the read data is 1. When the transistor stores 0 and is turned off, the signal on the read bit line does not change, and the signal is amplified to determine that the read data is 0.

[0112] In an embodiment of the present application, the read transistor 10 and the write transistor 20 form a two-transistor capacitor-free storage unit (2Transistor 0Capacitor, 2T0C), and the first gate 11 of the read transistor 10 is connected to the second semiconductor layer 23 of the write transistor 20. Ferroelectric material can be used as a gate capacitor to store charge and change the transistor storage information.

[0113] In the embodiment of the present application, the storage unit 100 of the memory is a 2T0C storage unit with read-write separation and no need to destroy data.

[0114] Based on the 2T0C type memory cell provided in the embodiment of the present application, before the reading operation, at least all other write word lines 60 other than the write word line 60 connected to the memory cell 100 to be written with data are applied with a turn-on voltage, so that the corresponding write transistors 20 are turned on, and the first voltage is applied to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, and the threshold voltage of the read transistor of the memory cell that does not need to be read is positively shifted (that is, the read transistor of the memory cell that does not need to be read has a second threshold voltage) by utilizing the characteristic that the ferroelectric material can adjust the threshold, thereby making these memory cells that do not need to be read have a second threshold voltage. The data stored in the storage cell is locked, so that all read transistors 10 are turned off, so that no matter whether the data stored in the storage cell that does not need to be read is 1 or 0, it cannot be read, and only the data stored in the storage cell to be read can be read (that is, the read transistor of the storage cell to be read has a first threshold voltage), so that when reading the data stored in the storage cell to be read, the data stored in all the storage cells that do not need to be read will not affect the reading of the storage cell to be read. Based on the read transistor whose gate insulating layer is a ferroelectric material, combined with the read-write operation method proposed in the present application, the current sharing problem is effectively improved or solved.

[0115] In some optional embodiments of the present application, a turn-on voltage is applied to all write word lines 60 other than the write word line 60 connected to at least the storage cell 100 to which data is to be written, so that the corresponding write transistors 20 are turned on, and a first voltage is applied to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, so that each read transistor 10 is turned off, and before the data reading operation is performed, the write transistor 20 is controlled to be turned on through the write word line 60 of the storage cell 100 to which data is to be written, so that a second voltage is applied to the first gate 11 of the read transistor 10 through the write bit line 50, so that when the written data is 1, the read transistor 10 is turned on, and when the written data is 0, the read transistor 10 is turned off, so as to facilitate reading of the data.

[0116] In some optional embodiments of the present application, before performing a data read operation, a turn-on voltage is applied to all write word lines 60, so that the corresponding write transistors 20 are turned on, and a first voltage is applied to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, so as to turn off the read transistors 10 of all storage cells 100. Thus, the data stored in the storage cells that do not need to be read can be locked, so that all read transistors 10 are turned off, so that no matter whether the data stored in the storage cells that do not need to be read is 1 or 0, it cannot be read, and only the data stored in the storage cells to be read can be read, so that when reading the data stored in the storage cells to be read, the data stored in all the storage cells that do not need to be read will not affect the reading of the storage cells to be read, and the current sharing problem is effectively improved or solved based on the read transistor whose gate insulating layer is a ferroelectric material, combined with the read and write operation method proposed in the present application.

[0117] In some optional implementations of the present application, each read bit line 30 of each memory cell 100 on a read word line 40 can read data simultaneously.

[0118] In some optional embodiments of the present application, such as Figure 8 and Fig. 9 As shown, the read transistor 10 and the write transistor 20 of the memory cell are arranged in sequence along a direction parallel to the substrate, which is conducive to realizing 3D stacking of multiple memory cells.

[0119] In some other optional embodiments of the present application, Fig.11 As shown, the read transistor 10 and the write transistor 20 are stacked and arranged in a direction perpendicular to the substrate, which is beneficial to improving the density of the device.

[0120] Fig.11 The first gate electrode 11 of the read transistor is connected to the second semiconductor layer 23, with a connecting electrode SN therebetween. Fig.11 The SN in the figure has two layers. In actual application, the SN can be one layer, and the SN can also be an integrated structure with the first gate.

[0121] In some optional embodiments of the present application, such as Figure 8 , Fig. 9 and Fig.11 As shown, the first semiconductor layer 13 and the second semiconductor layer 23 are both surrounding semiconductor layers, and the first gate insulating layer 12 and the first semiconductor layer 13 are sequentially disposed around the side wall of the first gate 11 . The second semiconductor layer 23 is disposed around the side wall of the second gate 21 .

[0122] In some optional embodiments of the present application, such as Figure 8 and Fig. 9As shown, the first gate 11 extends along a first direction parallel to the substrate, and the second gate 21 extends along a direction perpendicular to the substrate. The orthographic projection of the first gate 11 on the substrate does not overlap with the orthographic projection of the second gate 21 on the substrate. The first gate insulating layer 12 and the first semiconductor layer 13 sequentially wrap at least one end of the first gate 11 along the first direction.

[0123] In some optional embodiments of the present application, such as Figure 8 As shown, the first gate 11 has a first end wall 111, a first side wall 112 and a second end wall 113 connected in sequence, and the first end wall 111 and the second end wall 113 are arranged opposite to each other along a first direction; the first gate insulation layer 12 is arranged at the periphery of the first side wall 112 and the second end wall 113 of the first gate 11, and the first semiconductor layer 13 covers the outer wall surface of the first gate insulation layer 12 away from the first gate 11.

[0124] In some optional embodiments of the present application, such as Figure 8 and Fig. 9 As shown, the first end wall 111 of the first gate 11 contacts the outer wall of the second semiconductor layer 23. No interface layer is formed at the interface where the first gate 11 contacts the second semiconductor layer 23, which can increase data retention time and improve reliability.

[0125] In some optional embodiments of the present application, such as Figure 8 and Fig. 9 As shown, a side wall surface of the first gate insulating layer 12 facing the second semiconductor layer 23 contacts the outer wall surface of the second semiconductor layer 23, and a side wall surface of the first semiconductor layer 13 facing the second semiconductor layer 23 contacts the outer wall surface of the second semiconductor layer 23. No interface layer is formed at the interface where the first gate insulating layer 12 contacts the second semiconductor layer 23 and at the interface where the first semiconductor layer 13 contacts the second semiconductor layer 23, so that the data retention time can be increased and the reliability can be improved.

[0126] In some optional embodiments of the present application, such as Figure 8 As shown, a partial area of ​​the first semiconductor layer 13 corresponding to the first side wall 112 of the first gate 11 forms a first electrode region 131 of the first semiconductor layer 13, and at least a partial area of ​​the first semiconductor layer 13 corresponding to the second end wall 113 of the first gate 11 forms a second electrode region 132 of the first semiconductor layer 13, the first gate 11 extends along a first direction, and the first semiconductor layer 13 is located between the first electrode region 131 and the second electrode region 132, that is, the channel of the read transistor 10 extends along the first direction, and the extension direction of the channel of the read transistor 10 is parallel to the substrate.

[0127] Of course, in some other optional embodiments of the present application, according to actual needs, the first gate insulation layer 12 and the first semiconductor layer 13 can be sequentially arranged around the periphery of the first side wall 112 of the first gate 11, and the first semiconductor layer 13 forms a first electrode region 131 of the first semiconductor layer 13 corresponding to a portion of the first side wall 112 of the first gate 11, and the first semiconductor layer 13 forms a second electrode region 132 of the first semiconductor layer 13 corresponding to another portion of the first side wall 112 of the first gate 11.

[0128] In the embodiment of the present application, the first semiconductor layer 13 corresponds to the portion of the first side wall 112 of the first gate 11 extending in the first direction; the second gate 21 extends in a direction perpendicular to the substrate, and the second semiconductor layer 23 is arranged around the periphery of the second gate 21, and the second semiconductor layer 23 extends in a direction perpendicular to the substrate. The memory cell structure of the embodiment of the present application supports multi-layer stacking, which is conducive to 3D (3D, three-dimensional) integration.

[0129] The embodiment of the present application provides an improved 2T0C type semiconductor memory cell structure, which has the advantages of one-time vertical stacking integration, high 3D integration, low leakage, short refresh time, etc., and has obvious advantages over the existing planar 2T0C type semiconductor memory cell structure.

[0130] In some optional embodiments of the present application, such as Figure 8 As shown, the first semiconductor layer 13 has a first electrode region 131 and a second electrode region 132 arranged at intervals, the first electrode region 131 of the first semiconductor layer 13 is connected to the read word line 40, and the second electrode region 132 is connected to the read bit line 30. The second semiconductor layer 23 has a third electrode region 231 and a fourth electrode region 232 arranged at intervals, the third electrode region 231 of the second semiconductor layer 23 is connected to the write bit line 50, and the fourth electrode region 232 of the second semiconductor layer 23 is connected to the first gate 11.

[0131] In the embodiment of the present application, the first gate insulating layer 12 is located between the first gate electrode 11 and the first semiconductor layer 13 to insulate the first gate electrode 11 from the first semiconductor layer 13 .

[0132] It should be noted that, in the embodiment of the present application, the first electrode region 131 of the first semiconductor layer 13 forms one of the source and the drain of the read transistor 10, the second electrode region 132 of the first semiconductor layer 13 forms the other of the source and the drain of the read transistor 10, and the portion located between the first electrode region 131 and the second electrode region 132 of the first semiconductor layer 13 forms the channel of the read transistor 10; the third electrode region 231 of the second semiconductor layer 23 forms one of the source and the drain of the write transistor 20, the fourth electrode region 232 of the second semiconductor layer 23 forms the other of the source and the drain of the write transistor 20, and the portion located between the third electrode region 231 and the fourth electrode region 232 of the second semiconductor layer 23 forms the channel of the write transistor 20; the first gate 11 of the read transistor 10 is connected to the source or drain of the write transistor 20 (i.e., the fourth electrode region 232 of the second semiconductor layer 23).

[0133] Of course, in some optional embodiments of the present application, according to actual needs, the first electrode region 131 of the first semiconductor layer 13 forms one of the first source contact region and the first drain contact region, the second electrode region 132 of the first semiconductor layer 13 forms the other of the first source contact region and the first drain contact region, and the portion of the first semiconductor layer 13 located between the first source contact region and the first drain contact region forms the channel of the read transistor 10; in this case, the read transistor 10 further includes a first electrode and a second electrode, the first electrode is connected or in contact with the first electrode region 131 of the first semiconductor layer 13, the second electrode is connected or in contact with the second electrode region 132 of the first semiconductor layer 13, the first electrode forms one of the source and the drain of the read transistor 10, and the second electrode forms the other of the source and the drain of the read transistor 10. The first electrode is connected to the read word line 40, and optionally, the first electrode is integrally formed with the read word line 40, or the first electrode is a part of the read word line 40. The second electrode is connected to the read bit line 30, and optionally, the second electrode is integrally formed with the read bit line 30, or the second electrode is a part of the read bit line 30.

[0134] Of course, in some optional embodiments of the present application, according to actual needs, the third electrode region 231 of the second semiconductor layer 23 forms one of the second source contact region and the second drain contact region, the fourth electrode region 232 of the second semiconductor layer 23 forms the other of the second source contact region and the second drain contact region, and the portion of the second semiconductor layer 23 located between the second source contact region and the second drain contact region forms the channel of the write transistor 20; in this case, the write transistor 20 further includes a third electrode and a fourth electrode, the third electrode is connected or in contact with the third electrode region 231 of the second semiconductor layer 23, the fourth electrode is connected or in contact with the fourth electrode region 232 of the second semiconductor layer 23, the third electrode forms one of the source and the drain of the write transistor 20, and the fourth electrode forms the other of the source and the drain of the write transistor 20. The third electrode is connected to the write bit line 50, and optionally, the third electrode is integrally formed with the write bit line 50, or the third electrode is used as part of the write bit line 50. The fourth electrode is connected to the first gate 11, and optionally, the fourth electrode is integrally formed with the first gate 11, or the fourth electrode is used as part or all of the first gate 11.

[0135] In some optional embodiments of the present application, the material of the first semiconductor layer 13 includes a metal oxide semiconductor material. The material of the second semiconductor layer 23 includes a metal oxide semiconductor material.

[0136] In the embodiment of the present application, the first gate insulating layer 12 includes a ferroelectric material layer, and the material of the first semiconductor layer 13 includes a metal oxide semiconductor material. Since the metal oxide semiconductor (such as IGZO) material has a wide band gap, leakage current can be reduced and the ferroelectric leakage current problem can be improved.

[0137] In some optional embodiments of the present application, the first gate insulating layer 12 is in contact with the first gate 11 and the first semiconductor layer 13 respectively; the ferroelectric material includes doped hafnium oxide, and the doping elements in the doped hafnium oxide include at least one of zirconium, silicon, yttrium, aluminum, and lanthanum.

[0138] In some optional embodiments of the present application, the metal element in the metal oxide semiconductor material includes at least one of indium, gallium, zinc, and tin.

[0139] In some optional embodiments of the present application, the metal oxide semiconductor material may be indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15A), thereby ensuring a low refresh rate of dynamic memory. In addition, the off-state current of transistors based on IGZO materials is extremely small, which can effectively store charges and does not require the manufacture of capacitors separately. At the same time, it is flexible in application and can be applied to transistors of different structures, thus effectively saving process area and reducing power consumption. It should be noted that metal oxide semiconductor materials can also be ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), InGaO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a, InGaSiO, IAZO and other materials, as long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation. The first semiconductor layer 13 can be formed by atomic layer deposition, and each component is adjusted by the process.

[0140] Ferroelectric materials are prone to forming alloys with silicon or silicon dioxide, resulting in the formation of an interface layer between the ferroelectric material and silicon or silicon dioxide, which affects the device characteristics. In the embodiment of the present application, a ferroelectric material is used as a dielectric material, a metal oxide semiconductor material is used as a channel material, the ferroelectric material is in contact with the metal oxide semiconductor material, the ferroelectric material is easy to grow, and no interface layer is formed between the metal oxide semiconductor material and the ferroelectric material, which can increase the retention time (data retention time) and improve reliability.

[0141] In some optional embodiments of the present application, the material of the first gate 11 includes a metal material. Optionally, the metal material can be any metal material such as W, Al, Mo, Ru, TiN, Ta, Ti, or a compound thereof.

[0142] In some optional embodiments of the present application, the material of the second gate 21 includes a metal material. Optionally, the metal material can be any metal material such as W, Al, Mo, Ru, TiN, Ta, Ti, or a compound thereof.

[0143] In some optional embodiments of the present application, such as Figure 8 , Fig. 9 and Fig.11 As shown, the writing transistor 20 further includes a second gate insulating layer 22 , which is disposed between the second gate electrode 21 and the second semiconductor layer 23 to insulate the second gate electrode 21 from the second semiconductor layer 23 .

[0144] In some optional embodiments of the present application, the material of the second gate insulating layer 22 includes a high dielectric constant material (HK dielectric material).

[0145] Optionally, the high dielectric constant material includes but is not limited to any dielectric material with a dielectric constant value greater than 3.9. Optionally, the high dielectric constant material can be aluminum oxide, hafnium oxide, and other materials.

[0146] In some optional embodiments of the present application, such as Figure 8As shown, the second gate 21 has a second side wall 211, and the second gate insulating layer 22 and the second semiconductor layer 23 are sequentially arranged around the periphery of the second side wall 211 of the second gate 21. A portion of the second semiconductor layer 23 corresponding to the second side wall 211 of the second gate 21 forms a third electrode region 231 of the second semiconductor layer 23, and another portion of the second semiconductor layer 23 corresponding to the second side wall 211 of the second gate 21 forms a fourth electrode region 232 of the second semiconductor layer 23. The second gate 21 extends in a direction perpendicular to the substrate, and the portion of the second semiconductor layer 23 located between the third electrode region 231 and the fourth electrode region 232, i.e., the channel of the write transistor 20, extends in a direction perpendicular to the substrate.

[0147] In the embodiment of the present application, the gate dielectric layer of the read transistor 10 and the write transistor 20 of the memory cell 100 are made of different materials. The gate dielectric layer of the read transistor 10 is a first gate insulating layer 12 made of a ferroelectric material, and the gate dielectric layer of the write transistor 20 is a second gate insulating layer 22 made of a dielectric material. Optionally, the material of the second gate insulating layer 22 includes a high dielectric constant material, which helps to achieve a miniaturized device. In the embodiment of the present application, the thickness of the gate dielectric layer can be used to control the channel length of the corresponding transistor.

[0148] The memory cell of the embodiment of the present application relates to the field of memory devices, and in particular to a novel, capacitor-free ferroelectric memory cell structure. The memory cell of the embodiment of the present application can be applied to 3D ferroelectric memory and the like.

[0149] In some optional embodiments of the present application, the first semiconductor layer 13 and the second semiconductor layer 23 in a storage unit 100 are not connected, so as to avoid signal crosstalk between multiple storage units on a write word line. For example, when the semiconductor layers of multiple write transistors on a write word line are connected, the semiconductor layer between the write transistor and the read transistor in a storage unit is not connected, so as to avoid the read data from reaching the read transistors of other storage units through the write transistor.

[0150] In some optional embodiments of the present application, the second semiconductor layers 23 of adjacent write transistors 20 on a write word line 60 are not connected, so as to avoid the presence of parasitic transistors between adjacent write transistors 20 on a write word line 60. In addition, it can also avoid signal crosstalk to other storage cells when the semiconductor layers of the read transistor and the write transistor in a storage cell are connected.

[0151] In other words, when the semiconductor layer between the write transistor and the read transistor is connected, the semiconductor layers between the write transistors stacked in the direction perpendicular to the substrate need to be disconnected, which can avoid information crosstalk and parasitic MOS. At the same time, there is no need to remove or disconnect the two semiconductor layers separately, simplifying the manufacturing process.

[0152] In some optional embodiments of the present application, such as Figure 8 , Fig. 9 and Fig.12 As shown, the read word line 40 and the read bit line 30 are both located on a side of the first semiconductor layer 13 away from the first gate 11, the read bit line 30 is connected to the end of the first semiconductor layer 13 and extends along a second direction parallel to the substrate, so that multiple storage cells 100 share one read bit line 30; the read word line 40 is arranged around the outer wall of the first semiconductor layer 13 and extends in a direction perpendicular to the substrate; the write bit line 50 and the first gate 11 are arranged at intervals along the first direction and are respectively connected to different areas of the side wall of the second semiconductor layer 23, the write bit line 50 extends along the second direction, so that multiple storage cells 100 share one write bit line 50, and the write word line 60 extends in a direction perpendicular to the substrate; the second direction intersects with the first direction.

[0153] In some optional embodiments of the present application, the memory 1000 includes multiple layers of first memory cell arrays, and each layer of the first memory cell array includes a plurality of memory cells 100 arranged in an array along a first direction and a second direction.

[0154] Through this setting method, an array structure and a 3D stacking structure can be formed, which can improve the storage capacity of the memory, reduce storage costs, increase integration and storage density, and help achieve miniaturization.

[0155] In some optional embodiments of the present application, a read bit line 30 connects a plurality of read transistors 10 spaced apart along the second direction in a first memory cell array. A write bit line 50 connects a plurality of write transistors 20 spaced apart along the second direction in a first memory cell array. Specifically, Fig.12 and Fig.13 As shown, in any first memory cell array, the second electrode region 132 of the first semiconductor layer 13 of two adjacent memory cells 100 share a read bit line 30, and the third electrode region 231 of the second semiconductor layer 23 of two adjacent memory cells 100 share a write bit line 50. This arrangement can reduce the number of bit lines, which is beneficial to layout design, and improves structural density and practicality.

[0156] In some optional embodiments of the present application, a read word line 40 connects a plurality of read transistors 10 stacked in a direction perpendicular to the substrate. A write word line 60 connects a plurality of write transistors 20 stacked in a direction perpendicular to the substrate. Specifically, in the multi-layer first memory cell array, the first electrode region 131 of the first semiconductor layer 13 of a plurality of memory cells 100 whose orthographic projections overlap on the substrate shares a read word line 40, the read word line 40 extends in a direction perpendicular to the substrate, and the second gates 21 of a plurality of memory cells 100 whose orthographic projections overlap on the substrate share a write word line 60. This arrangement can reduce the number of word lines, which is beneficial to layout design, and improves structural density and practicality.

[0157] The memory can be used in either volatile or non-volatile memory scenarios.

[0158] Based on the same inventive concept, an embodiment of the present application provides a method for accessing a memory.

[0159] In some optional embodiments of the present application, the memory includes a plurality of read bit lines 30, a plurality of read word lines 40, a plurality of write bit lines 50, a plurality of write word lines 60, and a plurality of storage cells 100 arranged in an array, such as Fig.12 and Fig.13 As shown, the memory cell 100 includes a read transistor 10 and a write transistor 20, wherein the first semiconductor layer 13 of the read transistor 10 is connected to the read word line 40, the first semiconductor layer 13 is connected to the read bit line 30, the second semiconductor layer 23 of the write transistor 20 is connected to the write bit line 50, the second semiconductor layer 23 is connected to the first gate 11 of the read transistor 10, the second gate 21 of the write transistor 20 is connected to the write word line 60, and a first gate insulating layer 12 is provided between the first gate 11 and the first semiconductor layer 13, and the first gate insulating layer 12 includes a ferroelectric material layer.

[0160] The flowchart of the memory access method provided in the embodiment of the present application is as follows: Figures 14 to 16 As shown, the access method of the memory includes a data writing operation and a data reading operation; after the data writing operation and before the data reading operation, the access method further includes:

[0161] S101, such as Fig.14 As shown, a turn-on voltage is applied to all write word lines 60 other than the write word line 60 connected to the storage unit 100 to which data is to be written, so that the corresponding write transistors 20 are turned on, and a first voltage is applied to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, so that each read transistor 10 is turned off.

[0162] In some optional embodiments of the present application, at least a turn-on voltage is applied to all other write word lines 60 except the write word line 60 connected to the storage unit 100 to be written with data, so that the corresponding write transistors 20 are turned on, and a first voltage is applied to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, so that each read transistor 10 is turned off, including:

[0163] An on voltage is applied to all write word lines 60 to turn on the corresponding write transistors 20 , and a first voltage is applied to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20 to turn off the read transistors 10 of all memory cells 100 .

[0164] Optionally, a conduction voltage is applied to all write word lines 60 in the second memory cell array, so that all write transistors 20 in the second memory cell array are turned on. Figure 8 and Fig. 9 As shown, the write word line 60 is connected to the second gate 21, and the voltage applied to the second gate 21 can control the on or off of the write transistor 20. The on voltage is applied to the write word line 60, and the on voltage acts on the second gate 21 to turn on the write transistor 20, so as to facilitate the subsequent application of the first voltage to the first gate 11 through the write bit line 50. Optionally, the second memory cell array is perpendicular to the extension direction of the first gate, that is, the second memory cell array is perpendicular to the first direction.

[0165] Next, a first voltage is applied to all write bit lines 50 in the second memory cell array, and the first voltage is applied to the corresponding first gate 11, so that all read transistors 10 in the second memory cell array have a second threshold voltage, and all read transistors in the second memory cell array are turned off. The second threshold voltage satisfies the following relationship: the data stored in the memory cells that do not need to be read is 0 or 1, and the read transistors 10 of the memory cells that do not need to be read are all in a turned-off state. Since all write transistors 20 in the second memory cell array are turned on, a first voltage can be applied to all write bit lines 50 in the second memory cell array, and the first voltage is applied to the corresponding first gate 11, so that all read transistors 10 in the second memory cell array have a second threshold voltage, and the data stored in all memory cells in the second memory cell array are locked, so that no matter whether the data stored in these memory cells is 1 or 0, the read transistors 10 are all in a turned-off state, and the data stored in the memory cells cannot be read.

[0166] After applying a turn-on voltage to all other write word lines 60 except the write word line 60 connected to the storage unit 100 to be written with data, so that the corresponding write transistors 20 are turned on, and applying a first voltage to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, so that each read transistor 10 is turned off, before performing a data reading operation, the access method further includes:

[0167] A shutdown voltage is applied to at least all other write word lines 60 except the write word line 60 connected to the memory cell 100 to be written with data, so as to shut down the corresponding write transistors 20 and lock the voltage of the first gate 11 of the corresponding read transistor 10 .

[0168] Optionally, a shutdown voltage is applied to all write word lines 60 in the second memory cell array and connected to memory cells that do not need to be read, so as to shut down the write transistors 20 of all memory cells in the second memory cell array that do not need to be read, so that the voltage of the first gate 11 of all memory cells in the second memory cell array that do not need to be read is locked at the first voltage. The data stored in all memory cells in the second memory cell array that do not need to be read are locked, so that no matter whether the data stored in these memory cells is 1 or 0, the read transistor 10 is in a closed state, and the data stored in the memory cells cannot be read, which can avoid the problem that the data stored in the memory cells that do not need to be read interferes with the read data when the memory cells to be read are subsequently read, and can improve the current sharing problem.

[0169] In some optional embodiments of the present application, after applying a turn-on voltage to all other write word lines 60 except the write word line 60 connected to the storage unit 100 to be written with data, so that the corresponding write transistors 20 are turned on, and applying a first voltage to the first gate 11 of each read transistor 10 through the write bit line 50 corresponding to each write transistor 20, so that each read transistor 10 is turned off, before performing the data reading operation, the access method further includes:

[0170] The write transistor 20 is controlled to be turned on through the write word line 60 of the storage cell 100 to which data is to be written, so as to apply a second voltage to the first gate 11 of the read transistor 10 through the write bit line 50, so that when the written data is 1, the read transistor 10 is turned on, and when the written data is 0, the read transistor 10 is turned off.

[0171] Optionally, a second voltage is applied to all write bit lines 50 connected to the memory cells to be read in the second memory cell array, and the second voltage is applied to the first gate 11 of the memory cells to be read, so that the read transistors 10 of all the memory cells to be read in the second memory cell array have a first threshold voltage, and the difference between the current value detected when the data stored in the memory cell to be read is 0 and the current value detected when the stored data is 1 is maximized. The first threshold voltage satisfies the following relationship: if the data stored in the memory cell to be read is 0, the read transistor 10 of the memory cell to be read is in a closed state; if the data stored in the memory cell to be read is 1, the read transistor 10 of the memory cell to be read is in a conducting state.

[0172] After the write transistor 20 is turned on by the write word line 60 of the memory cell 100 to be written with data, so as to apply the second voltage to the first gate 11 of the read transistor 10 through the write bit line 50, and before performing the data reading operation, the access method further includes:

[0173] A turn-off voltage is applied to the write word line 60 of the memory cell 100 to which data is to be written, so as to turn off the corresponding write transistors 20 and lock the voltage of the first gate 11 of the corresponding read transistors 10 .

[0174] Optionally, a shutdown voltage is applied to all write word lines 60 located in the second memory cell array and connected to the memory cells to be read, so as to turn off the write transistors 20 of all the memory cells to be read located in the second memory cell array, so that the voltage of the first gate 11 of all the memory cells to be read located in the second memory cell array is locked at the first threshold voltage to ensure the accuracy of the reading.

[0175] In the embodiment of the present application, the write transistors 20 of all the memory cells to be read in the second memory cell array are turned on, and a second voltage is applied through the corresponding write bit lines 50, and the second voltage is applied to the first gate 11 of the memory cell to be read, so that the threshold voltage of the read transistor 10 of the memory cell to be read is shifted, so that the read transistors 10 of all the memory cells to be read in the second memory cell array have the first threshold voltage, when the data stored in the memory cell to be read is 0, the read transistor 10 is turned off, when the data stored in the memory cell to be read is 1, the read transistor 10 is turned on, and the difference between the current value detected when the data stored in the memory cell to be read is 0 and the current value detected when the stored data is 1 is maximized, so that it is convenient to judge whether the data stored in the memory cell to be read is 0 or 1 according to the magnitude of the detected current value, so as to distinguish the data and improve the accuracy of reading. Optionally, the second voltage can shift the threshold voltage of the read transistor 10 of the memory cell to be read positively.

[0176] Optionally, in the embodiment of the present application, the first data is one of "0" and "1", and the second data is the other of "0" and "1".

[0177] It can be understood that different data correspond to different read current values. By applying different second voltages to the first gate 11, the difference between the read current value corresponding to the first data and the read current value corresponding to the second data is different. Therefore, the second voltage that maximizes the difference between the read current value corresponding to the first data and the read current value corresponding to the second data can be obtained through experiments.

[0178] A write word line connects the write transistors of multiple storage cells; a read word line connects the read transistors of the multiple storage cells; the write transistors are connected to different write bit lines; the read transistors are connected to different read bit lines; the read bit lines of the storage cells on a read word line can read the data of the corresponding storage cells at the same time.

[0179] In some optional embodiments of the present application, such as Fig.14 As shown, the data reading operation includes:

[0180] S102 , applying different voltages to the read word line 40 and the read bit line 30 connected to the storage cell 100 to be written with data, and determining the write data of the storage cell 100 according to the data change amount of the read bit line 30 .

[0181] Optionally, a first read voltage is applied to a read word line 40 connected to a memory cell to be read, and a second read voltage different from the first read voltage is applied to a read bit line 30 connected to the memory cell to be read, so as to form a voltage difference between the read word line 40 and the read bit line 30;

[0182] Next, the change of the electrical signal on the read bit line 30 is measured to read the data stored in the storage unit. Specifically, when the voltage change or current change of the read bit line 30 is detected, and the change value is greater than or equal to the preset first voltage change threshold or first current change threshold, it is determined that the data stored in the storage unit to be read is 1; when it is detected that the voltage or current of the read bit line 30 is unchanged, or the change value is less than or equal to the preset second voltage change threshold or second current change threshold, it is determined that the data stored in the storage unit to be read is 0. Optionally, the first voltage change threshold is greater than the second voltage change threshold, and the first current change threshold is greater than the second current change threshold.

[0183] The memory access method of the embodiment of the present application can be used to access the memory of the embodiment of the present application.

[0184] In the embodiment of the present application, the storage unit 100 is a two-transistor capacitor-free storage unit (2T0C) structure with read-write separation, and the stored data is not destroyed when reading.

[0185] like Figure 8 As shown, the first gate 11 of the read transistor 10 is connected to the second semiconductor layer 23 of the write transistor 20 , and the first gate insulating layer 12 of the read transistor 10 is arranged around the periphery of the first gate 11 , and data can be stored in the first gate insulating layer 12 through the write transistor 20 .

[0186] like Figure 8 As shown, the first electrode region 131 of the first semiconductor layer 13 is connected to the read word line 40, the second electrode region 132 of the first semiconductor layer 13 is connected to the read bit line 30, and the portion between the first electrode region 131 and the second electrode region 132 of the first semiconductor layer 13 forms a channel of the read transistor 10.

[0187] In the embodiment of the present application, the read transistors 10 of the memory cells that do not need to be read in all the memory cells 100 located in the second memory cell array have a second threshold voltage, and the data stored in the memory cells that do not need to be read are locked, so that no matter whether the data stored in these memory cells that do not need to be read is 1 or 0, the read transistors 10 of the memory cells that do not need to be read are all in a closed state, and the data stored in the memory cells that do not need to be read cannot be read. Therefore, when reading the data stored in the memory cells to be read, the data stored in all the memory cells that do not need to be read will not affect the reading of the memory cells to be read, which can improve the current sharing problem between the existing 2T0C type semiconductor memory cells.

[0188] In the embodiment of the present application, the read transistor 10 of the memory cell to be read in all the memory cells 100 located in the second memory cell array has a first threshold voltage, so that the data stored in the memory cell to be read determines whether the read transistor 10 of the memory cell to be read is turned on or off. When the data stored in the memory cell to be read is 0, the read transistor 10 of the memory cell to be read is in an off state, and when the data stored in the memory cell to be read is 1, the read transistor 10 of the memory cell to be read is in an on state; thereafter, a first read voltage is applied to the read word line 40 connected to the memory cell to be read, and a second read voltage is applied to the read bit line 30 connected to the memory cell to be read. Since the second read voltage is different from the first read voltage, a voltage difference is formed between the first electrode region 131 and the second electrode region 132 of the first semiconductor layer 13 of the memory cell to be read. By detecting the current between the first electrode region 131 and the second electrode region 132 of the read transistor 10 in an on state or a off state, the data stored in the first gate insulating layer 12 of the memory cell to be read can be read.

[0189] In some optional embodiments of the present application, when applying a first read voltage to a read word line 40 connected to a memory cell to be read and applying a second read voltage to a read bit line 30 connected to the memory cell to be read to form a voltage difference between a first electrode region 131 and a second electrode region 132 of a first semiconductor layer 13 of the memory cell to be read, thereby turning on the read transistor 10, the memory access method further includes:

[0190] A first read voltage is applied to a read word line 40 located in the second memory cell array and connected to a memory cell that does not need to be read, and a first read voltage is applied to a read bit line 30 connected to the memory cell that does not need to be read, so that a voltage difference is not formed between the first electrode region 131 and the second electrode region 132 of the first semiconductor layer 13 of the memory cell that does not need to be read, thereby avoiding the problem that the data stored in the memory cell that does not need to be read interferes with the read data when the memory cell to be read is subsequently read, and improving the Current Sharing problem.

[0191] In some optional embodiments of the present application, such as Fig.15 As shown, the orthographic projections of multiple storage cells to be written with data overlap on the substrate, and the multiple storage cells to be written with data are located in different first storage cell arrays and share a write word line 60, and the shared write word line 60 extends in a direction perpendicular to the substrate. The data writing operation includes:

[0192] S103, applying a conduction voltage to a write word line 60 shared by a plurality of storage cells to be written with data, so that the write transistors 20 of the plurality of storage cells to be written with data are all turned on. The write word line 60 is connected to the second gates 21 of the plurality of storage cells to be written with data, and the voltage applied to the second gate 21 can control the write transistors 20 to be turned on or off, and by applying the conduction voltage, the write transistors 20 of the plurality of storage cells to be written with data can all be turned on.

[0193] S104, applying the first write voltage or the second write voltage to the plurality of write bit lines 50 connected one-to-one to the plurality of storage cells to be written with data, so as to write the first data or the second data into the ferroelectric material layer of the corresponding storage cells to be written with data. Figure 8As shown, the write bit line 50 is connected to the third electrode region 231 of the second semiconductor layer 23 of the write transistor 20, the fourth electrode region 232 of the second semiconductor layer 23 is connected to the first gate 11, and the first gate insulating layer 12 is arranged around the periphery of the first gate 11. By applying a write voltage, the first gate insulating layer 12 can be polarized, so that data can be written into the first gate insulating layer 12. The polarization direction of the first gate insulating layer 12 when the first write voltage is applied is different from the polarization direction of the first gate insulating layer 12 when the second write voltage is applied. Therefore, by applying the first write voltage, the first data can be written into the first gate insulating layer 12 of the corresponding storage unit to be written, or, by applying the second write voltage, the second data can be written into the first gate insulating layer 12 of the corresponding storage unit to be written.

[0194] S105, applying a shutdown voltage to the write word line 60 to turn off the write transistors 20 of the plurality of storage cells to be written with data. The write transistors 20 are turned off, and the polarization direction of the first gate insulating layer 12 is maintained, thereby saving the corresponding data. The read transistor and the write transistor are n-type transistors;

[0195] Among them: the voltage value of the second voltage is smaller than the voltage value of the first write voltage, and smaller than the voltage value of the second write voltage; the voltage value of the first voltage is smaller than the voltage value of the first write voltage, and smaller than the voltage value of the second write voltage.

[0196] In the embodiment of the present application, the read transistor and the write transistor are n-type transistors;

[0197] The voltage value of the first write voltage and the voltage value of the second write voltage are both greater than the voltage value of the second voltage. The first write voltage or the second write voltage acts on the first gate 11, so that the first gate insulating layer 12 is polarized, thereby writing data into the first gate insulating layer 12. The different polarization directions of the first gate insulating layer 12 indicate that the data stored in the first gate insulating layer 12 are different. The voltage value of the second voltage is less than the voltage value of the first write voltage and the voltage value of the second write voltage. In this way, when the second voltage acts on the first gate 11, it is not enough to polarize the first gate insulating layer 12, so that it will not affect the data stored in the first gate insulating layer 12. In this way, the second voltage can be applied to the first gate 11 without affecting the data stored in the first gate insulating layer 12, so that the read transistor 10 has a first threshold voltage, and the difference between the current value detected when the data stored in the storage unit is 0 and the current value detected when the data stored is 1 is maximized. Similarly, the voltage value of the first voltage is less than the voltage value of the first write voltage, and less than the voltage value of the second write voltage, which also has similar beneficial effects, which will not be repeated here.

[0198] In some other optional embodiments of the present application, Fig.16As shown, among the plurality of storage cells to be written with data, at least some of the storage cells to be written with data have no overlap in their orthographic projections on the substrate, and at least some of the storage cells to be written with data have no overlap in their orthographic projections on the substrate, respectively correspondingly connected to different write word lines 60, and each write word line 60 extends in a direction perpendicular to the substrate. The data writing operation includes:

[0199] S106, applying a turn-on voltage one by one to a plurality of write word lines 60 respectively connected to at least a portion of the storage cells to be written that do not overlap with the orthographic projection on the substrate, so as to turn on the write transistors 20 of one or more storage cells to be written that are connected to the write word line 60 to which the turn-on voltage is currently applied. A write word line 60 is connected to the second gate 21 of one or more storage cells to be written, and the write transistor 20 can be controlled to be turned on or off by applying a voltage to the second gate 21, and the write transistor 20 of one or more storage cells to be written can be turned on by applying a turn-on voltage.

[0200] S107, applying the first write voltage or the second write voltage to one or more write bit lines 50 connected one by one to one of the one or more storage cells to be written with data being turned on by the current write transistor 20, so as to write the first data or the second data into the first gate insulating layer 12 of the corresponding storage cells to be written with data. Figure 8 As shown, the write bit line 50 is connected to the third electrode region 231 of the second semiconductor layer 23 of the write transistor 20, the fourth electrode region 232 of the second semiconductor layer 23 is connected to the first gate 11, and the first gate insulating layer 12 is arranged around the periphery of the first gate 11. By applying a write voltage, the first gate insulating layer 12 can be polarized. The polarization direction of the first gate insulating layer 12 when the first write voltage is applied is different from the polarization direction of the first gate insulating layer 12 when the second write voltage is applied. Therefore, by applying the first write voltage, the first data can be written into the first gate insulating layer 12 of the corresponding storage unit to be written, or, by applying the second write voltage, the second data can be written into the first gate insulating layer 12 of the corresponding storage unit to be written.

[0201] S108, applying a turn-off voltage to the write word line 60 currently applying the turn-on voltage, so as to turn off the write transistor 20 of one or more storage units to be written with data connected to the write word line 60 currently applying the turn-off voltage. The write transistor 20 is turned off, and the polarization direction of the first gate insulating layer 12 is maintained, so as to save the corresponding data. Wherein: the voltage value of the second voltage is less than the voltage value of the first write voltage, and less than the voltage value of the second write voltage; the voltage value of the first voltage is less than the voltage value of the first write voltage, and less than the voltage value of the second write voltage.

[0202] In the embodiment of the present application, the voltage value of the first write voltage and the voltage value of the second write voltage are both greater than the voltage value of the second voltage. The first write voltage or the second write voltage acts on the first gate 11, so that the first gate insulating layer 12 is polarized, thereby writing data into the first gate insulating layer 12. The different polarization directions of the first gate insulating layer 12 indicate that the data stored in the first gate insulating layer 12 are different. The voltage value of the second voltage is less than the voltage value of the first write voltage and the voltage value of the second write voltage. In this way, when the second voltage acts on the first gate 11, it is not enough to polarize the first gate insulating layer 12, so that it will not affect the data stored in the first gate insulating layer 12. In this way, the second voltage can be applied to the first gate 11 without affecting the data stored in the first gate insulating layer 12, so that the read transistor 10 has a first threshold voltage, and the difference between the current value detected when the data stored in the storage unit is 0 and the current value detected when the stored data is 1 is maximized. Similarly, the voltage value of the first voltage is less than the voltage value of the first write voltage, and less than the voltage value of the second write voltage, which also has similar beneficial effects, which will not be repeated here.

[0203] The read and write transistors of the storage unit provided in the present application may both be p-type transistors, or one of them may be an n-type transistor and the other a p-type transistor. The corresponding voltage relationship changes adaptively with the type of transistor, which will not be elaborated here.

[0204] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: a memory 1000 as described above; or a memory accessed by using the memory access method as described above.

[0205] It should be noted that since the electronic device of the embodiment of the present application includes the memory of the embodiment of the present application or the memory accessed by the memory access method of the embodiment of the present application, the electronic device of the embodiment of the present application also has the above-mentioned beneficial effects of the memory of the embodiment of the present application or the memory accessed by the memory access method of the embodiment of the present application, which will not be repeated here.

[0206] In some optional embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply, etc. Among them, the storage device may include a memory in a computer, etc., which is not limited here.

[0207] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0208] In the embodiment of the present application, the first electrode region of the first semiconductor layer forms one of the source and the drain of the read transistor, the second electrode region of the first semiconductor layer forms the other of the source and the drain of the read transistor, and the portion located between the first electrode region and the second electrode region of the first semiconductor layer forms the channel of the read transistor; the third electrode region of the second semiconductor layer forms one of the source and the drain of the write transistor, the fourth electrode region of the second semiconductor layer forms the other of the source and the drain of the write transistor, and the portion located between the third electrode region and the fourth electrode region of the second semiconductor layer forms the channel of the write transistor; the first gate of the read transistor is connected to the source or drain of the write transistor (i.e., the fourth electrode region of the second semiconductor layer).

[0209] In the embodiment of the present application, the second gate is connected to the write word line, and the voltage applied to the second gate can control the write transistor to be turned on or off, the third electrode region of the second semiconductor layer is connected to the write bit line, and the fourth electrode region of the second semiconductor layer is connected to the first gate, and data can be written into the storage unit through the write bit line and stored in the ferroelectric material layer. The first electrode region of the first semiconductor layer is connected to the read word line, and the second electrode region of the first semiconductor layer is connected to the read bit line. By regulating the threshold voltage of the read transistor, the data stored in the storage unit determines whether the read transistor is turned on or off. After a voltage difference is formed between the read word line and the read bit line, the write data of the storage unit is determined according to the data change of the read bit line.

[0210] In the embodiment of the present application, the read transistor and the write transistor form a dual-transistor capacitor-free storage unit, and the first gate of the read transistor is connected to the fourth electrode region of the second semiconductor layer of the write transistor. The gate capacitance can be used to store charge and change the transistor storage information.

[0211] In the embodiment of the present application, ferroelectric material is used as the dielectric material and metal oxide semiconductor material is used as the channel material. The ferroelectric material is in contact with the metal oxide semiconductor material. The ferroelectric material is easy to grow and no interface layer is formed between the metal oxide semiconductor material and the ferroelectric material. This can increase the data retention time and improve reliability.

[0212] In the embodiment of the present application, the material of the first gate insulating layer of the read transistor includes a ferroelectric material, and the material of the first semiconductor layer includes a metal oxide semiconductor material. Since the metal oxide semiconductor material has a wide band gap, leakage current can be reduced and the ferroelectric leakage current problem can be improved.

[0213] The 2T0C type semiconductor memory cell structure provided in the embodiment of the present application utilizes the characteristic of adjustable threshold of ferroelectric material to positively shift the threshold voltage of the read transistor of the memory cell that does not need to be read, thereby locking the data stored in these memory cells that do not need to be read, so that no matter whether the data stored in the memory cell that does not need to be read is 1 or 0, it cannot be read, and only the data stored in the memory cell to be read can be read. Therefore, when reading the data stored in the memory cell to be read, the data stored in all the memory cells that do not need to be read will not affect the reading of the memory cell to be read. Therefore, based on the read transistor whose gate insulating layer is ferroelectric material, combined with the read-write operation method proposed in the present application, the current sharing problem is effectively improved or solved.

[0214] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0215] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0216] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0217] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0218] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0219] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0220] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A memory, characterized in that: The invention comprises a substrate and a plurality of memory cells arranged in an array on the substrate, a plurality of read word lines, a plurality of read bit lines, a plurality of write word lines and a plurality of write bit lines, wherein the memory cells comprise read transistors and write transistors; The read transistor comprises a first semiconductor layer, a first gate insulating layer connected to the first semiconductor layer, and a first gate connected to the first gate insulating layer, wherein the first gate insulating layer comprises a ferroelectric material layer; the write transistor comprises a second gate and a second semiconductor layer, wherein the second semiconductor layer is insulated from the second gate; The read word line and the read bit line are connected to the first semiconductor layer respectively; the write bit line and the first gate are connected to the second semiconductor layer respectively, and the write word line is connected to the second gate; When a data writing operation is performed on a storage unit to be written with data, the write transistor is controlled to be turned on through the write word line corresponding to the storage unit, and the data is written into the ferroelectric material layer through the write bit line corresponding to the storage unit, wherein the voltage of the read word line and the read bit line are the same voltage; Before the reading operation, at least applying a turn-on voltage to all other write word lines except the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off; When performing a data reading operation, different voltages are applied to a read word line and a read bit line connected to the storage cell to be written with data, and the write data of the storage cell is determined according to the data sensed on the read bit line.

2. The memory according to claim 1, characterized in that: Before performing a data reading operation, an on voltage is applied to all write word lines to turn on the corresponding write transistors, and a first voltage is applied to the first gate of each read transistor through the write bit line corresponding to each write transistor to turn off the read transistors of all storage cells.

3. The memory according to claim 2, characterized in that: After applying a turn-on voltage to all write word lines other than the write word line connected to at least the storage unit to which data is to be written, so that the corresponding write transistors are turned on, applying a first voltage to the first gate of each read transistor through the write bit line corresponding to the write transistor to turn off each read transistor, and before performing a data reading operation, the write transistor is controlled to be turned on through the write word line of the storage unit to which data is to be written, so as to apply a second voltage to the first gate of the read transistor through the write bit line, so that in the reading operation phase, when the written data is 1, the read transistor is turned on, and when the written data is 0, the read transistor is turned off.

4. The memory according to claim 1, characterized in that: A write word line connects the write transistors of the plurality of memory cells; A read word line connects the read transistors of the plurality of memory cells; Each write transistor is connected to a different write bit line; Each of the read transistors is connected to a different read bit line; Each read bit line of each memory cell on a read word line can read data of the corresponding memory cell at the same time.

5. The memory according to claim 1, characterized in that: The read transistor and the write transistor in a memory cell are arranged in sequence along a direction parallel to the substrate, or The read transistor and the write transistor in a memory cell are stacked and arranged along a direction perpendicular to the substrate.

6. The memory according to claim 5, characterized in that: The first semiconductor layer and the second semiconductor layer are both surrounding semiconductor layers. The first gate insulating layer and the first semiconductor layer are sequentially arranged around the side wall of the first gate; the second semiconductor layer is arranged around the side wall of the second gate.

7. The memory according to claim 6, characterized in that: The first gate extends along a first direction parallel to the substrate, the second gate extends along a direction perpendicular to the substrate, and an orthographic projection of the first gate on the substrate and an orthographic projection of the second gate on the substrate do not overlap; The first gate insulating layer and the first semiconductor layer sequentially wrap at least one end portion of the first gate along the first direction.

8. The memory according to claim 7, characterized in that: The first gate insulating layer is in contact with the first gate and the first semiconductor layer respectively; The ferroelectric material of the first gate insulating layer includes doped hafnium oxide, and the doping element in the doped hafnium oxide includes at least one of zirconium, silicon, yttrium, aluminum, and lanthanum.

9. The memory according to claim 1, characterized in that: A material of at least one of the first semiconductor layer and the second semiconductor layer includes a metal oxide semiconductor material.

10. The memory according to claim 1, characterized in that: The write transistor further includes a second gate insulating layer disposed between the second gate and the second semiconductor layer; The material of the second gate insulating layer includes a high dielectric constant material, and the high dielectric constant material includes a dielectric material with a dielectric constant value greater than 3.

9.

11. The memory according to claim 1, characterized in that: The first semiconductor layer and the second semiconductor layer in a memory cell are not connected; and / or, The second semiconductor layers of adjacent write transistors on one write word line are not connected to each other.

12. The memory according to any one of claims 1 to 4, characterized in that: The read word line and the read bit line are both located on a side of the first semiconductor layer away from the first gate, the read bit line is connected to an end of the first semiconductor layer and extends along a second direction parallel to the substrate, and the read word line surrounds an outer side wall of the first semiconductor layer and extends along a direction perpendicular to the substrate; The write bit line and the first gate are arranged at intervals in the first direction and are respectively connected to different regions of the side wall of the second semiconductor layer, the write bit line extends along the second direction, and the write word line extends along a direction perpendicular to the substrate; The second direction intersects with the first direction.

13. The memory according to claim 12, characterized in that: The memory comprises a plurality of layers of first memory cell arrays, each layer of the first memory cell arrays comprises a plurality of memory cells arranged in an array along a first direction and a second direction; One of the read bit lines is connected to a plurality of read transistors in a column of a first memory cell array spaced apart along a second direction; One of the write bit lines is connected to a plurality of write transistors in a column spaced apart and distributed along a second direction in a first memory cell array of a layer; One of the read word lines connects a plurality of read transistors stacked along a direction perpendicular to the substrate; One of the write word lines connects a plurality of write transistors stacked along a direction perpendicular to the substrate; The read bit lines corresponding to the read transistors connected to one of the read word lines can read the data of the storage cells in parallel.

14. A method for accessing a memory, characterized in that: The memory comprises a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, a plurality of write word lines and a plurality of storage cells arranged in an array; the storage cell comprises a read transistor and a write transistor, the read word line and the read bit line are respectively connected to a first semiconductor layer of the read transistor, the write bit line and a first gate of the read transistor are respectively connected to a second semiconductor layer of the write transistor, the write word line is connected to a second gate of the write transistor, a first gate insulating layer is provided between the first gate and the first semiconductor layer, and the first gate insulating layer comprises a ferroelectric material layer; The memory access method includes a data writing operation and a data reading operation; after the data writing operation and before the data reading operation, the access method further includes: Applying a turn-on voltage to at least all other write word lines except the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off; The data reading operation includes: Different voltages are applied to a read word line and a read bit line connected to the storage cell to be written with data, and the write data of the storage cell is determined according to the data sensed on the read bit line.

15. The memory access method according to claim 14, characterized in that: Applying a turn-on voltage to at least all other write word lines other than the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off, including: An on voltage is applied to all write word lines to turn on the corresponding write transistors, and a first voltage is applied to the first gate of each read transistor through the write bit line corresponding to each write transistor to turn off the read transistors of all memory cells.

16. The memory access method according to claim 14, characterized in that: After applying a turn-on voltage to all other write word lines other than the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off, and before performing the data reading operation, the access method further includes: The write transistor is controlled to be turned on through the write word line of the storage unit to which data is to be written, so as to apply a second voltage to the first gate of the read transistor through the write bit line, so that when the data written in the read operation phase is 1, the read transistor is turned on, and when the data written is 0, the read transistor is turned off.

17. The memory access method according to any one of claims 14 to 16, characterized in that: After applying a turn-on voltage to all other write word lines other than the write word line connected to the storage unit to be written with data, so that the corresponding write transistors are turned on, and applying a first voltage to the first gate of each read transistor through the write bit line corresponding to each write transistor, so that each read transistor is turned off, and before performing the data reading operation, the access method further includes: A shutdown voltage is applied to at least all other write word lines except the write word line connected to the storage unit to be written with data, so as to shut down the corresponding write transistors.

18. The memory access method according to claim 16, characterized in that: After controlling the write transistor to be turned on through the write word line of the storage unit to be written with data so as to apply a second voltage to the first gate of the read transistor through the write bit line and before performing a data reading operation, the access method further includes: A turn-off voltage is applied to the write word line of the memory cell to be written with data, so as to turn off the corresponding write transistors.

19. The memory access method according to any one of claims 14 to 16, characterized in that: The data writing operation includes: Applying a turn-on voltage to a write word line shared by the plurality of storage cells to be written with data, so that the write transistors of the plurality of storage cells to be written with data are all turned on; Applying a first write voltage or a second write voltage to a plurality of write bit lines connected one-to-one with a plurality of storage cells to be written with data, respectively, so as to write the first data or the second data into the ferroelectric material layer of the corresponding storage cells to be written with data; Applying a shutdown voltage to the write word line to turn off the write transistors of the plurality of storage cells to be written with data; wherein: The read transistor and the write transistor are n-type transistors; A voltage value of the second voltage is smaller than a voltage value of the first write voltage, and smaller than a voltage value of the second write voltage; A voltage value of the first voltage is smaller than a voltage value of the first write voltage, and smaller than a voltage value of the second write voltage.

20. The memory access method according to any one of claims 14 to 16, characterized in that: The read transistor and the write transistor are n-type transistors; The data writing operation includes: Applying a conduction voltage one by one to a plurality of write word lines respectively connected to at least a portion of the storage cells to be written that do not overlap with the orthographic projection on the substrate, so as to turn on the write transistors of one or more storage cells to be written that are connected to the write word lines to which the conduction voltage is currently applied; Applying a first write voltage or a second write voltage to one or more write bit lines connected one by one to one of the one or more storage cells to be written with data in which the current write transistor is turned on, so as to write the first data or the second data into the first gate insulating layer of the corresponding storage cells to be written; Applying a turn-off voltage to the write word line currently applying the turn-on voltage, so as to turn off the write transistors of one or more storage units to be written with data connected to the write word line currently applying the turn-off voltage; wherein: A voltage value of the second voltage is smaller than a voltage value of the first write voltage, and smaller than a voltage value of the second write voltage; A voltage value of the first voltage is smaller than a voltage value of the first write voltage, and smaller than a voltage value of the second write voltage.

21. An electronic device, characterized in that: A memory comprising any one of claims 1 to 13; or a memory accessed using the memory access method of any one of claims 14 to 20.

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