Storage and calculation integrated data selector with extensible data input end

Abstract

The invention discloses a storage and calculation integrated data selector with an extensible data input end, which consists of a basic storage and calculation integrated either-or data selector and a plurality of extended data input circuits, the basic storage and calculation integrated alternative data selector is provided with a first to-be-selected data signal input end, a second to-be-selected data signal input end, a data selection control input end, a first grid input end, a second grid input end, an output control signal input end and a selector output end, and comprises two ferroelectric transistors, three nMOS (n-channel metal oxide semiconductor) transistors and two phase inverters; each expansion data input circuit is used for expanding two to-be-selected data signal input ends and adding a data selection control input end; on the basis of a basic storage and calculation integrated either-or data selector, 2m (m is greater than or equal to 1) nMOS transistors are introduced and connected according to a certain rule, the function of the m + 1 basic storage and calculation integrated either-or data selector is expanded, the number of the used nMOS transistors and inverters is small, and the circuit area can be saved.

Description

Technical Field

[0001] The present invention relates to a storage-computation integrated logic circuit design, and in particular to a storage-computation integrated data selector with an expandable data input terminal. Background Art

[0002] In recent years, with the rapid development of big data and artificial intelligence, people's demand for computing power has risen sharply, and this growth rate has significantly exceeded the speed of hardware performance improvement predicted by Moore's Law. In addition, computers using the traditional von Neumann architecture have physically separated processors and memories. When processing large amounts of data, large amounts of data will be frequently migrated between the processor and memory, resulting in the memory bandwidth far behind the improvement of CPU performance, thus creating a "storage wall"; at the same time, studies have shown that under the traditional von Neumann architecture, more than 60% of energy consumption is used for data transfer rather than data calculation, that is, there is a "power consumption wall". The existence of the "storage wall" and the "power consumption wall" has affected the improvement of the computing power of computers with the traditional von Neumann architecture. An effective way to crack the "storage wall" and the "power consumption wall" under the traditional von Neumann architecture is to adopt a storage-computing integrated architecture.

[0003] The core of storage and computing integration is to integrate storage function and computing function on the same circuit. Since there is no need for frequent data transfer between computing units and storage units, the consumption caused by data movement is greatly reduced, and computing efficiency is greatly improved.

[0004] To realize the storage-computing integration function, the support of storage media is required. Currently, storage media can be divided into two categories: one is volatile memory, which will lose data when the power is off; the other is non-volatile memory, which will not lose the stored data when the power is off. Non-volatile memory includes traditional flash memory, resistive random access memory RRAM, magnetic memory MRAM, phase change memory PCRAM, ferroelectric transistor (FeFET), etc. Among these memories, ferroelectric transistor (FeFET) has received special attention due to its low power consumption, high switching ratio and compatibility with existing CMOS processes.

[0005] In digital circuits, a data selector is a basic combinational logic circuit that is used to select one output from multiple input signals. A 2-to-1 multiplexer is a simple data selector that has two input terminals and a selection terminal. Depending on the value of the selection terminal, the 2-to-1 multiplexer will output one of the input signals of the two input terminals. 2-to-1 multiplexers are widely used in digital circuit design. For example, 2-to-1 multiplexers are used in multiplexers in CPUs. They can select different registers as data inputs, thereby reading or writing data in different registers. In addition, by appropriately assigning values ​​to the data input and address input of the 2-to-1 multiplexer, basic logic operations such as "AND", "OR", and "NOT" can be implemented. Therefore, any combinational logic circuit can be implemented using a 2-to-1 multiplexer.

[0006] In the exploration of storage-computing integrated technology, Tsinghua University applied for an invention patent application named "Data processing method based on storage-computing integrated architecture". This method improves the computing efficiency of storage-computing integrated architecture through sparse coding and load balancing. In addition, some companies such as Qianxin Technology are studying the design of high-computing storage-computing integrated circuits based on RRAM and MRAM. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a storage-computing integrated data selector with expandable data input terminal, which realizes a basic storage-computing integrated two-choice data selector by utilizing ferroelectric transistors (FeFETs), nMOS transistors and inverters, and on the basis of the basic storage-computing integrated two-choice data selector, by introducing 2m (m≥1) nMOS transistors and connecting them according to certain rules, one basic storage-computing integrated two-choice data selector function can be expanded into (m+1) basic storage-computing integrated two-choice data selector functions, and the number of nMOS transistors and inverters used is small, which can save circuit area.

[0008] The technical solution adopted by the present invention to solve the above technical problems is: a storage and computing integrated data selector with expandable data input terminal, characterized in that it is composed of a basic storage and computing integrated two-choice data selector and a plurality of extended data input circuits; the basic storage and computing integrated two-choice data selector has a first data signal input terminal to be selected, a second data signal input terminal to be selected, a data selection control input terminal, a first gate input terminal, a second gate input terminal, an output control signal input terminal, and a selector output terminal; the basic storage and computing integrated two-choice data selector includes a first ferroelectric transistor, a second ferroelectric transistor, a first nMOS transistor, a second nMOS transistor, a third nMOS transistor, a first inverter, and a second inverter; the source of the first nMOS transistor is connected to the first data signal input terminal to be selected, the gate of the first nMOS transistor is connected to the data selection control input terminal, the drain of the first nMOS transistor is connected to the source of the first ferroelectric transistor, and the gate of the first ferroelectric transistor is connected to the first The gate input terminal is connected, the drain of the first ferroelectric transistor is connected to the drain of the second ferroelectric transistor, the gate of the second ferroelectric transistor is connected to the second gate input terminal, the source of the second ferroelectric transistor is connected to the drain of the second nMOS transistor, the gate of the second nMOS transistor is connected to the data selection control input terminal, the source of the second nMOS transistor is connected to the second data signal input terminal to be selected, the input terminal of the first inverter is simultaneously connected to the drain of the first ferroelectric transistor and the drain of the second ferroelectric transistor, the output terminal of the first inverter is connected to the source of the third nMOS transistor, the gate of the third nMOS transistor is connected to the output control signal input terminal, the drain of the third nMOS transistor is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the selector output terminal; each of the extended data input circuits is used to expand two data signal input terminals to be selected and simultaneously increase a data selection control input terminal.

[0009] The number of the extended data input circuits is m, where m≥1; the i-th extended data input circuit has two extended data signal input terminals to be selected and an additional data selection control input terminal, and the i-th extended data input circuit includes two nMOS transistors, the source of the first nMOS transistor is connected to the extended first data signal input terminal to be selected, the gate of the first nMOS transistor is connected to the additional data selection control input terminal, the drain of the first nMOS transistor is connected to the source of the first ferroelectric transistor, the drain of the second nMOS transistor is connected to the source of the second ferroelectric transistor, the gate of the second nMOS transistor is connected to the additional data selection control input terminal, and the source of the second nMOS transistor is connected to the extended second data signal input terminal to be selected, where 1≤i≤m.

[0010] Compared with the prior art, the advantages of the present invention are:

[0011] The two ferroelectric transistors, two inverters and nMOS transistors for output control in the present invention can realize time-sharing sharing. When k (k≥1) basic storage-computing-in-one two-choice data selector functions need to be realized, if the basic storage-computing-in-one two-choice data selector is directly adopted to realize it, 3k nMOS transistors, 2k n-type ferroelectric transistors and 2k inverters are required. However, if the storage-computing-in-one data selector with expandable data input end of the present invention is adopted, only 2k+1 nMOS transistors, two ferroelectric transistors and two inverters are required. The larger k is, the more nMOS transistors and inverters used in the circuit structure of the present invention are saved, and thus the circuit area is saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of an n-type ferroelectric transistor (FeFET);

[0013] Figure 2 is a schematic diagram of an nMOS transistor;

[0014] Figure 3 is a schematic diagram of an inverter;

[0015] Figure 4 This is a schematic diagram of a basic storage-computing-in-one two-choice data selector;

[0016] Figure 5 A schematic diagram of an expanded data selector whose logical function is equivalent to three basic storage-computing integrated two-choice data selectors;

[0017] Figure 6 for Figure 5 Middle A 0 ,A 1 ,A2 The end is {A 0 , A 1 , A 2}={0,0,1},B 0 ,B 1 ,B 2 The end is {B 0 , B 1 , B 2}={1,1,0}, and the simulation results when the three address variables input in time sharing are (1,0,0) respectively. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiment of the present invention more clear, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the examples of the present invention.

[0019] The present invention proposes a storage-computing integrated data selector with expandable data input terminal, which realizes a basic storage-computing integrated two-choice data selector by utilizing ferroelectric transistors (FeFETs), nMOS transistors and inverters, and on the basis of the basic storage-computing integrated two-choice data selector, introduces 2m (m≥1) nMOS transistors and connects them according to certain rules, so that one basic storage-computing integrated two-choice data selector can be expanded into (m+1) basic storage-computing integrated two-choice data selectors.

[0020] Figure 1 A schematic diagram of an n-type ferroelectric transistor (FeFET) is given, where g is the gate of the FeFET, s is the source of the FeFET, and d is the drain of the FeFET. When a forward bias voltage is applied between the g-end and the s-end of the n-type FeFET, and the forward bias voltage is greater than a certain threshold, the d-end and the s-end of the n-type FeFET will be in a low resistance state, and the low resistance state will be retained; when a reverse bias voltage is applied between the g-end and the s-end of the n-type FeFET, and the reverse bias voltage is greater than a certain threshold, the d-end and the s-end of the n-type FeFET will be in a high resistance state, and the high resistance state will be retained. The high or low resistance state between the d-end and the s-end of the n-type FeFET will be maintained even after power is turned off.

[0021] Figure 2 A schematic diagram of an nMOS transistor is given, where g M is the gate of nMOS, s M is the source of nMOS, d M The drain of nMOS. M and d M The conduction between the gate and M The voltage applied. M andM When the applied voltage between is greater than the turn-on voltage, s M and d M When g M and M When the applied voltage between is less than the turn-on voltage, s M and d M In the off state.

[0022] Figure 3 A schematic diagram of an inverter is given, where in is the input terminal and out is the output terminal. Let "0" represent a logic low level and "1" represent a logic high level. When in=0, out=1; when in=1, out=0.

[0023] Embodiment 1:

[0024] This embodiment proposes a storage and computing integrated data selector, such as Figure 4 As shown, it is composed of only one basic storage and computing integrated two-choice data selector, and the basic storage and computing integrated two-choice data selector has a first to-be-selected data signal input terminal A 0 , the second selected data signal input terminal B 0 , data selection control input terminal sel 0 , the first gate input terminal V g1 , the second gate input terminal V g2 , an output control signal input terminal pass, a selector output terminal Q, a basic storage and computing integrated two-choice data selector includes a first ferroelectric transistor f 1 , the second ferroelectric transistor f 2 , the first nMOS transistor t 00 , the second nMOS transistor t 01 , the third nMOS transistor t p , the first inverter INV 1 , the second inverter INV 2 , the first nMOS transistor t 00 The source of the first selected data signal input terminal A 0 connected, the first nMOS transistor t 00 The gate and data selection control input terminal sel 0 connected, the first nMOS transistor t 00 The drain of the first ferroelectric transistor f 1 The source of the first ferroelectric transistor f 1 The gate of the first gate input terminal V g1 connected, the first ferroelectric transistor f 1 The drain of the second ferroelectric transistor f 2 The drain of the second ferroelectric transistor f2 The gate and the second gate input terminal V g2 connected, the second ferroelectric transistor f 2 The source of the second nMOS transistor t 01 The drain of the second nMOS transistor t 01 The gate and data selection control input terminal sel 0 connected, the second nMOS transistor t 01 The source of the second selected data signal input terminal B 0 connected, the first inverter INV 1 The input terminal of the first ferroelectric transistor f 1 The drain of the second ferroelectric transistor f 2 The drain of the first inverter INV 1 The output terminal of the third nMOS transistor t p The source of the third nMOS transistor t p The gate of the third nMOS transistor t is connected to the output control signal input terminal pass. p The drain of the second inverter INV 2 The input terminal of the second inverter INV 2 The output end of is connected to the selector output end Q.

[0025] Embodiment 2:

[0026] This embodiment proposes a storage and computing integrated data selector, such as Figure 5 As shown, in Figure 4 Two extended data input circuits are added to the basis of the basic storage and computing integrated two-choice data selector shown, that is, it is composed of a basic storage and computing integrated two-choice data selector and two extended data input circuits, each extended data input circuit is used to expand two data signal input terminals to be selected, and at the same time add a data selection control input terminal, that is, the number of extended data signal input terminals to be selected should be a multiple of 2, that is, 2, 4, 6, 8 and so on.

[0027] The first extended data input circuit has two extended data signal input terminals A to be selected. 1 and B 1 , an additional data selection control input terminal sel 1 The first extended data input circuit includes two nMOS transistors t 10 and t 11 , the first nMOS transistor t 10 The source of the extended first selected data signal input terminal A 1 connected, the first nMOS transistor t 10 The gate and the added data selection control input terminal sel1 connected, the first nMOS transistor t 10 The drain of the first ferroelectric transistor f 1 The source of the second nMOS transistor t 11 The drain of the second ferroelectric transistor f 2 The source of the second nMOS transistor t 11 The gate and the added data selection control input terminal sel 1 connected, the second nMOS transistor t 11 The source of the second data signal input terminal B to be selected 1 connected.

[0028] The second extended data input circuit has two extended data signal input terminals A to be selected. 2 and B 2 , an additional data selection control input terminal sel 2 The second extended data input circuit includes two nMOS transistors t 20 and t 21 , the first nMOS transistor t 20 The source of the extended first selected data signal input terminal A 2 connected, the first nMOS transistor t 20 The gate and the added data selection control input terminal sel 2 connected, the first nMOS transistor t 20 The drain of the first ferroelectric transistor f 1 The source of the second nMOS transistor t 21 The drain of the second ferroelectric transistor f 2 The source of the second nMOS transistor t 21 The gate and the added data selection control input terminal sel 2 connected, the second nMOS transistor t 21 The source of the second data signal input terminal B to be selected 2 connected.

[0029] Figure 5 The storage and computing integrated data selector shown is in Figure 4 On the basis of the basic storage and computing integrated two-to-one data selector shown, four nMOS transistors are introduced, and the input terminal of the data signal to be selected is expanded to six, and the logic function is equivalent to three basic storage and computing integrated two-to-one data selectors.

[0030] To further illustrate the feasibility of the storage and computing integrated data selector of the present invention, Figure 5 The storage and computing integrated data selector shown is used for simulation experiments.

[0031] In the simulation experiment, a positive pulse is applied to the g-terminal of the n-type ferroelectric transistor (FeFET), so that a large forward bias is generated between the g-terminal and the s-terminal, so that the d-terminal and the s-terminal of the n-type ferroelectric transistor (FeFET) are in a low-resistance state; a negative pulse is applied to the g-terminal of the n-type ferroelectric transistor (FeFET), so that a large reverse bias is generated between the g-terminal and the s-terminal, so that the d-terminal and the s-terminal of the n-type ferroelectric transistor (FeFET) are in a high-resistance state. "0" is used to represent a logical low level, "1" is used to represent a logical high level, "L" indicates that the ferroelectric transistor is in a low-resistance state, and "H" indicates that the ferroelectric transistor is in a high-resistance state.

[0032] Figure 6 Yes Figure 5 The simulation results of the storage and computing integrated data selector shown in FIG. 1 are shown in FIG. 1 , where the initial value Q of the selector output terminal Q is Q=0. 0 ,A 1 ,A 2 The initial value of the terminal is {A 0 , A 1 , A 2}={0,0,1},in B 0 ,B 1 ,B 2 The initial value of the terminal is {B 0 , B 1 , B 2}={1,1,0}, and the three address variable values ​​input in time sharing are (1,0,0) respectively.

[0033] Figure 6 In, V g1 Terminal and V g2 The pulse at the end is generated by a special circuit, and V g1 Terminal and V g2 The relationship between the pulse at the end and the address variable value is: when the address variable value is logic "1", V g1 The positive pulse is V g2 The end is a negative pulse; when the address variable value is logic "0", V g1 The negative pulse is V g2 The end is a positive pulse.

[0034] Figure 6 At time T1, V g1 A positive pulse is applied to the end, V g2 A negative pulse is applied to the terminal, and the address variable value corresponding to the first input is 1, making Figure 5 The first ferroelectric transistor f 1 The gate and source of the second ferroelectric transistor f 2 The gate and source of the first ferroelectric transistor f are reverse biased. 1In the low resistance state, denoted as "L", the second ferroelectric transistor f 2 In high impedance state, recorded as "H". At time T2, only sel 0 A positive pulse is applied to the Figure 5 The first nMOS transistor t 00 and the second nMOS transistor t 01 is turned on, but since the first ferroelectric transistor f 1 In the low resistance state, the second ferroelectric transistor f 2 In high impedance state, so only A 0 =0 is transmitted to the first inverter INV 1 The input terminal of the first inverter INV 1 output, so the first inverter INV 1 The output of is 1. At time T3, the output control signal input terminal pass (the third nMOS transistor t p The gate of the third nMOS transistor t p The first inverter INV is turned on. 1 The output of the second inverter INV 2 Output from the selector output terminal Q, the value of the Q terminal is 0.

[0035] At time T4, V g1 A negative pulse is applied to the V g2 A positive pulse is applied to the end, and the address variable value corresponding to the second input is 0, making Figure 5 The first ferroelectric transistor f 1 The gate and source of the second ferroelectric transistor f 2 The gate and source of the first ferroelectric transistor f are in forward bias. 1 In high resistance state, denoted as "H", the second ferroelectric transistor f 2 In the low resistance state, recorded as "L". At time T5, only sel 1 A positive pulse is applied to the Figure 5 The two nMOS transistors t in the first extended data input circuit 10 and t 11 is turned on, but since the first ferroelectric transistor f 1 In high resistance state, the second ferroelectric transistor f 2 In low resistance state, so only B 1 =1 is transmitted to the first inverter INV 1 The input terminal of the first inverter INV 1 output, so the first inverter INV 1The output of is 0. At time T6, the output control signal input terminal pass (the third nMOS transistor t p The gate of the third nMOS transistor t p The first inverter INV is turned on. 1 The output of the second inverter INV 2 Output from the selector output terminal Q, the value of the Q terminal is 1.

[0036] At time T7, V g1 A negative pulse is applied to the V g2 A positive pulse is applied to the end, and the address variable value corresponding to the third input is 0, making Figure 5 The first ferroelectric transistor f 1 The gate and source of the second ferroelectric transistor f 2 The gate and source of the first ferroelectric transistor f are in forward bias. 1 In high resistance state, denoted as "H", the second ferroelectric transistor f 2 In the low resistance state, recorded as "L". At time T8, only sel 2 A positive pulse is applied to the Figure 5 The two nMOS transistors in the second extended data input circuit are t 20 and t 21 However, due to the first ferroelectric transistor f 1 In high resistance state, the second ferroelectric transistor f 2 In low resistance state, so only B 2 =0 is transmitted to the first inverter INV 1 The input terminal of the first inverter INV 1 output, so the first inverter INV 1 The output of is 1. At time T9, the output control signal input terminal pass (the third nMOS transistor t p The gate of the third nMOS transistor t p The first inverter INV is turned on. 1 The output of the second inverter INV 2 Output from the selector output terminal Q, the value of the Q terminal is 0.

Claims

1. A storage and computing integrated data selector with expandable data input end, characterized in that The invention is composed of a basic storage-computing integrated two-choice data selector and a plurality of extended data input circuits; the basic storage-computing integrated two-choice data selector has a first data signal input terminal to be selected, a second data signal input terminal to be selected, a data selection control input terminal, a first gate input terminal, a second gate input terminal, an output control signal input terminal, and a selector output terminal; the basic storage-computing integrated two-choice data selector includes a first ferroelectric transistor, a second ferroelectric transistor, a first nMOS transistor, a second nMOS transistor, a third nMOS transistor, a first inverter, and a second inverter; the source of the first nMOS transistor is connected to the first data signal input terminal to be selected, the gate of the first nMOS transistor is connected to the data selection control input terminal, the drain of the first nMOS transistor is connected to the source of the first ferroelectric transistor, the gate of the first ferroelectric transistor is connected to the first gate input terminal, and the drain of the first ferroelectric transistor is connected to the The drain of the second ferroelectric transistor is connected, the gate of the second ferroelectric transistor is connected to the second gate input terminal, the source of the second ferroelectric transistor is connected to the drain of the second nMOS transistor, the gate of the second nMOS transistor is connected to the data selection control input terminal, the source of the second nMOS transistor is connected to the second data signal input terminal to be selected, the input terminal of the first inverter is simultaneously connected to the drain of the first ferroelectric transistor and the drain of the second ferroelectric transistor, the output terminal of the first inverter is connected to the source of the third nMOS transistor, the gate of the third nMOS transistor is connected to the output control signal input terminal, the drain of the third nMOS transistor is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the selector output terminal; each of the extended data input circuits is used to expand two data signal input terminals to be selected and simultaneously add a data selection control input terminal.

2. A data selector with expandable data input terminal and integrated storage and computing according to claim 1, characterized in that The number of the extended data input circuits is m, where m≥1; the i-th extended data input circuit has two extended data signal input terminals to be selected and an additional data selection control input terminal, and the i-th extended data input circuit includes two nMOS transistors, the source of the first nMOS transistor is connected to the extended first data signal input terminal to be selected, the gate of the first nMOS transistor is connected to the additional data selection control input terminal, the drain of the first nMOS transistor is connected to the source of the first ferroelectric transistor, the drain of the second nMOS transistor is connected to the source of the second ferroelectric transistor, the gate of the second nMOS transistor is connected to the additional data selection control input terminal, and the source of the second nMOS transistor is connected to the extended second data signal input terminal to be selected, where 1≤i≤m.

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