memory

Abstract

This disclosure relates to the field of semiconductor technology, and in particular to a memory, the memory comprising: a memory cell array including a first edge region, a connection region, and a second edge region arranged along a first direction, wherein the connection region is located between the first edge region and the second edge region; a plurality of driving lines extending along the first direction, each driving line being coupled to a column of memory cells arranged along the first direction and including a first end region, a middle region, and a second end region, wherein the first end region corresponds to the first edge region, the middle region corresponds to the connection region, and the second end region corresponds to the second edge region; and a plurality of control lines extending along the first direction and corresponding to the driving lines, wherein the control lines are electrically connected to the middle region corresponding to the driving lines and to at least one of the first end region and the second end region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory. Background Technology

[0002] Memory is used to store information in various electronic devices (such as computers, wireless communication devices, and cameras), and the information is stored by controlling different states of the memory. With the rapid development of artificial intelligence technology, higher requirements are placed on the computing performance, read performance, write performance, reliability, and data retention capabilities of electronic devices.

[0003] As the feature size of memory cells approaches its lower limit, further increasing the feature size of memory cells in planar processes and manufacturing technologies becomes challenging and costly. 3D memory architectures can solve the density limitations in planar memory cells.

[0004] To selectively activate word lines (WL) and bit lines (BL), the memory includes a word line driver and a bit line driver. The word line driver is coupled to the word line via word line contacts and is used to decode the word line address, thereby activating the word line when addressing a specific word line. The bit line driver is coupled to the bit line via bit line contacts and is used to decode the bit line address, thereby activating the bit line when addressing a specific bit line.

[0005] However, the voltage drop on the word line and bit line increases significantly with the increase of the line length (word line length or bit line length) between the contact and the target memory cell, and may lead to insufficient current at the target memory cell, resulting in read / write errors in the memory. Summary of the Invention

[0006] The primary objective of this disclosure is to provide a memory designed to improve the driving capability of the drive structure in the memory cell to the drive line.

[0007] To achieve the above objectives, this disclosure proposes a memory, comprising: a memory cell array including a first edge region, a connecting region, and a second edge region arranged along a first direction, wherein the connecting region is located between the first edge region and the second edge region; a plurality of driving lines extending along the first direction, each driving line being coupled to a column of memory cells arranged along the first direction and including a first end region, a middle region, and a second end region, wherein the first end region corresponds to the first edge region, the middle region corresponds to the connecting region, and the second end region corresponds to the second edge region; and a plurality of control lines extending along the first direction and corresponding to the driving lines, wherein the control lines are electrically connected to the middle region corresponding to the driving lines and are electrically connected to at least one of the first end region and the second end region.

[0008] In some embodiments, the resistivity of the control line is less than that of the drive line.

[0009] In some embodiments, the drive line is made of tungsten, and the control line is made of copper.

[0010] In some embodiments, the memory further includes a driving structure located in at least one of the connection region, the first edge region, or the second edge region, the driving structure being electrically connected to the control line.

[0011] In some embodiments, the drive structure is symmetrically disposed in the first edge region and the second edge region. One end of the control line is electrically connected to the drive structure in the first end region and the first edge region of the corresponding drive line, and the other end is electrically connected to the drive structure in the second end region and the second edge region of the corresponding drive line. The middle end is connected to the middle region of the corresponding drive line.

[0012] In some embodiments, the drive structure is located in the connection region, and the control line includes a first sub-control line and a second sub-control line. One end of the first sub-control line and one end of the second sub-control line are respectively connected to the drive structure, the other end of the first sub-control line is connected to the first end region, and the other end of the second sub-control line is connected to the second end region.

[0013] In some embodiments, the distance from the first sub-control line to the drive line may be the same as or different from the distance from the second sub-control line to the drive line.

[0014] In some embodiments, between the drive structure and the first end region or between the drive structure and the second end region, the first sub-control line of any control line is adjacent to the second sub-control line of the adjacent control line, or the first sub-control line of any control line is adjacent to the first sub-control line of the adjacent control line.

[0015] In some embodiments, the drive lines include word lines and / or bit lines.

[0016] In some embodiments, the storage cell array includes multiple stacked storage cell arrays, wherein the connection region of any layer of the storage cell array overlaps with the projection of the first edge region or the second edge region of the adjacent layer of the storage cell array onto the array plane of the storage cell array.

[0017] The technical solution disclosed herein has the following beneficial effects:

[0018] In addition to the driving structure based on the driving lines, control lines corresponding one-to-one with the driving lines are also set. The driving structure indirectly drives the driving lines through the control lines. The control lines and driving lines are connected through multiple contacts, which reduces the line length between the contacts on the word lines and bit lines and the target memory cell. In addition, the resistance of the control lines can be adjusted by controlling the resistivity and width of the control lines, so as to adjust the driving capability of the driving structure to the target memory cell and avoid the limitation of the driving capability of the target memory cell by the width of the word lines and bit lines.

[0019] In some embodiments, by reducing the resistance of the control line, the resistance between the drive structure and the target memory cell on the drive line is reduced, thereby improving the drive capability of the drive structure and avoiding read / write errors in the memory. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this disclosure. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a single memory cell array in the word line direction provided in an embodiment of the present disclosure;

[0022] Figure 2 This is a schematic diagram of the structure of a single memory cell array in the bit line direction provided in an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of the connection structure of a drive structure, control line, and drive line provided in an embodiment of this disclosure;

[0024] Figure 4 A schematic diagram of another driving structure, control line, and driving line connection structure provided in an embodiment of this disclosure;

[0025] Figure 5A schematic diagram of another driving structure, control line, and driving line connection structure provided in an embodiment of this disclosure;

[0026] Figure 6 A schematic diagram of the layout structure of a first sub-control line and a second sub-control line provided in an embodiment of this disclosure;

[0027] Figure 7 A schematic diagram of another layout structure of the first sub-control line and the second sub-control line provided in an embodiment of this disclosure;

[0028] Figure 8 This is a schematic diagram of the connection structure of the driving structure, control line and driving line corresponding to the multi-layer storage cell array provided in the embodiments of this disclosure.

[0029] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0030] As is known from the background art, 3D memory architecture can solve the density limitations in planar memory cells. In 3D phase change memory (3D-PCM), bit lines and word lines are formed of tungsten (W) with relatively high resistivity; however, due to electron scattering at the surface and grain boundaries, the resistivity of tungsten increases rapidly as the critical size (CD) decreases.

[0031] In addition, to selectively activate word lines (WL) and bit lines (BL), the memory includes a word line driver and a bit line driver. The word line driver is coupled to the word line via word line contacts and is used to decode the word line address, thereby activating the word line when addressing a specific word line. The bit line driver is coupled to the bit line via bit line contacts and is used to decode the bit line address, thereby activating the bit line when addressing a specific bit line.

[0032] The voltage drop on word lines and bit lines increases significantly with the increase of the line length (word line length or bit line length) between the contact and the target memory cell, and may lead to insufficient current at the target memory cell, resulting in memory read / write errors. In this case, compensating for the voltage on word lines and bit lines can avoid the voltage drop problem caused by line length to some extent, but it will lead to excessive current at other memory cells along that word line or bit line.

[0033] In summary, the reasons why the memory density of 3D phase-change memory cannot be further improved include: (1) In order to reduce the resistance of word lines and bit lines, word lines and bit lines need to be guaranteed to a certain width, which makes it impossible to further compress the memory array area; (2) In order to ensure the driving capability of the driver structure, the length of word lines and bit lines needs to be shortened, which increases the number of driver structures in the memory and occupies part of the device area.

[0034] This embodiment proposes a memory, comprising: a memory cell array including a first edge region, a connecting region, and a second edge region arranged along a first direction, wherein the connecting region is located between the first edge region and the second edge region; a plurality of driving lines extending along the first direction, each driving line being coupled to a column of memory cells arranged along the first direction and including a first end region, a middle region, and a second end region, wherein the first end region corresponds to the first edge region, the middle region corresponds to the connecting region, and the second end region corresponds to the second edge region; and a plurality of control lines extending along the first direction and corresponding to the driving lines, wherein the control lines are electrically connected to the middle region corresponding to the driving lines and to at least one of the first end region and the second end region.

[0035] The memory provided in this embodiment, in addition to the driving structure based on driving lines, also includes control lines that correspond one-to-one with the driving lines. The driving structure indirectly drives the driving lines through the control lines. The control lines and driving lines are connected through multiple contacts, reducing the line length between the contacts on the word lines and bit lines and the target memory cell. Furthermore, the resistance of the control lines can be adjusted by regulating their resistivity and width, thereby adjusting the driving capability of the driving structure to the target memory cell and avoiding the limitation imposed by the width of the word lines and bit lines on the driving capability of the target memory cell.

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0037] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0038] For the memory provided in this embodiment, the driving lines include word lines WL and / or bit lines BL. If the driving lines are only exemplified by word lines WL, then word lines WL extend along a first direction, and bit lines BL extend along a second direction. If the driving lines are only exemplified by bit lines BL, then bit lines BL extend along a first direction, and word lines WL extend along a second direction. If the driving lines include both word lines WL and bit lines BL, then word lines WL extend along a first direction, and bit lines BL extend along a second direction.

[0039] It should be noted that the memory provided in this embodiment can be implemented based on word lines (WL) or bit lines (BL), or a combination of embodiments with word lines (WL) and embodiments with bit lines (BL).

[0040] It should also be noted that, in order to illustrate the difference between memory based on word lines WL or bit lines BL, when the drive line is word line WL, the control lines are described based on the first control line; when the drive line is bit line BL, the control lines are described based on the second control line.

[0041] In some embodiments, the first direction and the second direction are perpendicular to each other.

[0042] Figure 1 This is a schematic diagram of the structure of a single memory cell array in the word line direction provided in this embodiment. Figure 2 This is a schematic diagram of the structure of a single memory cell array in the bit line direction provided in this embodiment.

[0043] In some embodiments, if the driver line is a word line WL, refer to Figure 1The memory includes a memory cell array 100, comprising a first edge region 201, a connection region 200, and a second edge region 202 arranged along a first direction (X direction, where the second direction is Y direction), with the connection region 200 located between the first edge region 201 and the second edge region 202. A plurality of word lines 210 extending along the first direction are coupled to a column of memory cells arranged along the first direction, and each word line 210 includes a first end region, a middle region, and a second end region. The first end region corresponds to the first edge region, the middle region corresponds to the connection region, and the second end region corresponds to the second edge region. A plurality of first control lines extending along the first direction and corresponding to the word lines 210 are electrically connected to the middle region of the corresponding word line 210 and to at least one of the first end region and the second end region.

[0044] In some embodiments, if the driving line is a bit line BL, refer to Figure 2 The memory includes a memory cell array 100, comprising a first edge region 201, a connection region 200, and a second edge region 202 arranged along a first direction (Y direction, where the second direction is X direction), with the connection region 200 located between the first edge region 201 and the second edge region 202. A plurality of bit lines 220 extending along the first direction are coupled to a column of memory cells arranged along the first direction, and each bit line 220 includes a first end region, a middle region, and a second end region. The first end region corresponds to the first edge region, the middle region corresponds to the connection region, and the second end region corresponds to the second edge region. A plurality of second control lines extending along the first direction and corresponding to the bit lines 220 are electrically connected to the middle region of the corresponding bit line 220 and to at least one of the first end region and the second end region.

[0045] It should be noted that, Figure 1 and Figure 2 The memory in the example is implemented based on both word lines (WL) and bit lines (BL). However, to distinguish between driving lines based on word lines (WL) and bit lines (BL), the different ways of implementing driving lines based on word lines (WL) and bit lines (BL) are labeled separately in the accompanying drawings to illustrate the difference between driving lines based on word lines (WL) and bit lines (BL).

[0046] for Figure 1 and Figure 2 For example, the first edge region 201 and the second edge region 202 are used to increase the number of contacts on the drive line and the control line in order to reduce the line length between the contact on the drive line and the target memory cell.

[0047] In addition, compared to the drive structure driving directly through the drive line, the drive structure drives the drive line indirectly through the control line. The driving capability is determined by the control line instead of the drive line. This means that the influence of resistance on the driving capability does not need to be considered during the design of the drive line, and the size of the drive line can be further miniaturized.

[0048] In some embodiments, the resistivity of the control line is less than that of the drive line.

[0049] In one example, the control lines can be made of metals or alloys with low resistivity, such as copper (Cu) or silver (Ag). By reducing the resistance of the control lines, the resistance between the drive structure and the target memory cell on the drive line is reduced, thereby improving the drive capability of the drive structure and avoiding read / write errors in the memory.

[0050] For the storage cell array 100, the storage cell array 100 includes multiple storage cells arranged in an array, multiple storage cells arranged in the same row are coupled to the same word line 210, and multiple storage cells arranged in the same column are coupled to the same bit line 220.

[0051] In some embodiments, the memory cell array 100 may include a static random access memory cell array, a dynamic random access memory cell array, a ferroelectric random access memory cell array, or a phase change random access memory cell array.

[0052] For the connection area 200, the connection area 200 is used for the connection between the drive structure 230, the control line and the drive line. The connection area 200 is located between the first edge area 201 and the second edge area 202 to reduce the maximum value of the line length between the contact and the target memory cell.

[0053] In some embodiments, the memory further includes a drive structure 230, which is connected to at least one control line. Specifically, the drive structure 230 is connected to the control line via a conductive plug 240, and the control line is connected to the drive line via the conductive plug 240.

[0054] It should be noted that a drive structure 230 can drive one control line or multiple control lines, and the multiple control lines driven by the same drive structure 230 can be drive structures set on the same layer or drive structures set on different layers.

[0055] It should also be noted that the driving structure 230 includes word line driver and bit line driver. The word line driver is used to drive word line WL, and the bit line driver is used to drive bit line BL. The word line driver and bit line driver can be set in the same layer or different layers. Correspondingly, the control lines corresponding to the word line driver and bit line driver can also be set in the same layer or different layers.

[0056] The driving structure is located in at least one of the connection region 200, the first edge region 201, or the second edge region 202.

[0057] In some embodiments, if the drive structure is located in the connection region 200, the control line is electrically connected to the first end region and the second end region of the corresponding drive line.

[0058] In one application example, there is a first distance between the connection region 200 and the first edge region 201, and a second distance between the connection region 200 and the second edge region 202. The difference between the first distance and the second distance is less than a first preset value. By limiting the distance difference between the connection region 200 and the first edge region 201 and the second edge region 202, the difference in driving capability between the drive structure 230 and the left and right memory cells is reduced.

[0059] In one application example, the first distance and the second distance are equal; that is, the distances between each pair of the three contacts set on the connection area 200, the first edge area 201, and the second edge area 202 are equal, so as to balance the driving capability of the drive structure 230 to the left and right memory cells.

[0060] It should be noted that, Figure 1 and Figure 2 The example describes the memory provided in this embodiment using a single memory cell array 100 as an example, and does not constitute a limitation on the number of memory cell arrays 100 in the memory. The number of memory cell arrays 100 in the memory can be arbitrary.

[0061] In some embodiments, a first edge region 201 and a second edge region 202 are disposed at the edge of the storage cell array 100, and the first edge region 201 and the second edge region 202 are opposite edges of the storage cell array 100.

[0062] In some embodiments, control lines and drive lines are disposed on different layers to avoid the limitations imposed by size reduction on control line wiring.

[0063] In one example, the control line is located on the side of the drive line furthest from the memory cell. (Reference) Figure 3 , Figure 3 This is a schematic diagram illustrating the connection structure of a drive structure, control line, and drive line provided in this embodiment. Specifically, Figure 3 Can be regarded as Figure 1 The cross-sectional structural diagram at section AB can also be considered as Figure 2 A cross-sectional view of section CD. The drive structure 301 is connected to the control line 302, and the control line 302 is connected to the drive line 304 via a conductive plug.

[0064] In some embodiments, the conductive plug 240 includes a first conductive plug 303 and a second conductive plug 313, wherein the first conductive plug 303 is used for electrical connection of control line 302 and drive line 304 in connection region 200, and the second conductive plug 313 is used for electrical connection of control line 302 and drive line 304 in edge regions (first edge region 201 and second edge region 202).

[0065] exist Figure 3 In the example, the positions of control line 302 are at the same distance from drive line 304.

[0066] It should be noted that, Figure 3 In the example, the control line 302 and the driving structure 301 are disposed in the same or adjacent semiconductor layers, so the control line 302 can be directly connected to the driving structure 301. Alternatively, the control line and the driving structure can also be disposed in the spacer layer semiconductor structure, in which case the control line is connected to the driving structure through a conductive plug.

[0067] In some embodiments, Figure 3 The memory shown includes a substrate, and a first metal layer, an insulating layer, and a second metal layer located on the substrate, spaced from closest to farthest. A drive structure 301 is disposed in the substrate. The first metal layer is used for wiring control lines 302, the second metal layer is used for wiring drive lines 304, and the insulating layer is used for insulation between the first and second metal layers. A via is provided in the insulating layer, and the via is filled with conductive material to form conductive plugs (first conductive plug 303 and second conductive plug 313) to electrically connect the control lines 302 and the drive lines 304.

[0068] refer to Figure 4 , Figure 4 This is a schematic diagram illustrating another driving structure, control line, and drive line connection structure provided in this embodiment. Specifically, Figure 4 Can be regarded as Figure 1 A schematic diagram of the cross-sectional structure on section AB can also be considered as Figure 2 A cross-sectional structural diagram on a CD. In some embodiments, the control lines are located on the side of the drive lines away from the storage cells, and each control line includes a first sub-control line 401 and a second sub-control line 402. One end of the first sub-control line 401 and one end of the second sub-control line 402 are respectively connected to the drive structure 301, the other end of the first sub-control line 401 is connected to the first end region, and the other end of the second sub-control line 402 is connected to the second end region.

[0069] In some embodiments, the distance from the first sub-control line 401 to the drive line 304 may be the same as or different from the distance from the second sub-control line 402 to the drive line 304.

[0070] For example, in Figure 4In the example, the distance from the first sub-control line 401 to the drive line 304 is different from the distance from the second sub-control line 402 to the drive line 304. Specifically, the distance from the first sub-control line 401 to the drive line 304 is less than the distance from the second sub-control line 402 to the drive line 304. In other examples, the distance from the first sub-control line 401 to the drive line 304 is the same as the distance from the second sub-control line 402 to the drive line 304; see reference [link / reference]. Figure 3 Example.

[0071] Based on embodiments where the distances from the first sub-control line 401 and the second sub-control line 402 to the drive line are different. In some embodiments, refer to Figure 4 and Figure 6 , Figure 6 This is a schematic diagram of the layout structure of a first sub-control line and a second sub-control line provided in this embodiment. Figure 6 For the corresponding Figure 1 The diagram illustrates a layout of control lines for the drive structure 230. Between the drive structure 230 and the first end region or the second end region, a first sub-control line 401 of any control line is adjacent to an adjacent first sub-control line 401. In some embodiments, between the drive structure 230 and the first end region or the second end region, a second sub-control line 402 of any control line is adjacent to an adjacent second sub-control line 402. In short, control lines located on the same side of the drive structure 230 are of the same type, meaning they have the same height. By adjusting the height of the control lines on the same side, the difference in driving capability between the two sides of the drive structure 230 can be fine-tuned.

[0072] In some embodiments, the drive structure is symmetrically disposed in the first edge region and the second edge region. One end of the control line is electrically connected to the drive structure in the first end region and the first edge region of the corresponding drive line, and the other end is electrically connected to the drive structure in the second end region and the second edge region of the corresponding drive line. The middle end is connected to the middle region of the corresponding drive line.

[0073] refer to Figure 5 , Figure 5 This is a schematic diagram of another driving structure, control line, and connection structure of the driving line provided in this embodiment. The driving structure 301 is disposed in the first edge region and the second edge region, and the driving structure connects the control line 302 in both the first and second edge regions. In the first and second edge regions, the control line 302 is connected to the driving line 304 via a second conductive plug 313; in the connection region 200, the middle end of the control line 302 is connected to the middle region of the driving line 304 via a first conductive plug 303.

[0074] Based on embodiments where the distances from the first sub-control line 401 and the second sub-control line 402 to the drive line are different. In other embodiments, refer to... Figure 4 and Figure 7 , Figure 7 This is a schematic diagram of the layout structure of the second type of first sub-control line and second sub-control line provided in this embodiment. Figure 6 For the corresponding Figure 1 The diagram shows another control line layout of the drive structure 230. Between the drive structure 230 and the first end region or the second end region, the first sub-control line 401 of any control line is adjacent to the adjacent second sub-control line 402. In short, the first sub-control line 401 and the second sub-control line 402 are alternately arranged on the same side or different sides of the unique drive structure 230. By alternating the first sub-control line 401 and the second sub-control line 402 at different heights, the spacing between adjacent control lines is increased, avoiding crosstalk between adjacent control lines.

[0075] In some embodiments, the first sub-control line 401 and the second sub-control line 402 have different lengths. That is, the control lines located on the same side of the drive structure 230 have different lengths. By adjusting the length of the control lines on the same side, the difference in driving capability between the two sides of the drive structure 230 can be fine-tuned. In other embodiments, the first sub-control line 401 and the second sub-control line 402 have the same length.

[0076] In some embodiments, the widths of the first sub-control line 401 and the second sub-control line 402 are different. That is, the widths of the control lines located on the same side of the drive structure 230 are different, and the difference in driving capability between the two sides of the drive structure 230 is fine-tuned by adjusting the width of the control lines on the same side. In other embodiments, the widths of the first sub-control line 401 and the second sub-control line 402 are the same.

[0077] In some embodiments, the first sub-control line 401 and the second sub-control line 402 are made of different materials. That is, the control lines located on the same side of the drive structure 230 are made of different materials, and the difference in driving capability between the two sides of the drive structure 230 is fine-tuned by adjusting the materials of the control lines on the same side. In other embodiments, the first sub-control line 401 and the second sub-control line 402 are made of the same material.

[0078] It should be noted that whether the specific length, width and material of the first sub-control line 401 and the second sub-control line 402 are the same does not constitute a limitation on this embodiment. Those skilled in the art can combine the specific length, width and material settings of the first sub-control line 401 and the second sub-control line 402 with the location of the connection area to balance the driving capability from the connection area to the first edge area and the driving capability from the connection area to the second edge area.

[0079] In some embodiments, the storage cell array includes a multi-layer stacked storage cell array, wherein the connection region of any layer of storage cell array overlaps with the projection of a first edge region or a second edge region of an adjacent layer of storage cell array onto the array plane of the storage cell array.

[0080] In one example, suppose the storage cell array is multi-layered, and each layer of the storage cell array includes multiple such... Figure 1 and Figure 2 The illustrated memory cell array, in its stacking direction, has the following configuration: the connection area of ​​the second layer of memory cell array corresponds to the edge area (first or second edge area) of the first layer of memory cell array, and the edge area (first or second edge area) of the second layer of memory cell array corresponds to the connection area of ​​the first layer of memory cell array; similarly, the connection area of ​​the third layer of memory cell array corresponds to the edge area (first or second edge area) of the second layer of memory cell array, and the edge area (first or second edge area) of the third layer of memory cell array corresponds to the connection area of ​​the second layer of memory cell array; that is, the projection of the connection area of ​​any layer of memory cell array and the first or second edge area of ​​the adjacent layer of memory cell array onto the array plane of the memory cell array overlaps. By alternating the arrangement of the memory cell arrays, the gaps between the memory cell arrays are used to complete the wiring of the drive structure, further reducing the size of the memory.

[0081] For a two-level storage cell array, the reference Figure 8 , Figure 8 This is a schematic diagram of the connection structure of the driving structure, control line and driving line corresponding to the multi-layer memory cell array provided in this embodiment. The memory includes a first layer memory cell array 501 and a second layer memory cell array 502, wherein the second layer memory cell array 502 is located on the first layer memory cell array 501. In the stacking direction of the memory cell arrays, the connection area 520 of the second layer memory cell array 502 corresponds to the edge area (first edge area 511 or second edge area 512) of the first layer memory cell array 501, and the edge area (first edge area 521 or second edge area 522) of the second layer memory cell array 502 corresponds to the connection area 510 of the first layer memory cell array 501.

[0082] The first-layer storage cell array 501 is driven by the first driver structure 602, and the second-layer storage cell array 502 is driven by the second driver structure 601. Since the two storage cell arrays are stacked, the corresponding drive lines of the storage cell arrays are located at different heights, as shown in the figure. The first-layer storage cell array 501 corresponds to the first drive line 530, and the second-layer storage cell array 502 corresponds to the second drive line 540. The second drive line 540 is located above the first drive line 530. As mentioned above, the connection areas of different storage cells are alternately arranged, that is, the first driver structure 602 and the second driver structure 601 are alternately arranged. The drive connections corresponding to the first driver structure 602 or the second driver structure 601 can be referenced. Figure 3 and Figure 4 Specifically, control line 302 is illustrated with black lines, first conductive plug 303 with blue lines, and second conductive plug 313 with red lines; wherein, the drive connections corresponding to the first drive structure 602 or the second drive structure 601 are interleaved and superimposed to form Figure 8 For example, this embodiment will not be described in detail.

[0083] It should be noted that the memory cell array provided in this embodiment may include a static random access memory cell array, a dynamic random access memory cell array, a ferroelectric random access memory cell array, or a phase change random access memory cell array.

[0084] As mentioned above, in addition to the driving structure based on the driving lines, control lines corresponding one-to-one with the driving lines are also set up. The driving structure indirectly drives the driving lines through the control lines. The control lines and driving lines are connected through multiple contacts, which reduces the line length between the contacts on the word lines and bit lines and the target memory cell. In addition, the resistance of the control lines can be adjusted by controlling the resistivity and width of the control lines, so as to adjust the driving capability of the driving structure to the target memory cell and avoid the limitation of the driving capability of the target memory cell by the width of the word lines and bit lines.

[0085] It should be noted that, without conflict, the features disclosed in the memory provided in the above embodiments can be randomly combined to obtain new memory embodiments.

[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0087] The basic concepts have been described above. It is obvious that the detailed disclosure above is merely illustrative and does not constitute a limitation of this disclosure. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this disclosure by those skilled in the art. Such modifications, improvements, and corrections are suggested in this disclosure and therefore remain within the spirit and scope of the exemplary embodiments of this disclosure.

[0088] The foregoing has provided a detailed description of a memory provided by the embodiments of this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A memory, characterized in that, include: The storage cell array includes a first edge region, a connecting region, and a second edge region arranged along a first direction, wherein the connecting region is located between the first edge region and the second edge region; A plurality of drive lines extending along the first direction, each drive line being coupled to a column of memory cells arranged along the first direction, and including a first end region, a middle region and a second end region, wherein the first end region corresponds to the first edge region, the middle region corresponds to the connection region and the second end region corresponds to the second edge region; A plurality of control lines extending along the first direction and corresponding to the drive lines, wherein the control lines are electrically connected to the middle region corresponding to the drive lines and to at least one of the first end region and the second end region, and the resistivity of the control lines is less than that of the drive lines.

2. The memory as claimed in claim 1, characterized in that, The drive line is made of tungsten, and the control line is made of copper.

3. The memory as claimed in claim 1, characterized in that, Also includes: A drive structure is located in at least one of the connection region, the first edge region, or the second edge region, and the drive structure is electrically connected to the control line.

4. The memory as described in claim 3, characterized in that, The drive structure is symmetrically arranged in the first edge region and the second edge region. One end of the control line is electrically connected to the drive structure in the first end region and the first edge region of the corresponding drive line, and the other end is electrically connected to the drive structure in the second end region and the second edge region of the corresponding drive line. The middle end is connected to the middle region of the corresponding drive line.

5. The memory as described in claim 3, characterized in that, The drive structure is located in the connection area. The control line includes a first sub-control line and a second sub-control line. One end of the first sub-control line and one end of the second sub-control line are respectively connected to the drive structure. The other end of the first sub-control line is connected to the first end area, and the other end of the second sub-control line is connected to the second end area.

6. The memory as claimed in claim 5, characterized in that, The distance from the first sub-control line to the drive line may be the same as or different from the distance from the second sub-control line to the drive line.

7. The memory as claimed in claim 6, characterized in that, Between the drive structure and the first end region or between the drive structure and the second end region, the first sub-control line of any control line is adjacent to the second sub-control line of the adjacent control line, or the first sub-control line of any control line is adjacent to the first sub-control line of the adjacent control line.

8. The memory as claimed in claim 1, characterized in that, The drive lines include word lines and / or bit lines.

9. The memory according to any one of claims 1 to 8, characterized in that, The storage cell array includes multiple stacked storage cell arrays, wherein the connection area of ​​any layer of the storage cell array overlaps with the projection of the first edge area or the second edge area of ​​the adjacent layer of the storage cell array onto the array plane of the storage cell array.

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