Storage device and storage array

Abstract

A storage device includes a first transistor and a second transistor. The gate of the first transistor is coupled to a write word line, and the drain of the first transistor is coupled to a write bit line. The source of the second transistor is coupled to a read source line, and the drain of the second transistor is coupled to a read bit line. The gate of the second transistor is coupled to the source of the first transistor. The storage node is located at the coupling position of the grid electrode of the second transistor and the source electrode of the first transistor. The storage device selectively performs a write operation, a read operation, or a refresh operation according to input voltages received by the write word line, the write bit line, the read source line, and the read bit line, respectively.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a storage device based on a transistor and a capacitor. Background Art

[0002] Reservoir computing (RC) is a neural network-based framework for processing temporal / sequential information. Reservoir devices are used to perform reservoir computing. Reservoir devices are large, sparse, and randomly connected nonlinear layers that are not trained and can transform sequence inputs nonlinearly into high-dimensional space. The current state of the reservoir device of a virtual node in a neural network depends on the previous state of the reservoir device. Moreover, based on the short-term storage characteristics of the reservoir device, the reservoir device can be quickly restored to its original state.

[0003] In order to make a storage device suitable for performing in-memory computing (IMC), a storage device with an improved architecture is needed, which can be easily integrated into a memory device. Summary of the invention

[0004] According to one aspect of the present invention, a storage device is provided, comprising a first transistor and a second transistor. The gate of the first transistor is coupled to a write word line, and the drain of the first transistor is coupled to a write bit line. The source of the second transistor is coupled to a read source line, and the drain of the second transistor is coupled to a read bit line. The gate of the second transistor is coupled to the source of the first transistor. The storage node is located at the coupling point between the gate of the second transistor and the source of the first transistor. According to the input voltages received by the write word line, the write bit line, the read source line and the read bit line respectively, the storage device selectively performs a write operation, a read operation or a refresh operation. When the storage device performs a write operation or a refresh operation, a voltage of the storage node changes to a first potential or a second potential, and the first potential is higher than the second potential. When the storage device performs a read operation, the second transistor generates a read current, and the read current is related to the voltage of the storage node.

[0005] According to another aspect of the present invention, a reservoir array is provided, which has a plurality of transverse columns and a plurality of longitudinal rows. The reservoir array includes a plurality of reservoir elements, which are respectively arranged in the transverse columns and the longitudinal rows. The transverse columns include at least a first transverse column and a second transverse column, and the longitudinal rows include at least a first longitudinal row and a second longitudinal row. The first transistors of the reservoir elements arranged in the first transverse column are commonly coupled to a first write word line, and the second transistors of the reservoir elements are commonly coupled to a first read source line. The first transistors of the reservoir elements arranged in the second transverse column are commonly coupled to a second write word line, and the second transistors of the reservoir elements are commonly coupled to a second read source line. The first transistors of the reservoir elements arranged in the first longitudinal row are commonly coupled to a first write bit line, and the second transistors of the reservoir elements are commonly coupled to a first read bit line. The first transistors of the reservoir elements arranged in the second longitudinal row are commonly coupled to a second write bit line, and the second transistors of the reservoir elements are commonly coupled to a second read bit line. According to an input voltage received by the first write word line, the first write bit line, the first read source line, the first read bit line, the second write word line, the second write bit line, the second read source line and the second read bit line respectively, the storage elements selectively perform a write operation, a read operation or a refresh operation.

[0006] Other aspects and advantages of the invention will become apparent from a review of the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a circuit diagram of a storage device 100 a according to an embodiment of the present invention.

[0008] Figure 2 yes Figure 1 1. A timing relationship diagram of a write operation wrt, a refresh operation refh, and a read operation rd of the storage device 100a.

[0009] Figure 3A , 3B yes Figure 1 Schematic diagram of the modulation method of the input voltage V_WWL received by the storage device 100a.

[0010] Figure 4A is a circuit diagram of a storage device 100b according to another embodiment of the present invention.

[0011] Figure 4B yes Figure 4A Waveform diagram of each input voltage of the storage device 100b.

[0012] Figures 5A to 5Dis a circuit diagram of storage devices 100 - 1 to 100 - 4 according to other embodiments of the present invention.

[0013] Figure 6 is a circuit diagram of a reservoir array 200 according to another embodiment of the present invention.

[0014] Fig. 7A is a circuit diagram of a reservoir array 300 according to another embodiment of the present invention.

[0015] Figures 7B to 7E yes Fig. 7A Schematic diagram of the operation of the reservoir array 300.

[0016] Fig. 8A It is a schematic diagram of the operation of the storage devices 310, 320 and 330 in different longitudinal rows.

[0017] Figure 8B It is a schematic diagram of the operation of the storage devices 301 and 302.

[0018] Fig.9A is a circuit diagram of a reservoir array 300b according to another embodiment of the present invention.

[0019] Fig. 9B yes Fig.9A FIG. 3 is a schematic diagram showing the operation of the reservoir array 300 b according to different capacitance values.

[0020] Fig. 9C is a schematic diagram of the operation of a reservoir array 300c according to another embodiment of the present invention.

[0021] Fig.9D is a circuit diagram of a reservoir array 300d according to another embodiment of the present invention.

[0022] Figures 10A to 10H is a schematic diagram of the operation of a reservoir array 300e according to another embodiment of the present invention.

[0023] Fig.11 FIG. 1 is a circuit diagram of a storage device 100c according to another embodiment of the present invention.

[0024] Description of Reference Numerals

[0025] 100a, 100b, 100c, 100-1 to 100-4: storage device

[0026] 310~370,301,302:Storage device

[0027] 200, 300, 300b~300e: Reservoir array

[0028] 10(1,1)~10(2,2), 10(M,1)~10(M,3): storage element

[0029] 31-33: Storage element

[0030] e1: one end

[0031] e2: the other end

[0032] C1~CN,CM,C_a:Capacitor

[0033] C11~CNM: Capacitor

[0034] Cv1~Cv7,Cv11~CvM3: Capacitance value

[0035] 50,50(1),50(2): Inductive circuit

[0036] 51,60,70,80: decoding circuit

[0037] 51-1, 51-2, 60, 61, 62, 70, 71, 72, 80, 81, 82: decoding circuit

[0038] TwTW_b,TR,T_a:Transistor

[0039] g1,g1_b,g2,g3: gate

[0040] d1, d1_b, d2: drain

[0041] s1, s1_b, s2: source

[0042] WWL,WWL1,WWL2,WWLM: Write word line

[0043] WBL, WBL1~WBL7: write bit line

[0044] RSL,RSL1,RSL2,RSLM: read source line

[0045] RBL, RBL1~RBL7: read bit line

[0046] V_WWL, V_WWL(1), v_WWL(2), V_WWL_b: input voltage

[0047] V_CWL, V_WBL, V_WBL_b: input voltage

[0048] V_RSL,V_RBL: input voltage

[0049] Vw, Vb, Vr, Vwr: voltage value

[0050] R1: Resistor

[0051] SN: Storage Node

[0052] GND: Ground point

[0053] CP: Parasitic capacitance

[0054] V_SN: voltage

[0055] I_TR, I_TR(1), I_TR(2): read current

[0056] wrt: write operation

[0057] refh: refresh operation

[0058] rd: read operation

[0059] t1~t19: time point

[0060] T1, T2: time interval

[0061] V1~V4: voltage value

[0062] V_0, V_1, V_2, V_3: voltage amplitude

[0063] P_0, P_1, P_2, P_3: Pulse width

[0064] task_1,task_2,task_3:tasks DETAILED DESCRIPTION

[0065] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present invention has one or more technical features. Under the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0066] Figure 1 FIG. 1 is a circuit diagram of a reservoir device 100a according to an embodiment of the present invention. Figure 1As shown, the storage device 100a includes a transistor TW and a transistor TR. Each of the transistor TW and the transistor TR is a three-terminal selector, such as a metal oxide semiconductor transistor (MOS), a floating gate flash memory (FG flash), a silicon nitride flash memory (SONOS flash), a ferroelectric field effect transistor (FeFET) or an indium gallium zinc oxide (IGZO) transistor. In the present embodiment, the transistor TW and the transistor TR are both N-type metal oxide semiconductor transistors (NMOS). The transistor TW has a gate g1, a drain d1 and a source s1. The transistor TR has a gate g2, a drain d2 and a source s2. The source s1 of the transistor TW is coupled to the gate g2 of the transistor TR. The gate g1 of the transistor TW is coupled to the write word line WWL, and the drain d1 is coupled to the write bit line WBL. The source s2 of the transistor TR is coupled to the read source line RSL, and the drain d2 is coupled to the read bit line RBL. The write word line WWL is substantially parallel to the read source line RSL, and the write bit line WBL is substantially parallel to the read bit line RBL.

[0067] The coupling point between the source s1 of the transistor TW and the gate g2 of the transistor TR is a storage node SN. There is a parasitic capacitance CP between the storage node SN and the ground point GND, and the storage node SN has a voltage V_SN. The voltage V_SN of the storage node SN represents the state of the storage device 100a. The storage device 100a has short-term memory characteristics. The current state of the storage device 100a is related to the previous state, and the storage device 100a can relax back to the original state. Based on the characteristics of short-term memory, the storage device 100a can be used to perform reservoir computing (RC), which is suitable for temporal / sequential information processing. Figure 1 In the embodiment of FIG. 1 , the storage node SN is not coupled to any physical capacitor, and the storage device 100a maintains the voltage V_SN of the storage node SN through the parasitic capacitor CP. Therefore, Figure 1 The storage device 100a is called a "2T0C" architecture.

[0068] Table 1 shows three operations of the storage device 100a and corresponding input voltages and input logic values. The three operations of the storage device 100a include a write operation, a refresh operation, and a read operation.

[0069] Table 1

[0070] V_WWL V_WBL V_RSL V_RBL Write Operation Vw / 0 Vb 0 0 Read Operation 0 0 0 Vr Refresh Operation V 0 0 0

[0071] Please also see Figure 1 Table 1. The storage device 100a receives an input voltage V_WBL through the write bit line WBL, and receives an input voltage V_WWL through the write word line WWL. When the input voltage V_WWL is equal to the voltage value Vw, it indicates that the storage device 100a receives a logic value "1" through the write word line WWL. The voltage value Vw is greater than the threshold voltage Vt of the transistor TW. When the input voltage V_WWL is equal to the voltage value Vw, the transistor TW is turned ON. When the input voltage V_WWL is equal to 0V, it indicates that the storage device 100a receives a logic value "0" through the write word line WWL, and the transistor TW is turned OFF.

[0072] On the other hand, the storage device 100a receives an input voltage V_RBL through the read bit line RBL, and receives an input voltage V_RSL through the read source line RSL. When the input voltage V_RBL is equal to the voltage value Vr, and the input voltage V_RSL is equal to 0V, it means that the storage device 100a receives a logic value "1" through the read bit line RBL, and receives a logic value "0" through the read source line RSL, and the transistor TR is turned on and generates a read current I_TR. The read current I_TR flows from the drain d2 to the source s2, and flows through the read source line RSL and is provided to the sensing circuit 50. When the input voltage V_RBL and the input voltage V_RSL are both equal to 0V, it means that the storage device 100a receives a logic value "0" through the read bit line RBL and the read source line RSL, and the transistor TR is turned off and does not generate the read current I_TR.

[0073] When the storage device 100a performs a write operation or a refresh operation, the voltage V_SN of the storage node SN changes according to the input voltage V_WWL and the input voltage V_WBL, and the voltage V_SN changes to the first potential or the second potential. More specifically, when the storage device 100a performs a write operation, the input voltage V_RSL and the input voltage V_RBL are both 0V, and the transistor TR is disconnected. Moreover, the input voltage V_WWL is equal to the voltage value Vw or 0V, and the input voltage V_WBL is equal to the voltage value Vb, and the storage node SN may be written with a logic value "1". In this embodiment, when the input voltage V_WWL is equal to the voltage value Vw, and the input voltage V_WBL is equal to the voltage value Vb, the transistor TW is turned on and a current flows from the drain d1 to the source s1, and the parasitic capacitor CP is charged, so that the voltage V_SN of the storage node SN rises to the first potential (the first potential is a high potential), indicating that the storage node SN is written with a logic value "1". On the other hand, when the input voltage V_WWL is equal to 0 V and the input voltage V_WBL is equal to the voltage value Vb, the transistor TW is turned off and the parasitic capacitor CP is not charged.

[0074] When the storage device 100a performs a refresh operation, the input voltage V_RSL and the input voltage V_RBL are both 0V, and the transistor TR is turned off. In addition, the input voltage V_WWL is equal to the voltage value Vw, and the input voltage V_WBL is equal to 0V, the transistor TW is turned on, and a current flows from the source s1 to the drain d1, and the parasitic capacitor CP is discharged, so that the voltage V_SN of the storage node SN is restored to the second potential. (The second potential is a low potential, the second potential is lower than the first potential, and the second potential is, for example, 0V), indicating that the storage node SN is refreshed to a logic value "0".

[0075] On the other hand, when the storage device 100a performs a read operation, the input voltage V_WWL and the input voltage V_WBL are both equal to 0V, and the transistor TW is turned off. In addition, the input voltage V_RSL is 0V, and the input voltage V_RBL is equal to the voltage value Vr, and the transistor TR is turned on. The voltage V_SN of the storage node SN is reflected in the read current I_TR of the transistor TR, and the read current I_TR is provided to the sensing circuit 50 through the read source line RSL.

[0076] In the above embodiment, when the input voltages V_WWL, V_WBL, V_RSL and V_RBL are equal to 0V, the logic value "0" is represented. In another example, the logic value "0" can also be represented as: the input voltages V_WWL, V_WBL, V_RSL and V_RBL are equal to a low voltage value. The low voltage value is less than the voltage values ​​Vw, Vb and Vr and is not equal to 0V.

[0077] Next, see Figure 2 , which shows Figure 1 The timing relationship between the write operation wrt, the refresh operation refh and the read operation rd of the storage device 100a. The storage device 100a performs a refresh operation refh at time point t0, and the voltage V_SN of the storage node SN is refreshed to 0V. Then, the storage device 100a performs three write operations wrt between time point t0 and time point t3, and the gate g1 of the transistor TW receives the input voltage V_WWL. In the three write operations wrt, the input voltage V_WWL is respectively the voltage value Vw, 0V and the voltage value Vw, indicating that the gate g1 of the transistor TW receives the logic value "1", the logic value "0" and the logic value "1". According to the received logic value "1", logic value "0" and logic value "1", the voltage V_SN of the storage node SN rises to the voltage value V1 at time point t1, recovers to 0V at time point t2, and rises to the voltage value V1 again at time point t3.

[0078] After three write operations wrt, the storage device 100a performs a read operation rd at time t3. The voltage V_SN of the storage node SN is equal to the voltage value V1 at time t3, and the voltage V_SN is reflected in the read current I_TR of the transistor TR. The read current I_TR is provided to the sensing circuit 50 through the read source line RSL.

[0079] Then, the storage device 100a performs another three write operations wrt between time point t3 and time point t6, and the input voltage V_WWL received by the gate g1 of the transistor TW is the voltage value Vw, indicating that the gate g1 of the transistor TW receives the logic value "1" in the three write operations wrt between time point t3 and time point t6. According to the received logic value "1", the voltage V_SN of the storage node SN continues to rise between time point t3 and time point t6, and rises to the voltage value V4 at time point t6. After the three write operations wrt between time point t3 and time point t6, the storage device 100a performs the read operation rd again at time point t6. The voltage V_SN of the storage node SN is equal to the voltage value V4 at time point t6 and is reflected in the read current I_TR of the transistor TR.

[0080] Then, the storage device 100a performs three more write operations wrt between time point t6 and time point t9. The input voltages V_WWL received by the gate g1 of the transistor TW are 0V, voltage value Vw and 0V respectively, indicating that the gate g1 of the transistor TW receives the logic value "0", logic value "1" and logic value "0" respectively. According to the received logic values ​​"0", logic value "1" and logic value "0", the voltage V_SN of the storage node SN drops to the voltage value V2 at time point t7, rises to the voltage value V3 at time point t8, and drops to the voltage value V1 again at time point t9. Then, the storage device 100a performs the read operation rd again at time point t9, and the voltage V_SN of the storage node SN is equal to the voltage value V1 and is reflected in the read current I_TR of the transistor TR.

[0081] The storage device 100a performs 9 write operations wrt and 3 read operations rd between time point t0 and time point t9. The above 9 write operations wrt and 3 read operations rd belong to one operation sequence. Then, the storage device 100a performs another operation sequence between time point t10 and time point t19, which also includes 9 write operations wrt and 3 read operations rd. Between the operation sequence from time point t0 to time point t9 and the operation sequence from time point t10 to time point t19, the storage device 100a can perform a refresh operation refh to refresh the voltage V_SN of the storage node SN to 0V.

[0082] In the operation sequence from time point t10 to time point t19, the storage device 100a performs three write operations wrt between time point t10 and time point t13, the gate g1 of the transistor TW receives the logic value "0", the logic value "1" and the logic value "1" respectively, the voltage V_SN of the storage node SN is maintained at 0V at time point t11, and continues to rise to the voltage value V2 from time point t12 to time point t13. Then, the storage device 100a performs one read operation rd at time point t13. Similarly, next, the storage device 100a performs three write operations wrt between time point t13 and time point t16, the gate g1 of the transistor TW receives the logic value "1", the logic value "0" and the logic value "0" respectively, the voltage V_SN of the storage node SN rises to the voltage value V3 at time point t14, and continues to drop to 0V from time point t14 to time point t16. Then, the storage device 100a performs one read operation rd at time point t16. Next, the storage device 100a performs three write operations wrt between time point t16 and time point t19, and the voltage V_SN of the storage node SN rises to the voltage value V1 at time point t17, drops to 0V at time point t18, and rises to V1 again at time point t19. Then, the storage device 100a performs one read operation rd at time point t19.

[0083] exist Figure 2 In the embodiment of the present invention, the storage device 100a first performs three write operations wrt and then performs one read operation rd. In another example, the storage device 100a may perform one read operation rd after each write operation wrt. Moreover, the refresh operation refh between the operation sequence from time point t0 to time point t9 and the operation sequence from time point t10 to time point t19 is selective. If the voltage V_SN of the storage node SN has been restored to 0V after the operation sequence from time point t0 to time point t9, the refresh operation refh does not need to be performed at time point t10.

[0084] Figure 3A , 3B yes Figure 1 Schematic diagram of the modulation method of the input voltage V_WWL received by the storage device 100a. The input voltage V_WWL can be in analog form, multi-level form or digital form. When the input voltage V_WWL is in analog form, for example, the modulation method of the input voltage V_WWL can be amplitude modulation (amplitude_modulation) or pulse width modulation (pulse_width_modulation).

[0085] like Figure 3AAs shown, when the input voltage V_WWL adopts amplitude modulation, the voltage amplitudes V_0, V_1, V_2 and V_3 of the input voltage V_WWL respectively represent that the analog values ​​of the input voltage V_WWL are “0”, “0.1”, “0.5” and “1.0”.

[0086] On the other hand, Figure 3B As shown, when the input voltage V_WWL adopts pulse width modulation, the pulse widths P_0, P_1, P_2 and P_3 of the input voltage V_WWL respectively represent that the analog values ​​of the input voltage V_WWL are "0", "0, 1", "0.5" and "1.0".

[0087] Figure 4A is a circuit diagram of a storage device 100b according to another embodiment of the present invention. Figure 4A The storage device 100b is similar to Figure 1 The storage device 100a is different in that: Figure 4A The transistor TW_b of the storage device 100b is a P-type metal oxide semiconductor transistor (PMOS). Therefore, Figure 4A The gate g1_b of transistor TW_b receives the logic value complementary to Figure 1 The gate g1 of the NMOS transistor TW receives the logic value.

[0088] Figure 4B yes Figure 4A Please also refer to the waveform diagram of each input voltage of the storage device 100b. Figure 4A , 4B , the gate g1_b of the transistor TW_b of the storage device 100b receives the input voltage V_WWL_b through the write word line WWL. When the input voltage V_WWL_b is equal to the voltage value Vw, it indicates that the gate g1_b receives the logic value "0". When the input voltage V_WWL_b is equal to 0V (or a low voltage value less than the voltage value Vw), it indicates that the gate g1_b receives the logic value "1". The drain d1_b of the transistor TW_b receives the input voltage V_WBLb through the write bit line WBL. When the input voltage V_WBL_b is equal to the voltage value Vb, it indicates that the drain d1_b receives the logic value "1". Therefore, when Figure 4A When the storage device 100b performs a write operation to write a logic value "1", the input voltage V_WWL_b received by the gate g1_b of the transistor TW_b is 0V (or equal to a low voltage value), and the input voltage V_WBL_b received by the drain d1_b is equal to the voltage value Vb.

[0089] on the other hand, Figure 4A The transistor TR is an NMOS transistor, which is the same as Figure 1When the input voltage V_RBL received by the drain d2 of the transistor TR is equal to the voltage value Vr, it means that the drain d2 receives the logic value "1". When the input voltage V_RSL received by the source s2 of the transistor TR is equal to 0V (or equal to a low voltage value), it means that the source s2 receives the logic value "0".

[0090] Figures 5A to 5D is a circuit diagram of storage devices 100 - 1 to 100 - 4 according to other embodiments of the present invention. Figures 5A to 5D In addition to having parasitic capacitance, the storage node SN of the storage devices 100-1 to 100-4 may also be coupled to at least one physical capacitor to maintain the voltage V_SN of the storage node SN. The physical capacitor is, for example, provided during the manufacturing process of the storage devices 100-1 to 100-4. Figures 5A to 5D The storage devices 100 - 1 to 100 - 4 are referred to as a “2TXC” architecture, where “X” represents the number of physical capacitors.

[0091] Please see first Figure 5A , the storage node SN of the storage device 100 - 1 is coupled to a physical capacitor C1 , which is called a “2T1C” architecture. One end e1 of the capacitor C1 is coupled to the storage node SN, and the other end e2 of the capacitor C1 is coupled to the ground point GND.

[0092] Next, see Figure 5B , the storage node SN of the storage device 100 - 2 is coupled to N physical capacitors C1 ˜CN, which is called a “2TNC” architecture. The capacitors C1 ˜CN are coupled to each other in parallel, for example.

[0093] Next, see Figure 5C The storage node SN of the storage device 100 - 3 is coupled to M physical capacitors C1 ˜CM. The capacitors C1 ˜CM are coupled to each other in series, for example.

[0094] Next, see Figure 5D , the storage node SN of the storage device 100-4 is coupled to NxM physical capacitors C11-CNM. The capacitors C11-C1M arranged in the first vertical row are coupled to each other in series, and so on, the capacitors CN1-CNM arranged in the Nth vertical row are coupled to each other in series. The capacitors between different vertical rows are coupled in parallel.

[0095] Figure 6 is a circuit diagram of a reservoir array 200 according to another embodiment of the present invention. Figure 6The reservoir array 200 includes a plurality of reservoir elements 10(1,1), 10(1,2), 10(2,1) and 10(2,2). Each of the reservoir elements 10(1,1) to 10(2,2) can be used Figure 1 The storage device 100a, Figure 4A The storage device 100b, or Figures 5A to 5D This is achieved by the storage devices 100-1 to 100-4.

[0096] The reservoir array 200 has a plurality of longitudinal rows and a plurality of transverse columns, for example, a first longitudinal row, a second longitudinal row, a first transverse column, and a second transverse column. The reservoir elements 10(1,1), 10(1,2), 10(2,1), and 10(2,2) are arranged in an array. The reservoir elements 10(1,1) and 10(1,2) are arranged in the first transverse column, and the transistors TW of the reservoir elements 10(1,1) and 10(1,2) are commonly coupled to the write word line WWL1 to receive the input voltage V_WWL(1). In addition, the transistors TR of the reservoir elements 10(1,1) and 10(1,2) are commonly coupled to the read source line RSL1 to transmit the read current I_TR(1) to the sensing circuit 50(1) through the read source line RSL1.

[0097] Similarly, the storage elements 10(2, 1) and 10(2, 2) are arranged in the second horizontal row, and the transistors TW of the storage elements 10(2, 1) and 10(2, 2) are commonly coupled to the write word line WWL2 to receive the input voltage V_WWL(2). In addition, the transistors TR of the storage elements 10(2, 1) and 10(2, 2) are commonly coupled to the read source line RSL2 to transmit the read current I_TR(2) to the sensing circuit 50(2) through the read source line RSL2. The sensing circuits 50(1) and 50(2) are, for example, sensing amplifiers (SA).

[0098] On the other hand, the storage elements 10(1,1) and 10(2,1) are arranged in a first vertical row, the transistors TW of the storage elements 10(1,1) and 10(2,1) are commonly coupled to the write bit line WBL1, and the transistors TR are commonly coupled to the read bit line RBL1. Similarly, the storage elements 10(1,2) and 10(2,2) are arranged in a second vertical row, the transistors TW of the storage elements 10(1,2) and 10(2,2) are commonly coupled to the write bit line WBL2, and the transistors TR are commonly coupled to the read bit line RBL2.

[0099] Fig. 7A is a circuit diagram of a reservoir array 300 according to another embodiment of the present invention. Fig. 7A , the reservoir array 300 is similar to Figure 6The reservoir array 200 includes a plurality of reservoir elements 10 (1, 1) to 10 (M, 3) arranged in an array. Each of the reservoir elements 10 (1, 1) to 10 (M, 3) can be Figure 1 The storage device 100a, Figure 4A The storage device 100b, or Figures 5A to 5D This is achieved by the storage devices 100-1 to 100-4.

[0100] The reservoir array 300 has first, second and third vertical rows and first, second, ..., Mth horizontal columns. The transistors TW of the reservoir elements 10 (1, 1) to 10 (1, 3) of the first horizontal column are commonly coupled to the write word line WWL1. The write word line WWL1 is coupled to the decoding circuit 60, which is, for example, a write word line decoder. In addition, the transistors TR of the reservoir elements 10 (1, 1) to 10 (1, 3) are commonly coupled to the read source line RSL1. The read source line RSL1 is coupled to the decoding circuit 51, which includes, for example, a read source line decoder and a sense amplifier.

[0101] Similarly, the transistors TW of the storage elements 10 (2, 1) to 10 (2, 3) of the second horizontal column are commonly coupled to the write word line WWL2. The write word line WWL2 is coupled to the decoding circuit 60. Furthermore, the transistors TR of the storage elements 10 (2, 1) to 10 (2, 3) are commonly coupled to the read source line RSL2. The read source line RSL2 is coupled to the decoding circuit 51. The transistors TW of the storage elements 10 (M, 1) to 10 (M, 3) of the Mth horizontal column are coupled to the decoding circuit 60 through the write word line WWLM. Furthermore, the transistors TR of the storage elements 10 (M, 1) to 10 (M, 3) are coupled to the decoding circuit 51 through the read source line RSLM.

[0102] The transistors TW of the storage elements 10(1,1)-10(M,1) of the first vertical row are coupled to a decoding circuit 70 through a write bit line WBL1, and the decoding circuit 70 is, for example, a write bit line decoder. Furthermore, the transistors TR of the storage elements 10(1,1)-10(M,1) are coupled to a decoding circuit 80 through a read bit line RBL1, and the decoding circuit 80 is, for example, a read bit line decoder.

[0103] Similarly, the transistors TW of the storage elements 10(1,2) to 10(M,2) in the second vertical row are coupled to the decoding circuit 70 via the write bit line WBL2. Furthermore, the transistors TR of the storage elements 10(1,2) to 10(M,2) are coupled to the decoding circuit 80 via the read bit line RBL2. The transistors TW of the storage elements 10(1,3) to 10(M,3) in the third vertical row are coupled to the decoding circuit 70 via the write bit line WBL3. Furthermore, the transistors TR of the storage elements 10(1,3) to 10(M,3) are coupled to the decoding circuit 80 via the read bit line RBL3.

[0104] In one example, the entire array of reservoir elements 10 (1, 1) to 10 (M, 3) may be collectively regarded as a reservoir array 300. In another example, each of the reservoir elements 10 (1, 1) to 10 (M, 3) may independently serve as a reservoir device.

[0105] In another example, the reservoir elements 10(1,1)-10(M,1) of the first longitudinal row may form a reservoir device 310. Similarly, the reservoir elements 10(1,2)-10(M,2) of the second longitudinal row may form another reservoir device 320, and the reservoir elements 10(1,3)-10(M,3) of the third longitudinal row may form another reservoir device 330. That is, the reservoir elements of each longitudinal row form an independent reservoir device.

[0106] Figures 7B to 7E yes Fig. 7A Schematic diagram of the operation of the reservoir array 300. Figure 7B , only one longitudinal row of storage elements is operated at the same time. For example, in the time interval T1, only the storage device 310 formed by the storage elements 10 (1, 1) to 10 (M, 1) in the first longitudinal row is operated.

[0107] See next Figure 7C At the same time, multiple longitudinal rows of storage elements can also be operated. For example, in the time interval T1, the storage device 310 of the first longitudinal row and the storage device 330 of the third longitudinal row can be operated.

[0108] See next Fig.7D , only part of the storage elements in one longitudinal row are operated at the same time. For example, only two storage elements 10 (2, 2) and 10 (M, 2) in the storage device 320 of the second longitudinal row are operated in the time interval T1.

[0109] See next Fig. 7EAt the same time, some of the storage elements in multiple longitudinal rows can also be operated. For example, in the time interval T1, two storage elements 10 (1, 1) and 10 (M, 1) in the storage device 310 of the first longitudinal row can be operated, and two storage elements 10 (1, 2) and 10 (M, 2) in the storage device 320 of the second longitudinal row can be operated.

[0110] Fig. 8A is a schematic diagram of the operation of different longitudinal rows of storage devices 310, 320 and 330. Fig. 8A In the reservoir array 300, the reservoir devices 310, 320 and 330 in different vertical rows receive the same input voltage through the write word lines WWL1-WWLM. For example, the input voltage received by the reservoir device 310 in the first vertical row through the write word lines WWL1-WWLM is equal to the input voltage received by the reservoir device 320 in the second vertical row through the write word lines WWL1-WWLM.

[0111] Furthermore, the storage devices 310, 320, and 330 have different capacitance values. For example, the capacitor of each of the storage elements 10(1, 1) to 10(M, 1) in the storage device 310 of the first longitudinal row has a capacitance value Cv1. Furthermore, the capacitor of each of the storage elements 10(1, 2) to 10(M, 2) in the storage device 320 of the second longitudinal row has a capacitance value Cv2. The capacitance value Cv1 of the capacitors of the first longitudinal row is not equal to the capacitance value Cv2 of the capacitors of the first longitudinal row. On the other hand, the capacitance value Cv3 (not shown) of the capacitors of the third longitudinal row is also different from the capacitance values ​​Cv1 and Cv2.

[0112] exist Fig. 8A In the embodiment, the operations of the storage devices 310 to 330 of different longitudinal rows are sequentially performed at different times. For example, the storage device 310 of the first longitudinal row is performed in the time interval T1, and the storage device 320 of the second longitudinal row is performed in the next time interval T2. On the other hand, the storage device 330 of the second longitudinal row can be performed in the next time interval (not shown in the figure).

[0113] Figure 8B is a schematic diagram of the operation of the storage devices 301 and 302. Fig. 8A The storage array 300 is divided into three independent storage devices according to different longitudinal rows. Figure 8B Two independent storage devices 301 and 302 are shown as an example. In terms of operation function, the storage device 301 corresponds to Fig. 8A The first longitudinal row of storage devices 310, storage devices 302 are corresponding to Fig. 8A A first longitudinal row of storage devices 320.

[0114] The storage devices 301 and 302 operate in sequence with their respective decoding circuits. For example, the write word lines WWL1-WWLM of the storage device 301 are coupled to the decoding circuit 61, the write bit line WBL1 is coupled to the decoding circuit 71, the read source lines RSL1-RSLM are coupled to the decoding circuit 51-1, and the read bit line RBL1 is coupled to the decoding circuit 81. In addition, the capacitor of each of the storage elements 10(1,1)-10(M,1) in the storage device 301 has a capacitance value Cv1.

[0115] On the other hand, the write word lines WWL1 to WWLM of the storage device 302 are coupled to the decoding circuit 62, the write bit line WBL2 is coupled to the decoding circuit 72, the read source lines RSL1 to RSLM are coupled to the decoding circuit 51-2, and the read bit line RBL2 is coupled to the decoding circuit 82. Furthermore, the capacitor of each of the storage elements 10(1, 2) to 10(M, 2) in the storage device 302 has a capacitance value Cv2. The capacitance value Cv2 is not equal to the capacitance value Cv1.

[0116] In operation, the storage devices 301 and 302 receive the same input voltage through the write word lines WWL1 ˜WWLM. The storage device 301 may be executed in a time interval T1 , and the storage device 302 may be executed in a next time interval T2 . Figure 8B The execution result of the embodiment of is substantially equivalent to: Fig. 8A In the embodiment of the present invention, the storage device 310 of the first longitudinal row is executed in the time interval T1, and the storage device 320 of the second longitudinal row is executed in the next time interval T2. Figure 8B In another embodiment, the storage devices 301 and 302 may be executed simultaneously during the time interval T1.

[0117] Fig.9A 3 is a circuit diagram of a reservoir array 300b according to another embodiment of the present invention. Fig. 7A Another form of the reservoir array 300. Fig.9A The capacitors of the reservoir elements 10 ( 1 , 1 ) to 10 ( M, 3 ) of the reservoir array 300 b have corresponding capacitance values ​​Cv11 to CvM3 . According to different examples, these capacitance values ​​Cv11 to CvM3 may be equal or different.

[0118] In one example, the capacitance values ​​of the storage elements in the same vertical row are equal, but the capacitance values ​​of the storage elements in different vertical rows are different. For example, the capacitance values ​​Cv11, Cv21, ..., CvM1 of the capacitors in the storage device 310 of the first vertical row are all equal to the capacitance value Cv1, the capacitance values ​​Cv12, Cv22, ..., CvM2 of the capacitors in the storage device 320 of the second vertical row are all equal to the capacitance value Cv2, and the capacitance values ​​Cv13, Cv23, ..., CvM3 of the capacitors in the storage device 330 of the third vertical row are all equal to the capacitance value Cv3. Moreover, the capacitance values ​​Cv1, Cv2 and Cv3 are different from each other. The relationship between the above-mentioned capacitance values ​​is shown in Formula (1-1) to Formula (1-4):

[0119] C11=C21=…=CM1=C1 (1-1)

[0120] C12=C22=…=CM2=C2 (1-2)

[0121] C13=C23=…=CM3=C3 (1-3)

[0122] C1≠C2≠C3 (1-4)

[0123] In another example, the capacitance values ​​Cv11, Cv21, ..., CvM1 of the capacitors in the storage device 310 of the first longitudinal row are different from each other. The capacitance values ​​Cv12, Cv22, ..., CvM2 of the capacitors in the storage device 320 of the second longitudinal row can be partially the same and partially different. The capacitance values ​​Cv13, Cv23, ..., CvM3 of the capacitors in the storage device 330 of the third longitudinal row are the same. The relationship between the above-mentioned capacitance values ​​is shown in formula (2-1) to formula (2-3):

[0124] C11≠C21≠…≠CM1 (2-1)

[0125] C12=C22≠…≠CM2 (2-2)

[0126] C13=C23=…=CM3 (2-3)

[0127] The capacitance values ​​Cv11 to CvM3 of the capacitors of the storage elements 10 (1, 1) to 10 (M, 3) can be adjusted in the following manner. For example, when the capacitors of the storage elements 10 (1, 1) to 10 (M, 3) are parasitic capacitors, the capacitance values ​​Cv11 to CvM3 can be adjusted by changing the doping concentration Nd (doping concentration) of the PN junction of the transistor TW (at this time, the capacitance values ​​Cv11 to CvM3 are equivalent capacitance values ​​of the parasitic capacitors). Taking the capacitance value Cv11 of the capacitor of the storage element 10 (1, 1) as an example, the relationship between the capacitance value Cv11 and the doping concentration Nd of the PN junction is shown in formula (3-1). Among them, the capacitance value Cv11 is proportional to the 1 / 2 power of the doping concentration Nd. When the doping concentration Nd is reduced, a lower capacitance value Cv11 can be obtained.

[0128]

[0129] In another example, when the capacitor of the storage element 10 (1, 1) to 10 (M, 3) is a parasitic capacitor, the capacitance values ​​Cv11 to CvM3 can also be adjusted by changing the size of the transistor TR. Taking the capacitance value Cv11 of the capacitor of the storage element 10 (1, 1) as an example, the relationship between the capacitance value Cv11 and the length L and width W of the transistor TR, the equivalent capacitance value Cox of the oxide layer of the transistor TR, and the overlapping equivalent capacitance value Cov of the transistor TR operating in the saturation range is shown in formula (3-2). Among them, the capacitance value Cv11 is proportional to the length L and width W of the transistor TR. When the length L and / or the width W are reduced, a lower capacitance value Cv11 can be obtained.

[0130]

[0131] On the other hand, when the capacitor of the storage element 10(1,1) to 10(M,3) is a physical capacitor, the capacitor can be implemented as a ferroelectric capacitor, an electrochemical tunable capacitor or an oxynitride oxide insulated capacitor. The capacitance value can be adjusted by changing the element parameters of the above-mentioned capacitors.

[0132] The critical voltage Vt of the transistor TR of each storage element 10(1,1)~10(M,3) of the storage array 300b can be the same or different. For example, the critical voltage Vt of the transistors TR in the same vertical row is the same, and the critical voltage Vt of the transistors TR in different vertical rows is different. The critical voltage Vt of the transistor TR can be adjusted according to the following methods. For example, the critical voltage Vt is adjusted by changing the thickness of the gate oxide layer (gate oxide) of the transistor TR. For another example, the transistor TR is a SONOS flash memory or has a floating gate, and the critical voltage Vt of the transistor TR can be adjusted by applying a gate voltage.

[0133] Fig. 9B yes Fig.9A Schematic diagram of the reservoir array 300b operating according to different capacitance values. Fig. 9B As shown, in the storage device 310 of the first vertical row, the capacitance value of the capacitor of each storage element is equal to the capacitance value Cv1. In the storage device 320 of the second vertical row, the capacitance value of the capacitor of each storage element is equal to the capacitance value Cv2. In the storage device 330 of the third vertical row, the capacitance value of the capacitor of each storage element is equal to the capacitance value Cv3. In this embodiment, the capacitors in each vertical row are, for example, physical capacitors, and the number of physical capacitors in each vertical row can be the same. The capacitance value can be adjusted by changing the element parameters of the physical capacitor during the manufacturing process of the storage array 300b, so that the capacitance values ​​Cv1, Cv2 and Cv3 of the storage devices 310, 320 and 330 in different vertical rows are different from each other.

[0134] The storage devices in different vertical rows can perform different tasks according to different capacitance values ​​Cv1, Cv2 and Cv3. For example, the storage device 310 in the first vertical row performs task task_1 according to the capacitance value Cv1, and task task_1 is, for example, a storage operation for speech recognition. Also, the storage device 320 in the second vertical row performs task task_2 according to the capacitance value Cv2, and task task_2 is, for example, a storage operation for image recognition. Furthermore, the storage device 330 in the third vertical row performs task task_3 according to the capacitance value Cv3, and task task_3 is, for example, a storage operation for stereoscopic image processing.

[0135] Fig. 9C Schematic diagram of the operation of a reservoir array 300c according to another embodiment of the present invention. Fig. 9BA variation of the storage array 300b. The capacitance values ​​of the storage devices 310-370 of the first to seventh longitudinal rows of the storage array 300c are respectively equal to the capacitance values ​​Cv1-Cv7. The above-mentioned capacitance values ​​Cv1-Cv7 can be different from each other. In this embodiment, the storage devices 310, 330 and 340 of the first, third and fourth longitudinal rows perform task task_1 according to the capacitance values ​​Cv1, Cv3 and Cv4. The storage devices 320 and 350 of the second and fifth longitudinal rows perform task task_2 according to the capacitance values ​​Cv2 and Cv5. The storage devices 360 and 370 of the sixth and seventh longitudinal rows perform task task_3 according to the capacitance values ​​Cv6 and Cv7.

[0136] Fig.9D is a circuit diagram of a reservoir array 300d according to another embodiment of the present invention. Fig. 9B Another variation of the reservoir array 300b. Fig.9D In the storage devices 310, 320 and 330, the capacitor elements of the storage elements 31, 32 and 33 have the same layout. The layout of the capacitor elements is, for example, Figure 5D The N×M capacitors C11-CNM are shown. The capacitors C11-C1M in the same vertical row are coupled in series, and similarly, the capacitors CN1-CNM in the same vertical row are coupled in series.

[0137] Compared to Fig. 9B The reservoir array 300b adjusts the capacitance value by changing the element parameters of the capacitor, so that the capacitance values ​​Cv1, Cv2 and Cv3 of the capacitors of the reservoir elements in different vertical rows are different from each other; Fig.9D The storage array 300d obtains different capacitance values ​​by selectively short-circuiting or opening the capacitors C11-CNM of the capacitor element layout, so that the capacitance values ​​Cv1, Cv2 and Cv3 of the capacitor elements of different vertical rows of storage elements 31, 32 and 33 are different from each other.

[0138] For example, among the storage elements 31 of the storage device 310 of the first longitudinal row, one of the capacitors C11 of the layout of the capacitor elements is disconnected to change the equivalent resistance value of the capacitors C11 to C1M in series, thereby changing the capacitance value Cv1 of the capacitor element of the storage element 31. Furthermore, among the storage elements 32 of the storage device 320 of the second longitudinal row, the capacitor CN1 of the layout of the capacitor elements is disconnected to change the capacitance value Cv2 of the capacitor element of the storage element 32. Similarly, among the storage elements 33 of the storage device 330 of the third longitudinal row, the capacitor C1M of the layout of the capacitor elements is disconnected to change the capacitance value Cv3 of the capacitor element of the storage element 33. Accordingly, the capacitance values ​​Cv1, Cv2 and Cv3 of the capacitor elements of the storage elements 31, 32 and 33 of different longitudinal rows are different from each other.

[0139] Figures 10A to 10H 300e is a schematic diagram of the operation of the reservoir array 300e of another embodiment of the present invention. The write operation, read operation and refresh operation of the reservoir array 300e can be performed independently for the selected portion of the reservoir elements, the selected portion of the vertical rows or the selected portion of the horizontal columns, or for all the reservoir elements as a whole. Fig. 10A , the write operation of the reservoir array 300e can be performed on part of the reservoir elements. For example, the reservoir array 300e selects the first longitudinal row and the first transverse column, and the reservoir elements 10 (1, 1) disposed at the positions of the first longitudinal row and the first transverse column are selected to perform the write operation. Among the reservoir elements in the first longitudinal row, the selected reservoir elements 10 (1, 1) in the first transverse column perform the write operation independently of the reservoir elements in the second transverse column.

[0140] The input voltages of the write bit lines WBLi and the read bit lines RBLi in each vertical row of the reservoir array 300e, and the input voltages of the write word lines WWLi and the read source lines RSLi in each horizontal column are shown in Table 2-1.

[0141] Table 2-1

[0142]

[0143]

[0144] Please refer to Table 2-1, the input voltage V_WBL of the selected write bit line WBL1 of the first vertical row is equal to the voltage value Vb, and the input voltage V_WWL of the selected write word line WWL1 of the first horizontal column is equal to the voltage value Vw or 0V. In addition, the input voltage V_RBL of the read bit line RBL1 of the first vertical row is equal to 0V, and the input voltage V_RSL of the read source line RSL1 of the first horizontal column is equal to 0V.

[0145] On the other hand, the input voltage V_WBL of the write bit line WBL2 of the unselected second vertical row is equal to 0V, or the write bit line WBL2 is floating (the input voltage V_WBL is represented by "X"), and the input voltage V_RBL of the read bit line RBL2 of the second vertical row is equal to 0V. In addition, the input voltage V_WWL of the write word line WWL2 of the unselected second horizontal column is equal to 0V, and the input voltage V_RSL of the read source line RSL2 of the second horizontal column is equal to 0V.

[0146] Next, see Fig. 10B , the write operation of the reservoir array 300e can be performed on part of the longitudinal rows. For example, the reservoir array 300e selects the first longitudinal row and the first and second transverse columns, and all the reservoir elements arranged in the first longitudinal row are selected to perform the write operation. The reservoir elements in the first longitudinal row perform the write operation independently of the reservoir elements in the second longitudinal row.

[0147] The input voltages of the write bit lines WBLi and the read bit lines RBLi in each vertical row of the reservoir array 300e, and the input voltages of the write word lines WWLi and the read source lines RSLi in each horizontal column are shown in Table 2-2.

[0148] Table 2-2

[0149]

[0150] Please refer to Table 2-2, the input voltage V_WBL of the selected write bit line WBL1 of the first vertical row is equal to the voltage value Vb, and the input voltages V_WWL of the selected write word lines WWL1 and WWL2 of the first and second horizontal columns are equal to the voltage value Vw or 0V. In addition, the input voltage V_RBL of the read bit line RBL1 of the first vertical row is equal to 0V, and the input voltages V_RSL of the read source lines RSL1 and RSL2 of the first and second horizontal columns are equal to 0V.

[0151] On the other hand, the input voltage V_WBL of the unselected write bit line WBL2 of the second vertical row is equal to 0V, or the write bit line WBL2 is floating (the input voltage V_WBL is represented by "X"), and the input voltage V_RBL of the read bit line RBL2 of the second vertical row is equal to 0V.

[0152] Next, see Fig. 10C As shown in Table 3-1, the read operation of the reservoir array 300e can be performed on a portion of the reservoir elements. For example, the reservoir array 300e selects the first longitudinal row and the first transverse column, and accordingly selects the reservoir element 10(1,1) to perform the read operation. Among the reservoir elements in the first longitudinal row, the reservoir element 10(1,1) selected in the first transverse column performs the read operation independently of the reservoir elements in the second transverse column.

[0153] Table 3-1

[0154]

[0155] The input voltage V_WBL of the selected first vertical row write bit line WBL1 is 0V, and the input voltage V_RBL of the selected first horizontal column write word line WWL1 is 0V, and the input voltage V_RSL of the selected first horizontal column read source line RSL1 is 0V.

[0156] On the other hand, the input voltage V_WBL of the unselected write bit line WBL2 of the second vertical row is equal to 0V, or the write bit line WBL2 is floating (the input voltage V_WBL is represented by “X”), and the input voltage V_RBL of the read bit line RBL2 is equal to 0V.

[0157] The second horizontal column is not selected, the input voltage V_WWL of the write word line WWL2 of the second horizontal column is equal to 0V, and the input voltage V_RSL of the read source line RSL2 is equal to 0V.

[0158] Next, see Fig. 10D The reservoir array 300e selects the first longitudinal row and the first and second transverse columns, and all the reservoir elements arranged in the first longitudinal row are selected to perform the read operation. The reservoir elements in the first longitudinal row perform the read operation independently of the reservoir elements in the second longitudinal row.

[0159] The input voltages of each write bit line WBLi and each read bit line RBLi, and the input voltages of each write word line WWLi and each read source line RSLi are also as shown in Table 3-1. The second horizontal column is selected, and the input voltage V_WWL of the write word line WWL2 of the second horizontal column is equal to 0V, and the input voltage V_RSL of the read source line RSL2 is equal to 0V.

[0160] Next, see Fig.10E As shown in Table 4-1, the refresh operation of the reservoir array 300e can be performed on a portion of the reservoir elements. For example, the reservoir array 300e selects the first longitudinal row and the first transverse column, and accordingly selects the reservoir element 10(1, 1) to perform the refresh operation. Among the reservoir elements in the first longitudinal row, the reservoir element 10(1, 1) selected in the first transverse column performs the refresh operation independently of the reservoir elements in the second transverse column.

[0161] Table 4-1

[0162]

[0163] The input voltage V_WWL of the selected write word line WWL1 of the first horizontal column is equal to the voltage value Vwr, so that the transistor TW of the storage element 10 (1, 1) is turned on. The voltage value Vwr may be the same as or different from the voltage value Vw of the write operation. The input voltage V_WBL of the selected write bit line WBL1 of the first vertical row is equal to 0V, so that the capacitance of the storage element 10 (1, 1) is discharged through the turned-on transistor TW, so that the voltage V_SN of the storage node SN is restored to the second potential, and the storage node SN is refreshed to the logic value "0".

[0164] On the other hand, the input voltage V_RBL of the read bit line RBL1 of the first vertical row is equal to 0V, and the input voltage V_RSL of the read source line RSL1 of the first horizontal column is equal to 0V. The input voltage V_WBL of the write bit line WBL2 of the unselected second vertical row is equal to 0V or the write bit line WBL2 is floating, and the input voltage V_RBL of the read bit line RBL2 is equal to 0V. Furthermore, the input voltage V_WWL of the write word line WWL2 of the unselected second horizontal column is equal to 0V, and the input voltage V_RSL of the read source line RSL2 is equal to 0V.

[0165] Next, see Fig.10F As shown in Table 4-2, the refresh operation of the reservoir array 300e may be performed on all reservoir elements in each vertical row and horizontal column.

[0166] Table 4-2

[0167]

[0168]

[0169] The input voltage V_WWL of the write word lines WWL1 and WWL2 of the first and second horizontal columns is equal to the voltage value Vwr (the voltage value Vwr may be the same as or different from the voltage value Vw of the write operation), so that the transistors TW of all the storage elements of the storage device 310 of the first vertical row and the storage device 320 of the second vertical row are turned on. In addition, the input voltage V_WBL of the write bit lines WBL1 and WBL2 of the first and second vertical rows is equal to 0V, so that the capacitance of all the storage elements of the storage device 310 and the storage device 320 is discharged through the turned-on transistors TW, so that the storage nodes SN of all the storage elements are refreshed to the logic value "0".

[0170] Furthermore, the input voltage V_RBL of the read bit lines RBL1 and RBL2 of the first and second vertical rows is equal to 0V. The input voltage V_RSL of the read source lines RSL1 and RSL2 of the first and second horizontal columns is equal to 0V.

[0171] Next, see Figure 10GAs shown in Table 5-1, the refresh operation of the reservoir array 300e can be performed on a portion of the horizontal rows. For example, the reservoir array 300e selects the reservoir elements 10(1, 1) and 10(1, 2) in the first horizontal row to perform the refresh operation.

[0172] Table 5-1

[0173]

[0174] The input voltage V_WWL of the selected write word line WWL1 of the first horizontal column is equal to the voltage value Vwr (the voltage value Vwr may be the same as or different from the voltage value Vw of the write operation), so that the transistors TW of the storage elements 10 (1, 1) and 10 (1, 2) of the first horizontal column are turned on. In addition, the input voltage V_WBL of the write bit lines WBL1 and WBL2 of the first and second vertical rows is equal to 0V, so that the capacitors of the storage elements 10 (1, 1) and 10 (1, 2) are discharged through the turned-on transistors TW to refresh the storage node SN to the logic value "0".

[0175] On the other hand, the input voltage V_RSL of the selected read source line RSL1 of the first horizontal column is equal to 0V, and the input voltage V_RBL of the read bit line RBL1 is equal to 0V. In contrast, the input voltages of the unselected read source line RSL2 and the write word line WWL2 of the second horizontal column are both equal to 0V.

[0176] Next, see Fig. 10H As shown in Table 5-2, the refresh operation of the reservoir array 300e can be performed on a portion of the vertical rows. For example, the reservoir array 300e selects the reservoir devices 310 of the first vertical row to perform the refresh operation. The reservoir elements of the first vertical row perform the refresh operation independently of the reservoir elements of the second vertical row.

[0177] Table 5-2

[0178]

[0179] The reservoir array 300e selects the first vertical row and the first and second horizontal columns. The input voltage V_WWL of the write word lines WWL1 and WWL2 of the first and second horizontal columns is equal to the voltage value Vwr (the voltage value Vwr may be the same as or different from the voltage value Vw of the write operation), and the input voltage V_WBL of the write bit line WBL1 of the first vertical row is equal to 0V, so that the capacitors of all the reservoir elements of the reservoir device 310 are discharged through the turned-on transistor TW to refresh the storage node SN to the logic value "0". The input voltage V_RSL of the read source lines RSL1 and RSL2 of the first and second horizontal columns is equal to 0V. The input voltage V_RBL of the read bit lines RBL1 and RBL2 of the first and second vertical rows is equal to 0V.

[0180] On the other hand, the input voltage V_WBL of the write bit line WBL2 of the unselected storage device 320 in the second vertical column is equal to 0V, or the write bit line WBL2 is floating.

[0181] Fig.11 FIG. 1 is a circuit diagram of a storage device 100c according to another embodiment of the present invention. The storage device 100c of this embodiment is similar to Figure 1 The storage device 100a is different from the storage device 100c in that the storage device 100c further includes a resistor R1 and a transistor T_a.

[0182] The resistor R1 is disposed between the drain d1 of the transistor TW and the write bit line WBL. The resistor R1 is used to adjust the charging rate of the capacitor C_a. When the resistor R1 has a high resistance value, the capacitor C_a can have a low charging rate. That is, the resistor R1 is used to adjust the charging rate of the storage node SN. When the resistor R1 has a high resistance value, the voltage value V_SN of the storage node SN rises at a low rate.

[0183] The transistor T_a is disposed between the source s1 of the transistor TW and the ground point GND2. The gate g3 of the transistor T_a receives the input voltage V_CWL. The transistor T_a is used to adjust the discharge rate of the storage node SN. When the input voltage V_CWL has a high voltage value, the storage node SN has a high discharge rate, and the voltage value V_SN of the storage node SN decreases at a higher rate.

[0184] In summary, the reservoir devices based on 2TOC or 2TXC architectures according to different embodiments of the present invention can be applied to in-memory computing (IMC) or spiking neural networks that require gradual programming and gradual leaking. The reservoir devices of the present invention can also be used as an integrate-and-fire circuit and are suitable for spiking neuromorphic applications. Furthermore, the reservoir devices based on 2TOC or 2TXC architectures can be easily integrated into memory devices, and are therefore suitable for performing in-memory computing.

[0185] Although the present invention has been disclosed in detail as above with preferred embodiments and examples, it is to be understood that these examples are intended to be illustrative rather than restrictive. It is contemplated that a variety of modifications and combinations may be conceived by those skilled in the art, and the variety of modifications and combinations thereof fall within the scope of the spirit of the present invention and the appended claims.

Claims

1. A storage device, characterized in that: include: a first transistor, wherein a gate of the first transistor is coupled to a write word line, and a drain of the first transistor is coupled to a write bit line; a second transistor, wherein a source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to the source of the first transistor; as well as a storage node located at the coupling point between the gate of the second transistor and the source of the first transistor, wherein the storage device selectively performs a write operation, a read operation or a refresh operation according to an input voltage received by each of the write word line, the write bit line, the read source line and the read bit line; as well as When the storage device performs the write operation or the refresh operation, the voltage of the storage node changes. When the storage device performs the read operation, the second transistor generates a read current, and the read current is related to the voltage of the storage node. 2 . The storage device according to claim 1 , wherein the read source line is coupled to a sensing circuit, and the read current is provided to the sensing circuit through the read source line.

3. The storage device according to claim 1, wherein when the storage device performs the write operation: The input voltage received by the write word line is equal to a first voltage value or 0V; The input voltage received by the write bit line is equal to a second voltage value; The input voltage received by the read source line is equal to 0V; as well as The input voltage received by the read bit line is equal to 0V.

4. The storage device according to claim 1, wherein when the storage device performs the refresh operation: The input voltage received by the write word line is equal to a first voltage value; The input voltage received by the write bit line is equal to 0V; The input voltage received by the read source line is equal to 0V; and The input voltage received by the read bit line is equal to 0V.

5. The storage device according to claim 1, wherein when the storage device performs the read operation: The input voltage received by the write word line is equal to 0V; The input voltage received by the write bit line is equal to 0V; The input voltage received by the read source line is equal to 0V; and The input voltage received by the read bit line is equal to a third voltage value. 6 . The storage device according to claim 1 , wherein the storage device performs the read operation once after performing the write operation at least once. 7 . The storage device according to claim 1 , wherein the input voltage received by the write word line is in an analog form, a multi-level form or a digital form.

8. The storage device according to claim 7, wherein when the input voltage is in analog form, the modulation method of the input voltage is amplitude modulation or pulse width modulation. 9 . The reservoir device according to claim 1 , wherein the first transistor is an N-type metal oxide semiconductor transistor or a P-type metal oxide semiconductor transistor, and the second transistor is an N-type metal oxide semiconductor transistor.

10. The storage device of claim 1, wherein the storage node is coupled to at least one physical capacitor, and the at least one physical capacitor is a ferroelectric capacitor, an electrochemically tunable capacitor, or an oxynitride oxide insulated capacitor. 11 . The storage device according to claim 1 , wherein the storage node is coupled to a plurality of physical capacitors, and the physical capacitors are coupled to each other in parallel and / or in series.

12. The storage device of claim 1, wherein the storage node is coupled to a capacitive element having a layout including a plurality of capacitors, wherein a capacitance value of the capacitive element is related to selective short-circuiting or disconnecting of the capacitors. 13 . The storage device according to claim 1 , wherein a parasitic capacitor is provided between the storage node and a ground point, and an equivalent capacitance value of the parasitic capacitor is related to a doping concentration of a PN junction of the first transistor or a size of the second transistor.

14. The storage device according to claim 1, further comprising: a third transistor coupled to the storage node; as well as A resistor is coupled to the drain of the first transistor and the write bit line.

15. A reservoir array, characterized in that: Having a plurality of transverse columns and a plurality of longitudinal rows, the reservoir array comprises: A plurality of storage elements, each of which is the storage device of claim 1, and the storage elements are respectively arranged in the transverse rows and the longitudinal rows, the transverse rows at least include a first transverse row and a second transverse row, and the longitudinal rows at least include a first longitudinal row and a second longitudinal row; The first transistors of the storage elements disposed in the first horizontal row are coupled to a first write word line, and the second transistors of the storage elements are coupled to a first read source line. The first transistors of the storage elements disposed in the second horizontal row are coupled to a second write word line, and the second transistors of the storage elements are coupled to a second read source line. The first transistors of the storage elements disposed in the first vertical row are coupled to a first write bit line, and the second transistors of the storage elements are coupled to a first read bit line. The first transistors of the storage elements disposed in the second vertical row are coupled to a second write bit line, and the second transistors of the storage elements are coupled to a second read bit line; and According to an input voltage respectively received by the first write word line, the first write bit line, the first read source line, the first read bit line, the second write word line, the second write bit line, the second read source line and the second read bit line, the storage elements selectively perform a write operation, a read operation or a refresh operation.

16. The reservoir array according to claim 15, wherein the first write word line and the second write word line are coupled to a first decoding circuit, the first read source line and the second read source line are coupled to a second decoding circuit, the first write bit line and the second write bit line are coupled to a third decoding circuit, the first read bit line and the second read bit line are coupled to a fourth decoding circuit, in, The second decoding circuit includes a read source line decoder and a plurality of sense amplifiers, and the read current of each second transistor is provided to a corresponding one of the sense amplifiers.

17. The reservoir array of claim 15, wherein The storage elements arranged in the first longitudinal row each have a first capacitor element having a first capacitance value, and the storage elements arranged in the second longitudinal row each have a second capacitor element having a second capacitance value, and the first capacitance value is not equal to the second capacitance value.

18. The reservoir array of claim 17, wherein the reservoir elements in the first longitudinal row perform a reservoir operation of a first task according to the first capacitance value, and the reservoir elements in the second longitudinal row perform a reservoir operation of a second task according to the second capacitance value, the first task being different from the second task.

19. The reservoir array according to claim 15, wherein the reservoir elements of the first longitudinal row perform the write operation, the read operation or the refresh operation independently of the reservoir elements of the second longitudinal row.

20. The reservoir array according to claim 19, wherein among the reservoir elements in the first longitudinal row, the reservoir elements in the first transverse column perform the write operation, the read operation or the refresh operation independently of the reservoir elements in the second transverse column.

21. The reservoir array according to claim 15, wherein the reservoir elements of the first longitudinal row and the reservoir elements of the second longitudinal row perform the refresh operation simultaneously.

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