Program operations in memory devices

Abstract

Example memory devices, memory systems, and methods for reducing the time of program operations in NAND flash memories are disclosed. One example method includes applying a first program voltage to a first word line coupled with a first string of memory cells of an array of memory cells between a first moment in time and a second moment in time to program first memory cells in the first string of memory cells. And between the second moment and a third moment, a second programming voltage higher than or equal to the first programming voltage is applied to the first word line so as to program a second storage unit in a second storage unit string of the storage unit array, and the first word line is coupled to the second storage unit string.

Description

Technical Field

[0001] The present disclosure relates to a memory device, a memory system, and a method for a programming operation in a flash memory. Background Art

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be erased and programmed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as programming (writing) and erasing operations, to change the threshold voltage of each memory cell to a corresponding level. For NAND flash memory, an erase operation can be performed at the block level, a programming operation can be performed at the page level, and a read operation can be performed at the page level. Summary of the invention

[0003] The present disclosure relates to a storage device, a storage system, and a method for reducing the time of a programming operation in a NAND flash memory. An example method includes applying a first programming voltage to a first word line coupled to a first memory cell string of a memory cell array between a first moment and a second moment to program a first memory cell in the first memory cell string. Between the second moment and a third moment, applying a second programming voltage higher than or equal to the first programming voltage to the first word line to program a second memory cell in a second memory cell string of the memory cell array, wherein the first word line is coupled to the second memory cell string.

[0004] Although generally described as computer-implemented software embodied on a tangible medium for processing and transforming corresponding data, some or all aspects may be computer-implemented methods, or further included in corresponding systems or other devices for performing the functions described. Details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example of a schematic diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0006] Figure 2 An example of a side view of a cross-section of a memory cell array including NAND memory strings according to some aspects of the present disclosure is shown.

[0007] Figure 3 Some example peripheral circuits according to some aspects of the present disclosure are shown.

[0008] Figure 4Examples of voltage conditions of components in a memory cell array during programming of memory cells in a plurality of memory cell strings of the memory cell array according to some aspects of the present disclosure are shown.

[0009] Figure 5 Another example of voltage conditions of components in a memory cell array during programming of memory cells in a plurality of memory cell strings of the memory cell array according to some aspects of the present disclosure is shown.

[0010] Figure 6 An example memory cell array having two memory cell strings according to some aspects of the present disclosure is shown.

[0011] Figure 7 An example of a flowchart of a method for reducing the time of a program operation in a memory device according to some aspects of the present disclosure is shown.

[0012] Figure 8 A block diagram of an example system with storage according to some aspects of the present disclosure is shown.

[0013] Fig.9A A diagram showing a memory card having a storage device according to some aspects of the present disclosure is shown.

[0014] Fig. 9B A diagram of a solid-state drive (SSD) having a storage device according to some aspects of the present disclosure is shown.

[0015] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0016] The specification relates to a storage device, a storage system, a method and a medium for reducing the time of programming operations in NAND flash memory. In some cases, a memory cell array may have multiple memory cell strings of memory cells. Each memory cell string may have memory cells corresponding to multiple cell columns. When memory cells in multiple memory cell strings are coupled to word lines and selected for programming, a programming pulse may be applied to the word lines, and programming operations of all memory cells coupled to the word lines and selected for programming may be performed within the programming pulse without applying a voltage ramp down to the word lines between programming of memory cells in different memory cell strings. Therefore, since the application of voltage ramp down and ramp up to the word lines is eliminated between programming of memory cells in different memory cell strings, the time for programming memory cells coupled to the word lines can be reduced.

[0017] Figure 1An example of a schematic circuit diagram of a memory device 100 including peripheral circuits according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically above a substrate (not shown). Each memory cell 106 may hold a continuous analog value, such as a voltage or charge depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0018] In some embodiments, each memory cell 106 is a single-level cell (SLC) having two possible storage states, and thus can store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to take one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. The fourth nominal storage value can be used for the erased state.

[0019] like Figure 1As shown, each NAND memory string 108 may include a source select gate (SSG) 110 at its source end and a drain select gate (DSG) 112 at its drain end. SSG 110 and DSG 112 may be configured to activate a selected NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled through the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, from which data may be read or written via an output bus (not shown). In some embodiments, each NAND memory string 108 is configured to be selected or deselected by applying a select voltage (e.g., higher than a threshold voltage of a transistor having DSG 112) or a deselect voltage (e.g., 0 V) ​​to a corresponding DSG 112 via one or more DSG lines 113, and / or applying a select voltage (e.g., higher than a threshold voltage of a transistor having SSG 110) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG 110 via one or more SSG lines 115.

[0020] like Figure 1 As shown, the NAND memory strings 108 can be organized into a plurality of blocks 104, each of which can have a common source line 114, for example, coupled to an ACS. In some embodiments, each block 104 is a basic data unit for an erase operation, i.e., all memory cells 106 on the same block 104 are erased simultaneously. In order to erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and the unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). In some examples, the erase operation can be performed at a half-block level, a quarter-block level, or a level with any appropriate number of blocks or any appropriate fraction of blocks. The memory cells 106 of adjacent NAND memory strings can be coupled by word lines 118, which select which row of the memory cells 106 is affected by the read and program operations. Each word line 118 may include a plurality of control gates (gate electrodes) at each memory cell 106 in a corresponding page 120 and a gate line coupling the control gates. Figure 1The example word lines shown in illustrative example embodiments include dummy WLs, WL1 , WL2 , WL3 , WL4 , and WL5 located between one or more DSG lines 113 and one or more SSG lines 115 .

[0021] Figure 2 An example of a side view of a cross section of a memory cell array 101 including NAND memory strings 108 according to some aspects of the present disclosure is shown. Figure 2 As shown, the NAND memory strings 108 may extend vertically through a memory stack 204 above a substrate 202. The substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0022] The memory stack 204 may include interlaced gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate, DSG 112, or SSG 110 surrounding the memory cell 106, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between the DSG line 113 and the SSG line 115.

[0023] like Figure 1As shown, consistent with the scope of the present disclosure, since the programming operation is performed at the page / word line level for each block 104, each block 104 can be an open block or a full block depending on whether all pages in the corresponding block 104 have been programmed. In some embodiments, if at least one page 120 in the block 104 is not programmed, that is, the storage cells 106 in at least one page 120 in the block 104 are in an erased state, the block 104 is an open block. For example, an open block may include one or more unprogrammed pages. In some embodiments, if all pages 120 in the block 104 are programmed, that is, the storage cells 106 in all pages 120 in the block 104 are in a programmed state, the block 104 is a full block. For example, a full block may not include any unprogrammed pages.

[0024] The peripheral circuit 102 is coupled to the memory cell array 101 through the bit line 116, the word line 118, the source line 114, the SSG line 115, and the DSG line 113. The peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuits for applying a voltage signal and / or a current signal to each target memory cell of the memory cell 106 and sensing a voltage signal and / or a current signal from each target memory cell of the memory cell 106 through the bit line 116, the word line 118, the source line 114, the SSG line 115, and the DSG line 113 to facilitate the operation of the memory cell array 101. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some example peripheral circuits according to some aspects of the present disclosure are shown. The example peripheral circuits include page buffers / sense amplifiers 304, column decoders / bit line drivers 306, row decoders / word line drivers 308, voltage generators 310, control logic 312, registers 314, interfaces 316, and data buses. In some examples, the example peripheral circuits may also include Figure 3 Additional peripheral circuits not shown.

[0025] The page buffer / sense amplifier 304 may be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 according to a control signal from the control logic 312. In one example, the page buffer / sense amplifier 304 may store a page of programming data (write data) to be programmed into a page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may perform a program verification operation to ensure that the data has been properly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may also sense a low-power signal from the bit line 116 representing a data bit stored in the memory cell 106 in a read operation and amplify a small voltage swing to a recognizable logic level. The column decoder / bit line driver 306 may be configured to be controlled by the control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from the voltage generator 310.

[0026] The row decoder / word line driver 308 may be configured to be controlled by the control logic 312 and to select / deselect the block 104 of the memory cell array 101 and to select / deselect the word line 118 of the block 104. The row decoder / word line driver 308 may be further configured to drive the word line 118 using the word line voltage generated from the voltage generator 310. In some embodiments, the row decoder / word line driver 308 may also select / deselect and drive the SSG pair line 115 and the DSG line 113. As described in detail below, the row decoder / word line driver 308 is configured to apply a read voltage to the selected word line 118 in a read operation of the memory cell 106 coupled to the selected word line 118.

[0027] The voltage generator 310 may be configured to be controlled by the control logic 312 and generate word line voltages (eg, read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101 .

[0028] The control logic 312 may be coupled to each of the above-mentioned peripheral circuits and configured to control the operation of each peripheral circuit. The register 314 may be coupled to the control logic 312 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. As described in detail below, the status register of the register 314 may include one or more registers configured to store open block information indicating the open blocks (single or multiple) of all blocks 104 in the memory cell array 101, such as having an ADSV list. In some embodiments, the open block information also indicates the last programming page of each open block.

[0029] The interface 316 may be coupled to the control logic 312 and used as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic 312 and status information received from the control logic 312 to the host. The interface 316 may also be coupled to the column decoder / bit line driver 306 via a data bus and used as a data input / output (I / O) interface and a data buffer to buffer and relay data to and from the memory cell array 101.

[0030] Figure 4 An example of voltage conditions of components in a memory cell array during programming of memory cells in a plurality of memory cell strings in the memory cell array according to some aspects of the present disclosure is shown. In some embodiments, select WL represents a word line (e.g., a first word line) selected for programming operations of memory cells coupled to a word line and in a plurality of memory cell strings in the memory cell array. Select WL may be Figure 1 1. An example of a word line 118 in FIG. Unselected WLs represent word lines coupled to memory cells in a plurality of memory cell strings and not selected for programming. Unselected WLs may be Figure 1 118 in FIG. 119. Dummy WL represents a word line coupled to a dummy memory cell in a plurality of memory cell strings. String0_SSL or String1_SSL represents one or more string select lines (SSL) (e.g., Figure 1 The string select line (SSL) is coupled to one or more select gate transistors, such as DSG line 113 in FIG. Figure 1 The selected GSL or unselected GSL indicates a GSL coupled to one or more select gate transistors (e.g., Figure 1 One or more ground select lines (GSL) of SSG110 in the embodiment, for example, SSG line 115. Figure 4 Each of the four bit lines (BL) in the voltage state shown in FIG. 1 represents a bit line coupled to a plurality of cell columns in a plurality of memory cell strings of a memory cell array and may be Figure 1 An example of bit line 116 in FIG.

[0031] In some embodiments, having Figure 4 The components of the voltage conditions shown in the figure can be mapped to Figure 6 Components in . Figure 6 An example memory cell array 600 having two memory cell strings (String0 and String1) according to some aspects of the present disclosure is shown. String0 includes memory cells associated with cell column 1 and cell column 3. String1 includes memory cells associated with cell column 2 and cell column 4. Figure 4 From t 0 (e.g., first moment) to t 1 During the time period (eg, the second time instant), one or more memory cells in String0 coupled to the selected word line may be selected for programming. Then, Figure 4 From t 1 to 2 During a time period (eg, a third moment), one or more memory cells in String1 coupled to a selected word line may be selected for programming.

[0032] More specifically, in some embodiments, in order to 0 to 1 Program one or more memory cells in String0, with a programming voltage (eg, a first programming voltage), such as Figure 4 From t 0 to 1 The Vpgm applied to Sel.WL can be obtained from Figure 4 t in 0 to 1 is applied to a selected word line coupled to both String0 and String1, e.g. Figure 6 WLn616 in (corresponding to Figure 4 The selected word line is coupled to the selected word line in String0 for use from t 0 to 1 Program one or more memory cells.

[0033] In some embodiments, in the 0 to 1 After programming one or more memory cells in String0, you can 1 to 2Program one or more memory cells in String1. 1 to 2 Program one or more memory cells in String1 with a programming voltage (eg, a second programming voltage), such as Figure 4 From t 1 to 2 The Vpgm applied to Sel.WL can be obtained from Figure 4 t in 1 to 2 is applied to a selected word line coupled to both String0 and String1, e.g. Figure 6 WLn 616 in (corresponding to Figure 4 The selected word line is coupled to the selected word line in String1 for use from t 1 to 2 Therefore, by programming one or more memory cells from t 0 to 1 Immediately after applying a programming voltage to the selected word line (to program one or more memory cells in String0), the 1 to 2 A programming voltage is applied to a selected word line (to program one or more memory cells in String1), and a voltage ramp down and subsequent voltage ramp up are not used between programming one or more memory cells in String0 and programming one or more memory cells in String1, and thus the total time used to program the memory cells in both String0 and String1 can be reduced.

[0034] In some embodiments, when one or more memory cells in String0 are programmed, a voltage (eg, a fourth voltage) is applied, such as Figure 4 From t 0 to 1 Vpass applied to Unsel.WL can be obtained from t 0 to 1 is applied to an unselected word line (eg, the second word line), for example, Figure 6 WL0 618 in (corresponding to Figure 4 Unsel.WL in String0 and String1). The unselected word lines are coupled to the unselected word lines in String0 and String1 for use from t 0 to 1 of programmed memory cells.

[0035] In some embodiments, when one or more memory cells in String1 are programmed, a voltage, such as Figure 4 From t 1 to 2 Vpass applied to Unsel.WL can be obtained from t 1 to 2 is applied to unselected word lines, e.g., Figure 6 WL0 618 in (corresponding to Figure 4 Unsel.WL in String0 and String1). The unselected word lines are coupled to the unselected word lines in String0 and String1 for use from t 1 to 2 of programmed memory cells.

[0036] In some embodiments, when one or more memory cells in String0 are programmed, a voltage, such as Figure 4 From t 0 to 1 Vpass applied to the dummy word line WL can be 0 to 1 is applied to a dummy word line, for example, Figure 6 The dummy word lines 608, 610, 612, 614, 620 and 622 (corresponding to Figure 4 The dummy word line is coupled to the dummy memory cells in String0 and String1.

[0037] In some embodiments, when one or more memory cells in String1 are programmed, a voltage, such as Figure 4 From t 1 to 2 Vpass applied to the dummy word line WL can be 1 to 2 is applied to a dummy word line, for example, Figure 6 The dummy word lines 608, 610, 612, 614, 620 and 622 (corresponding to Figure 4 In the virtual WL).

[0038] In some embodiments, when one or more memory cells in String0 are programmed, the turn-on voltage (first voltage), e.g. Figure 4 From t 0 to 1 is applied to String0_SSL's Von, which can be obtained from t 0 to 1 is applied to one or more string selection lines (eg, first selection lines) coupled to String0 to turn on top selection gate (TSG) transistors in String0, such as the top selection gates in String0 respectively coupled to Figure 6The TSG transistors of the string selection lines 602, 604 and 606 in FIG. 1 may include one or more SSLs. Figure 6 SSL 602 to SSL 606 (corresponding to Figure 4 String0_SSL in .

[0039] In some embodiments, when programming one or more memory cells in String1, the voltage is turned off, e.g. Figure 4 From t 1 to 2 The voltage applied to String0_SSL may be applied to one or more string select lines (SSL) coupled to String0 to select the voltage from t 1 to 2 Turn off the memory cells in String0.

[0040] In some embodiments, when one or more memory cells in String0 are programmed, a voltage (eg, a second voltage) is turned off, such as Figure 4 From t 0 to 1 Vss applied to String1_SSL may be applied to one or more SSLs (eg, second select lines) coupled to String1 to provide a voltage from t 0 to 1 Turn off the TSG transistor in String1. For example, String1 is coupled to Figure 6 The TSG crystals of the string selection lines 632, 634 and 636 in FIG. An example of one or more SSLs may include Figure 6 SSL 632 to SSL 636 (corresponding to Figure 4 An example value for Vss is 0V.

[0041] In some embodiments, when programming one or more memory cells in String1, a turn-on voltage, e.g. Figure 4 From t 1 to 2 Von applied to String1_SSL can be applied to one or more SSLs coupled to String1 to 1 to 2 Turn on the storage unit in String1. Examples of one or more SSLs may include Figure 6 SSL 632 to SSL 636 (corresponding to Figure 4An example value of Vss is 0 V. The on-voltage applied to one or more SSLs coupled to String1 may be the same as or different from the on-voltage applied to one or more SSLs coupled to String0.

[0042] In some embodiments, a voltage Vss (eg, a third voltage) may be applied to all ground select lines (GSL) to provide a ground voltage from t 0 to 2 Ground them. The grounded GSL may include a GSL (eg, a third select line) coupled to String0 (eg, Figure 4 Sel.GSL in String1), and GSL (e.g., the fourth selection line) coupled to String1 (e.g., Figure 4 An example GSL coupled to String0 may include Figure 6 624 in GSL1. An example GSL coupled to String1 may include Figure 6 An example value of Vss is 0 V. In some implementations, ACS 626 can be coupled to multiple strings of a memory cell array.

[0043] In some embodiments, a bit line may be coupled to a plurality of memory cell strings of a memory cell array. Figure 6 BLn 628 in String0 is coupled to memory cells associated with cell column 1 in String0 and memory cells associated with cell column 2 in String1. Figure 6 BLn+1 630 in String 1 is coupled to memory cells associated with cell column 3 in String 0 and memory cells associated with cell column 4 in String 1 .

[0044] In some embodiments, "String0 sel.BL, String1 unsel.BL" indicates a bit line coupled to a first cell column coupled to String0 and a second cell column coupled to String1. 0 to 1 During the time period from t 1 to 2 During the time period of t , no memory cell associated with the second cell column is selected for programming. A voltage (eg, a fifth voltage), for example, from t 0 to 1 Applied to Figure 4The voltage Vi of “String0 sel.BL, String1 unsel.BL” in String0 may be applied to “String0 sel.BL, String1 unsel.BL” to reduce the programming speed of the memory cells coupled to “String0 sel.BL, String1 unsel.BL” and in String0. The voltage Vi applied to “String0 sel.BL, String1 unsel.BL” may also turn on the TSG coupled to “String0 sel.BL, String1 unsel.BL” and enable the memory cells coupled to “String0 sel.BL, String1 unsel.BL” to be programmed, although at a reduced speed. A voltage (e.g., a sixth voltage), e.g. Figure 4 From t 1 to 2 Vinhibit applied to "String0 sel.BL, String1 unsel.BL" can be obtained from t 1 to 2 Applied to "String0 sel.BL, String1 unsel.BL" to turn off the TSG coupled to "String0 sel.BL, String1 unsel.BL" and inhibit programming of the memory cell coupled to "String0 sel.BI, String1 unsel.BL" and in String1. Vi may be less than Vinhibit and greater than 0V. In some embodiments, the voltage applied to "String0 sel.BL, String1 unsel.BL" may be greater than t 1 A few microseconds earlier, the ramp from Vi to Vinhibit begins, t 1 is the moment when the voltage applied to String1_SSL begins to ramp up from the off voltage (eg, Vss) to the on voltage (eg, Von).

[0045] In some embodiments, "String0 sel.BL, String1 sel.BL" indicates a bit line coupled to a first cell column coupled to String0 and a second cell column coupled to String1. 0 to 1 During the time period from t 1 to 2 During the time period of , some memory cells associated with the second cell column are selected for programming. A voltage (eg, a seventh voltage), such as Figure 4From t 0 to 1 Vi applied to "String0 sel.BL, String1 sel.BL" can be applied to "String0 sel.BL, String1 sel.BL" to reduce the programming speed of the memory cell coupled to "String0 sel.BL, String1 sel.BL" and in String0. 1 to 2 A voltage lower than Vi, such as Vss, is applied to "String0 sel.BL, String1 sel.BL" to program the memory cell coupled to "Stringe0 sel.BI, String1 sel.BL" and in String1. An example value of Vss is 0V.

[0046] In some embodiments, "String0 unsel.BL, String1 sel.BL" represents a bit line coupled to a first cell column coupled to String0 and a second cell column coupled to String1. 0 to 1 During the time period from t ... 1 to 2 During the time period of , some memory cells associated with the second cell column are selected for programming. A voltage (eg, an eighth voltage), such as Figure 4 From t 0 to 1 The Vinhibit applied to "String0 unsel.BL, String1 sel.BL" can be obtained from t 0 to 1 Applied to "String0unsel.BL, String1 sel.BL" to inhibit programming of memory cells coupled to "String0unsel.BI, String1 sel.BL" and in String0. Figure 4 The voltage of Vi, such as Vss, can be obtained from t 1 to 2Applied to "String0 unsel.BL, String1 sel.BL" to program the memory cell coupled to "String0 unsel.BL, String1 sel.BL" and in String1. An example value of Vss is 0V. In some embodiments, the voltage applied to "String0 unsel.BL, String1 sel.BL" can be at t 1 A few microseconds later, it starts to ramp down from Vinhibit to a voltage lower than Vi (e.g., Vss), t 1 It is the moment when the voltage applied to String0_SSL completes ramping down from the on-voltage (eg, Von) to the off-voltage (eg, Vss).

[0047] In some embodiments, "String0 unsel.BL, String1 unsel.BI" represents a bit line coupled to a first cell column coupled to String0 and a second cell column coupled to String1. 0 to 1 During the time period from t ... 1 to 2 During the time period of , no memory cell associated with the second cell column is selected for programming. A voltage (eg, a ninth voltage), such as Figure 4 From t 0 to 1 Vinhibit applied to "String0 unsel.BL, String1 unsel.BL" can be obtained from t 0 to 1 Applied to "String0 unsel.BL, String1 unsel.BL" to inhibit programming of memory cells coupled to "String0 unsel.BI, String1 unsel.BL" and in String0. Voltage, e.g. Figure 4 From t 1 to 2 The voltage Vinhibit applied to "String0 unssel.BL, String1 unsel.BL" can be 1 to 2 Applied to “String0 unsel.BL, String1 unsel.BL” to inhibit programming of memory cells coupled to “String0 unsel.BL, String1 unsel.BL” and in String1.

[0048] Figure 5 Another example of voltage conditions of components in a memory cell array during programming of memory cells in a plurality of memory cell strings of the memory cell array according to some aspects of the present disclosure is shown. In addition to the selected WL, the unselected WL, and the dummy WL, Figure 5 The voltage conditions of most components in Figure 4 More specifically, due to Figure 5 The voltage of each word line in can ramp down when the memory cell string coupled to the memory cell selected for programming is turned on and the channel corresponding to the memory cell string can be discharged, so an additional voltage can be applied to each word line when the memory cell string coupled to the memory cell selected for programming is turned on. Figure 5 It shows that when t 1 to 2 An additional voltage is applied to each word line when the memory cells in String1 are selected for programming.

[0049] Figure 7 An example of a flow chart of a method for reducing the time of a programming operation in a memory device according to some aspects of the present disclosure is shown. At 702, a peripheral circuit of a memory device applies a first voltage to a first word line coupled to the first memory cell at a first time and during a channel preparation period of a programming operation of a first memory cell in a memory cell array.

[0050] At 704 , the peripheral circuit applies a second voltage to the first word line at a second time after the first time and during a channel preparation period, wherein the second voltage is lower than the first voltage.

[0051] At 706 , the peripheral circuit applies a program voltage to the first word line after the channel preparation period and during a program operation of the first memory cell.

[0052] Figure 8 A block diagram of an example system 800 with a storage device according to some aspects of the present disclosure is shown. The system 800 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 8As shown, system 800 may include a host 808 and a storage system 802, the storage system 802 having one or more storage devices 804 and a memory controller 806. The host 808 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 808 may be configured to send data to the storage device 804 or receive data from the storage device 804.

[0053] The storage device 804 may be any storage device disclosed in the present disclosure. According to some embodiments, the memory controller 806 is coupled to the storage device 804 and the host 808 and is configured to control the storage device 804. The memory controller 806 may manage data stored in the storage device 804 and communicate with the host 808. In some embodiments, the memory controller 806 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 806 is designed to operate in a high duty cycle environment SSD or an embedded multi-media card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 806 may be configured to control the operation of the storage device 804, such as read, erase, and program operations. The memory controller 806 may also be configured to manage various functions regarding data stored or to be stored in the storage device 804, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 806 is further configured to process error correction code (ECC) regarding data read from or written to the storage device 804. The memory controller 806 may also perform any other suitable functions, such as formatting the storage device 804.

[0054] The memory controller 806 may communicate with an external device (e.g., the host 808) according to a specific communication protocol. For example, the memory controller 806 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0055] The memory controller 806 and one or more storage devices 804 may be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 802 may be implemented and packaged into different types of terminal electronic products. Fig.9A In one example shown, the memory controller 806 and the single storage device 804 may be integrated into a memory card 902. The memory card 902 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 902 may also include a processor that connects the memory card 902 to a host (e.g., Figure 8 The host 808 in the memory card connector 904 is coupled. Fig. 9B In another example shown, the memory controller 806 and the plurality of storage devices 804 may be integrated into the SSD 906. The SSD 906 may also include a processor that connects the SSD 906 to a host (eg, Figure 8 In some implementations, the storage capacity and / or operating speed of the SSD 906 is greater than the storage capacity and / or operating speed of the memory card 902.

[0056] Certain aspects of the subject matter described herein may be implemented as a memory device. The memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory cell strings coupled to a first word line, wherein each of the plurality of memory cell strings includes a first selection gate transistor, a second selection gate transistor coupled to a source line of the memory cell array, and one or more memory cells located between the first selection gate transistor and the second selection gate transistor. The peripheral circuit is coupled to the memory cell array and is configured to perform an operation including applying a first programming voltage to the first word line between a first moment and a second moment to program a first memory cell in a first memory cell string in the plurality of memory cell strings. The operation also includes applying a second programming voltage higher than or equal to the first programming voltage to the first word line between the second moment and a third moment to program a second memory cell in a second memory cell string in the plurality of memory cell strings.

[0057] The storage device may include one or more of the following features.

[0058] In some embodiments, the operation also includes: applying a first voltage to a first selection line coupled to a first selection gate transistor of the first memory cell string at the first moment, wherein the first voltage is lower than the first programming voltage; and applying a second voltage to the first selection line at the second moment, wherein the second voltage is lower than the first voltage.

[0059] In some embodiments, the operation further includes: applying the second voltage to a second selection line coupled to a first selection gate transistor of the second memory cell string at the first time; and applying the first voltage to the second selection line at the second time.

[0060] In some embodiments, the operation further includes: applying a third voltage to a third selection line coupled to a second selection gate transistor of the first memory cell string between the first moment and the third moment, wherein the third voltage is lower than or equal to the second voltage.

[0061] In some embodiments, the operation further includes: applying a third voltage to a fourth selection line coupled to a second selection gate transistor of the second memory cell string between the first moment and the third moment, wherein the third voltage is lower than or equal to the second voltage.

[0062] In some embodiments, the operation also includes: applying a fifth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment; and applying a sixth voltage to the bit line between the first moment and the second moment, wherein the sixth voltage is higher than the fifth voltage and lower than the first voltage.

[0063] In some embodiments, the operation also includes: applying a fifth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment, wherein the fifth voltage is lower than the first voltage; and applying a third voltage to the bit line between the first moment and the second moment, wherein the third voltage is lower than the fifth voltage.

[0064] In some embodiments, the operation also includes: applying a sixth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment, wherein the sixth voltage is lower than the first voltage; and applying a third voltage to the bit line between the second moment and the third moment, wherein the third voltage is lower than the sixth voltage.

[0065] In some embodiments, the operation also includes applying a sixth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment, wherein the sixth voltage is lower than the first voltage; and applying a third voltage to the bit line at the third moment, wherein the third voltage is lower than the sixth voltage.

[0066] In some implementations, the plurality of memory cell strings are coupled to a second word line, and the operation further includes applying a fourth voltage to the second word line at the first time, wherein the fourth voltage is lower than the first programming voltage.

[0067] In some implementations, the plurality of memory cell strings are coupled to a dummy word line, and the operation further includes applying the fourth voltage to the dummy word line at the first time.

[0068] In some embodiments, the first memory cell and the second memory cell are single-level cells (SLC).

[0069] Certain aspects of the subject matter described herein may be implemented as a memory system. The memory system includes a memory device and a controller. The memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory cell strings coupled to a first word line, wherein each of the plurality of memory cell strings includes a first selection gate transistor, a second selection gate transistor coupled to a source line of the memory cell array, and one or more memory cells located between the first selection gate transistor and the second selection gate transistor. The peripheral circuit is coupled to the memory cell array and is configured to perform an operation including applying a first programming voltage to the first word line between a first moment and a second moment to program a first memory cell in a first memory cell string in the plurality of memory cell strings. The operation also includes applying a second programming voltage higher than or equal to the first programming voltage to the first word line between the second moment and a third moment to program a second memory cell in a second memory cell string in the plurality of memory cell strings. The controller is coupled to the memory device and configured to send a signal to the memory device to initiate the operation.

[0070] The storage system may include one or more of the following features.

[0071] In some embodiments, the operation also includes: applying a first voltage to a first selection line coupled to a first selection gate transistor of the first memory cell string at the first moment, wherein the first voltage is lower than the first programming voltage; and applying a second voltage to the first selection line at the second moment, wherein the second voltage is lower than the first voltage.

[0072] In some embodiments, the operation further includes: applying the second voltage to a second selection line coupled to a first selection gate transistor of the second memory cell string at the first time; and applying the first voltage to the second selection line at the second time.

[0073] In some embodiments, the operation also includes: applying a fifth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment; and applying a sixth voltage to the bit line between the first moment and the second moment, wherein the sixth voltage is higher than the fifth voltage and lower than the first voltage.

[0074] In some embodiments, the operation also includes: applying a fifth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment, wherein the fifth voltage is lower than the first voltage; and applying a third voltage to the bit line between the first moment and the second moment, wherein the third voltage is lower than the fifth voltage.

[0075] In some embodiments, the operation also includes: applying a sixth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment, wherein the sixth voltage is lower than the first voltage; and applying a third voltage to the bit line between the second moment and the third moment, wherein the third voltage is lower than the sixth voltage.

[0076] In some embodiments, the operation also includes applying a sixth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first moment, wherein the sixth voltage is lower than the first voltage; and applying a third voltage to the bit line at the third moment, wherein the third voltage is lower than the sixth voltage.

[0077] Certain aspects of the subject matter described herein may be implemented as a method. The method includes applying a first programming voltage to a first word line coupled to a first memory cell string of a memory cell array between a first time and a second time to program a first memory cell in the first memory cell string. Applying a second programming voltage higher than or equal to the first programming voltage to the first word line between the second time and a third time to program a second memory cell in a second memory cell string of the memory cell array, wherein the first word line is coupled to the second memory cell string.

[0078] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in this specification in the context of a separate implementation may also be implemented in combination in a single implementation. On the contrary, the various features described in the context of a single implementation may also be implemented in multiple implementations, individually or in any sub-combination. In addition, although the previously described features may be described as working in certain combinations, and even initially claimed to be protected as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may point to a variant of a sub-combination or a sub-combination.

[0079] The terms "a", "an" or "the" as used in this disclosure are intended to include one or more, unless the context clearly dictates otherwise. Unless otherwise indicated, the term "or" is used to refer to a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the words or terms used in this disclosure and not otherwise defined are intended to be descriptive only and not limiting. The use of any section headings is intended to aid in reading the document and is not to be construed as limiting; information associated with a section heading may appear within or outside that particular section.

[0080] As used in this disclosure, the terms "about" or "approximately" may allow a certain degree of variability in a value or range, for example, within 10%, 5% or 1% of the stated value or the stated limit of the stated range.

[0081] As used in this disclosure, the term "substantially" refers to a majority, or a majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0082] Values ​​expressed in range format should be interpreted in a flexible manner to include not only the values ​​explicitly stated as the limits of the range, but also all individual values ​​or subranges contained within the range, as if each value and subrange were explicitly stated. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3% and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise specified, the statement "X to Y" has the same meaning as "about X to about Y". Similarly, unless otherwise specified, the statement "X, Y or Z" has the same meaning as "about X, about Y or about Z".

[0083] Specific embodiments of the subject matter have been described. Other embodiments, modifications, and permutations of the described embodiments are within the scope of the following claims and will be apparent to those skilled in the art. Although operations are described in a particular order in the drawings or claims, it is not required that the operations be performed in the particular order or sequential order shown, or that all of the operations shown (some operations may be considered optional), be performed to achieve the desired results. In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed where deemed appropriate.

[0084] Furthermore, the various system modules and components in the previously described embodiments may not need to be separated or integrated in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0085] Therefore, the example embodiments described above do not define or constrain the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

Claims

1. A storage device, comprising: a memory cell array comprising a plurality of memory cell strings coupled to a first word line, wherein each of the plurality of memory cell strings comprises a first select gate transistor, a second select gate transistor coupled to a source line of the memory cell array, and one or more memory cells located between the first select gate transistor and the second select gate transistor; and A peripheral circuit coupled to the memory cell array and configured to perform an operation comprising: Between a first time and a second time, applying a first programming voltage to the first word line to program a first memory cell in a first memory cell string among the plurality of memory cell strings; and Between the second time and the third time, a second programming voltage higher than or equal to the first programming voltage is applied to the first word line to program a second memory cell in a second memory cell string among the plurality of memory cell strings.

2. The storage device according to claim 1, wherein: The operations also include: applying a first voltage to a first selection line coupled to a first selection gate transistor of the first memory cell string at the first time, wherein the first voltage is lower than the first programming voltage; and A second voltage is applied to the first selection line at the second time, wherein the second voltage is lower than the first voltage.

3. The storage device according to claim 2, wherein: The operations also include: applying the second voltage to a second selection line coupled to a first selection gate transistor of the second memory cell string at the first time; and The first voltage is applied to the second selection line at the second time.

4. The storage device according to claim 3, wherein: The operations also include: Between the first time and the third time, a third voltage is applied to a third selection line coupled to the second selection gate transistor of the first memory cell string, wherein the third voltage is lower than or equal to the second voltage.

5. The storage device according to claim 3, wherein: The operations also include: Between the first time and the third time, a third voltage is applied to a fourth selection line coupled to the second selection gate transistor of the second memory cell string, wherein the third voltage is lower than or equal to the second voltage.

6. The storage device according to any one of claims 2 to 5, wherein: The operations also include: applying a fifth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time; and Between the first time and the second time, a sixth voltage is applied to the bit line, wherein the sixth voltage is higher than the fifth voltage and lower than the first voltage.

7. The storage device according to claim 2 or 3, wherein: The operations also include: applying a seventh voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time, wherein the seventh voltage is lower than the first voltage; and Between the first time and the second time, a third voltage is applied to the bit line, wherein the third voltage is lower than the seventh voltage.

8. The storage device according to claim 2 or 3, wherein: The operations also include: applying an eighth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time, wherein the eighth voltage is lower than the first voltage; and Between the second time and the third time, a third voltage is applied to the bit line, wherein the third voltage is lower than the eighth voltage.

9. The storage device according to claim 2 or 3, wherein: The operations also include: applying a ninth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time, wherein the ninth voltage is lower than the first voltage; and A third voltage is applied to the bit line at the third time, wherein the third voltage is lower than the ninth voltage.

10. The storage device according to any one of claims 1 to 9, wherein: The plurality of memory cell strings are coupled to a second word line, and wherein the operations further comprise: A fourth voltage is applied to the second word line at the first time, wherein the fourth voltage is lower than the first programming voltage.

11. The storage device according to claim 10, wherein: The plurality of memory cell strings are coupled to a dummy word line, and wherein the operations further comprise: The fourth voltage is applied to the dummy word line at the first time.

12. The storage device according to any one of claims 1 to 11, wherein: The first memory cell and the second memory cell are single level cells (SLC).

13. A storage system comprising: A storage device comprising: a memory cell array comprising a plurality of memory cell strings coupled to a first word line, wherein each of the plurality of memory cell strings comprises a first select gate transistor, a second select gate transistor coupled to a source line of the memory cell array, and one or more memory cells located between the first select gate transistor and the second select gate transistor; and A peripheral circuit coupled to the memory cell array and configured to perform an operation comprising: Between a first time and a second time, applying a first programming voltage to the first word line to program a first memory cell in a first memory cell string among the plurality of memory cell strings; and Between the second time and the third time, applying a second programming voltage higher than or equal to the first programming voltage to the first word line to program a second memory cell in a second memory cell string among the plurality of memory cell strings; and A controller is coupled to the memory device and is configured to send a signal to the memory device to initiate the operation.

14. The storage system according to claim 13, wherein: The operations also include: applying a first voltage to a first selection line coupled to a first selection gate transistor of the first memory cell string at the first time, wherein the first voltage is lower than the first programming voltage; and A second voltage is applied to the first selection line at the second time, wherein the second voltage is lower than the first voltage.

15. The storage system according to claim 14, wherein: The operations also include: applying the second voltage to a second selection line coupled to a first selection gate transistor of the second memory cell string at the first time; and The first voltage is applied to the second selection line at the second time.

16. The storage system according to claim 14 or 15, wherein: The operations also include: applying a fifth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time; and Between the first time and the second time, a sixth voltage is applied to the bit line, wherein the sixth voltage is higher than the fifth voltage and lower than the first voltage.

17. The storage system according to claim 14 or 15, wherein: The operations also include: applying a seventh voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time, wherein the seventh voltage is lower than the first voltage; and Between the first time and the second time, a third voltage is applied to the bit line, wherein the third voltage is lower than the seventh voltage.

18. The storage system according to claim 14 or 15, wherein: The operations also include: applying an eighth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time, wherein the eighth voltage is lower than the first voltage; and Between the second time and the third time, a third voltage is applied to the bit line, wherein the third voltage is lower than the eighth voltage.

19. The storage system according to claim 14 or 15, wherein: The operations also include: applying a ninth voltage to a bit line coupled to the first memory cell string and the second memory cell string at the first time, wherein the ninth voltage is lower than the first voltage; and A third voltage is applied to the bit line at the third time, wherein the third voltage is lower than the ninth voltage.

20. A method comprising: Between a first time and a second time, applying a first programming voltage to a first word line coupled to a first memory cell string of a memory cell array to program a first memory cell in the first memory cell string; as well as Between the second moment and the third moment, a second programming voltage higher than or equal to the first programming voltage is applied to the first word line to program a second memory cell in a second memory cell string of the memory cell array, wherein the first word line is coupled to the second memory cell string.

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