Clamping circuit suitable for NOR flash reading system and memory
By designing a clamp circuit of a shared read reference generation module in the NOR flash read system, the chip area increase problem caused by the complex clamping circuit structure in the prior art is solved, and the reliability of voltage clamping and read operation is improved, while simplifying the circuit structure and reducing the layout area.
Patent Information
- Application Number
- CN202411798445.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-28
AI Technical Summary
The clamp circuit in the prior art has a complex structure, resulting in an increase in the overall chip area, which is not suitable for scenarios where there are a large number of reading unit circuits in NOR flash reading systems.
A clamping circuit suitable for NOR flash reading system is designed, including a reading reference generation module and multiple reading unit modules. Through multiple reading unit modules, a reading reference generation module is shared by multiple reading unit modules, the transmission of global reference voltage signals is realized, the circuit structure is simplified and the layout area is reduced.
Voltage clamping is realized, which improves the reliability of read operations, while simplifies the circuit structure and reduces the space occupied by the clamping circuit in the chip system.
Smart Images
Figure CN119724299A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of circuit technology, and in particular to a clamping circuit and a memory suitable for a NOR flash reading system. Background Art
[0002] Non-volatile memory (NVM) refers to a memory in which the stored data will not disappear after power failure. In non-volatile memory, there are two major categories of products, namely read-only memory (ROM) and flash memory, based on whether the data in the memory can be rewritten at any time when using the computer. Among them, flash memory is the mainstream, mainly including NAND Flash and NOR Flash. With the continuous development of IoT devices, data storage is becoming more and more important at the moment. Since NOR Flash memory not only has the ability to be repeatedly erased and written, but also has the characteristics of small size and low power consumption, it is used in micro digital devices in different application scenarios.
[0003] The read, write and erase operations of NOR Flash memory chips require a fixed voltage to be applied to each end of the storage cell. For example, in the design of the NOR flash read system, the voltage clamping of the drain end of the storage cell needs to be considered. The potential change of the cell drain end will cause the cell current to change, causing errors in the read operation. Therefore, in order to improve the accuracy of the read operation, it is necessary to set a voltage clamping circuit to ensure that the drain voltage of the cell is as stable as possible.
[0004] The existing voltage clamping circuit has a complex structure. When used in a NOR flash chip reading system, due to the large number of reading unit circuits, once the existing clamping circuit has a complex structure, the overall chip area of the system will increase.
[0005] Therefore, it is a technical problem that needs to be solved urgently by those skilled in the art to provide a clamping circuit and memory suitable for a NOR flash read system that can achieve voltage clamping, improve the reliability of the read operation, simplify the circuit structure, and minimize the circuit layout area. Summary of the invention
[0006] In order to solve the above technical problems, the present disclosure provides a clamping circuit and a memory suitable for a NOR flash read system, so as to solve the problem that the clamping circuit in the prior art has a complex structure, easily causes the overall chip area to be too large, and is not suitable for a NOR flash read system with a large number of read unit circuits.
[0007] The present disclosure provides a clamping circuit suitable for a NOR flash read system, comprising a read reference generation module and a plurality of read unit modules; the read reference generation module is used to provide a global reference voltage signal for each of the plurality of read unit modules;
[0008] The read reference generation module includes a first transistor and a second transistor, the drain of the first transistor is electrically connected to the drain of the second transistor, the gate of the first transistor is electrically connected to the reference voltage signal, and the gate and drain of the second transistor are short-circuited; the first transistor is used to convert the reference voltage signal into a reference current signal;
[0009] The read unit module includes a third transistor, a fourth transistor and a clamp transistor, the drain of the third transistor and the drain of the fourth transistor are both electrically connected to the gate of the clamp transistor, and the gate of the third transistor is electrically connected to the source of the clamp transistor;
[0010] The gate of the second transistor is electrically connected to the gate of the fourth transistor. The second transistor and the fourth transistor form a current mirror. The fourth transistor is used to mirror-copy the reference current signal received by the second transistor.
[0011] Optionally, the first transistor and the third transistor are of the same type, the ratio of the width to length ratio of the second transistor constituting the current mirror to the width to length ratio of the fourth transistor is A, and the ratio of the width to length ratio of the first transistor to the width to length ratio of the third transistor is A.
[0012] Further optionally, the second transistor and the first transistor are of different types.
[0013] Further optionally, the clamping transistor is an NMOS transistor, the first transistor is one of the NMOS transistor and the PMOS transistor, and the second transistor is the other of the NMOS transistor and the PMOS transistor.
[0014] Optionally, the clamping transistor is an NMOS transistor; the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the third transistor is an NMOS transistor, and the fourth transistor is a PMOS transistor;
[0015] The source of the first transistor and the source of the third transistor are both grounded, and the source of the second transistor and the source of the fourth transistor are both connected to the power supply terminal.
[0016] Optionally, the clamping transistor is an NMOS transistor; the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, the third transistor is a PMOS transistor, and the fourth transistor is an NMOS transistor;
[0017] The source of the first transistor and the source of the third transistor are both connected to the power supply terminal, and the source of the second transistor and the source of the fourth transistor are both grounded.
[0018] Based on the same inventive concept, the present disclosure also provides a memory, which includes the above-mentioned clamping circuit applicable to the NOR flash reading system.
[0019] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:
[0020] The clamping circuit suitable for a NOR flash read system provided by the embodiment of the present disclosure has a plurality of read unit modules sharing a read reference generation module, and a global reference voltage signal provided by a read reference generation module can be transmitted to the plurality of read unit modules respectively, so that the reading of a plurality of cell information is completed in one read operation, and the second transistor in the read reference generation module and the fourth transistor in each read unit module form a simple current mirror structure, so that the voltage clamping function of the source signal of the clamping transistor can be realized, thereby ensuring the reliability of the read operation. Not only are the circuit structures of the read reference generation module and the read unit module simple, but also the plurality of read unit modules share a read reference generation module. Therefore, while realizing the voltage clamping function, it is also beneficial to simplify the structure of the entire clamping circuit and reduce the layout space occupied by the clamping circuit in the entire chip system. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0023] Figure 1 This is a schematic diagram of an electrical connection structure of a clamp circuit applicable to a NOR flash read system provided by an embodiment of the present invention;
[0024] Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure between the middle read reference generation module and the read unit module;
[0025] Figure 3 yes Figure 1 Another schematic diagram of the electrical connection structure of the read reference generation module and the read unit module. DETAILED DESCRIPTION
[0026] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0028] In the prior art, the read, write and erase operations of flash memory chips require the application of a fixed voltage to each end of the storage unit (cell). In the read operation, it is generally necessary to apply a voltage of about 0.8V to the drain end of the cell. Fluctuations in the drain voltage will cause fluctuations in the current generated by the cell. Therefore, in order to improve the accuracy of the read operation, it is necessary to set a voltage clamping circuit to make the drain voltage of the cell as stable as possible. Common voltage clamping circuits are generally implemented by a reference voltage circuit, a comparator and a feedback circuit. However, in the NOR flash chip read system, the number of read unit circuits is relatively large. For area considerations, the clamping circuit cannot adopt a complex structure, otherwise it is easy to cause the overall area to increase.
[0029] Based on this, the present application provides a clamping circuit suitable for a NOR flash read system, which can realize voltage clamping, improve the reliability of the read operation, and solve the problem that the clamping circuit structure in the prior art is complex, resulting in an overall chip area that is too large and is not suitable for a NOR flash read system with a large number of read unit circuits. The specific embodiment of the clamping circuit suitable for a NOR flash read system proposed in the present application is described in detail as follows.
[0030] Please refer to Figure 1 and Figure 2 , Figure 1 1 is a schematic diagram of an electrical connection structure of a clamp circuit applicable to a NOR flash read system provided by an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure of a read reference generation module and a read unit module in the embodiment, the clamp circuit suitable for a NOR flash read system provided in the embodiment includes a read reference generation module 10 and a plurality of read unit modules 20; the read reference generation module 10 is used to provide a global reference voltage signal VBIAS for the plurality of read unit modules 20 respectively;
[0031] The read reference generation module 10 includes a first transistor M1 and a second transistor M2, wherein the drain of the first transistor M1 and the drain of the second transistor M2 are electrically connected, the gate of the first transistor M1 is electrically connected to the reference voltage signal VREF, and the gate and the drain of the second transistor M2 are short-circuited; the first transistor M1 is used to convert the reference voltage signal VREF into a reference current signal IREF;
[0032] The read unit module 20 includes a third transistor M3, a fourth transistor M4 and a clamping transistor M5, the drain of the third transistor M3 and the drain of the fourth transistor M4 are both electrically connected to the gate of the clamping transistor M5, and the gate of the third transistor M3 is electrically connected to the source of the clamping transistor M5;
[0033] The gate of the second transistor M2 is electrically connected to the gate of the fourth transistor M4 . The second transistor M2 and the fourth transistor M4 form a current mirror. The fourth transistor M4 is used for mirroring the reference current signal IREF received by the second transistor M2 .
[0034] Specifically, the clamp circuit provided in this embodiment can be used in a NOR flash reading system, including a read reference generation module 10 and multiple read unit modules 20, and the multiple read unit modules 20 are used to read the storage information of multiple storage cells (cells) of the NOR flash. The read reference generation module 10 can provide a global reference voltage signal (or a reference current signal) for the multiple read unit modules 20. For example, the reference current signal can be a reference current for judging the current size of the storage cell, and for example, the global reference voltage signal can be a bias voltage required in the read unit module 20. Multiple read unit modules 20 in this embodiment share one read reference generation module 10, that is, the global reference voltage signal VBIAS provided by one read reference generation module 10 can be transmitted to multiple read unit modules 20 respectively, so that the reading of multiple cell information can be completed in one read operation, which simplifies the structure of the entire clamp circuit and helps to reduce the layout space occupied by the clamp circuit in the entire chip system.
[0035] The read cell module 20 includes at least a clamping transistor M5, and the read cell module 20 can realize the reading of the cell storage information. The source signal of the clamping transistor M5 can be defined as a DL signal, and the DL signal is electrically connected to the drain of the cell. It can be understood that the source of the clamping transistor M5, that is, the DL signal, can be electrically connected to the drain of the cell through a series of other structures, so that the current of the cell can flow to the clamping transistor M5, and the clamping transistor M5 receives the current signal of the cell.
[0036] It can be understood that the read reference generation module 10 can provide a global reference voltage signal (or reference current signal) for multiple read cell modules 20. For example, the reference current signal can be a reference current for judging the current size of the storage cell, and the read reference current refers to the reference current for judging the current size of the cell. During the operation of the read cell module 20, by comparing the current of the cell with the read reference current signal, if the current of the cell is greater than the read reference current, it can be judged that the storage information of this cell is '1', and if the current of the cell is less than the read reference current, it can be judged that the storage information of this cell is '0', and finally the current signal of the cell is converted into a digital output (0, 1) to complete the read operation. In some other read cell module structures, it may not be directly compared by current, and the current signal of the cell can be converted into a voltage signal through a resistor, and the converted voltage signal is then compared with the read reference voltage. The process of the read operation is not described in detail in this embodiment, and specific reference can be made to the relevant technology for understanding.
[0037] The gate of the clamping transistor M5 in the read unit module 20 generally receives a clamping voltage, and this clamping voltage can be dynamically compensated, so as to ultimately achieve the source signal of the clamping transistor M5, i.e., the DL signal, that is, the voltage signal transmitted to the drain end of the cell remains stable. That is, the clamping effect of the clamping circuit provided in this embodiment is to clamp the source signal of the clamping transistor M5, i.e., the DL signal, that is, the voltage signal electrically connected to the drain end of the cell, to a stable potential, so as to avoid fluctuations in the potential of the drain end of the cell, thereby avoiding fluctuations in the current of the cell.
[0038] The read reference generation module 10 of the present embodiment includes a first transistor M1 and a second transistor M2, the drain of the first transistor M1 and the drain of the second transistor M2 are electrically connected, that is, the first transistor M1 and the second transistor M2 are electrically connected, and the gate of the first transistor M1 is electrically connected to the reference voltage signal VREF. Optionally, the reference voltage signal VREF can be provided by other reference voltage generation circuits, and its voltage value is the target voltage of the source signal of the clamp transistor M5, that is, the DL signal. Therefore, it can be seen that the value of the reference voltage signal VREF provided in the present embodiment can be the clamp voltage value required by the read unit module 20. The gate of the first transistor M1 is electrically connected to the reference voltage signal VREF. When the first transistor M1 is turned on, it is used to convert the reference voltage signal VREF into a reference current signal IREF and transmit it to the second transistor M2 electrically connected thereto. The read unit module 20 includes a third transistor M3, a fourth transistor M4 and a clamping transistor M5. The drain of the third transistor M3 and the drain of the fourth transistor M4 are electrically connected to the gate of the clamping transistor M5 to realize the electrical connection among the third transistor M3, the fourth transistor M4 and the clamping transistor M5. The gate and the drain of the second transistor M2 are short-circuited, and the gate of the second transistor M2 is electrically connected to the gate of the fourth transistor M4. The second transistor M2 and the fourth transistor M4 are arranged in this way to form a current mirror structure. The second transistor M2 and the fourth transistor M4 of the current mirror structure can realize that the fourth transistor M4 mirrors the reference current signal IREF received by the second transistor M2. The gate of the third transistor M3 is electrically connected to the source of the clamping transistor M5, that is, the gate signal of the third transistor M3 is the source signal (DL signal) of the clamping transistor M5. By feeding the reference voltage signal VREF equal to the clamping voltage value required by the read unit module 20 into the gate of the first transistor M1, the first transistor M1 converts the reference voltage signal VREF into a reference current signal IREF and transmits it to the second transistor M2 electrically connected thereto, and the second transistor M2 and the fourth transistor M4 form a current mirror structure, and the fourth transistor M4 mirrors the reference current signal IREF received by the second transistor M2. The third transistor M3 is electrically connected to the fourth transistor M4, and the third transistor M3 also receives the reference current signal IREF, that is, the reference current signal IREF transmitted by the first transistor M1. Therefore, the gate potential of the third transistor M3 is equal to the gate potential of the first transistor M1, and both are the value of the reference voltage signal VREF.The source of the clamp transistor M5 is electrically connected to the gate of the third transistor M3, and the source signal of the clamp transistor M5, that is, the DL signal, is clamped to the reference voltage signal VREF and remains unchanged, thereby clamping the source signal of the clamp transistor M5, that is, the DL signal, that is, the voltage signal electrically connected to the drain of the cell, to a stable potential value of the reference voltage signal VREF, thereby avoiding fluctuations in the potential of the drain of the cell to which the source of the clamp transistor M5 is electrically connected, thereby avoiding fluctuations in the current of the cell, thereby realizing the voltage clamping function of the clamp circuit and ensuring the reliability of the read operation.
[0039] The clamping circuit suitable for the NOR flash read system provided in this embodiment has a plurality of read unit modules 20 sharing a read reference generation module 10, and a global reference voltage signal VBIAS provided by a read reference generation module 10 can be transmitted to the plurality of read unit modules 20 respectively, so that the reading of a plurality of cell information can be completed in one read operation, and the second transistor M2 in the read reference generation module 10 and the fourth transistor M4 in each read unit module 20 form a simple current mirror structure, which can realize the voltage clamping function of the source signal of the clamping transistor M5, that is, the DL signal, and ensure the reliability of the read operation. Not only the circuit structures of the read reference generation module 10 and the read unit module 20 are simple, but also the plurality of read unit modules 20 share a read reference generation module 10, so it is also beneficial to simplify the structure of the entire clamping circuit and reduce the layout space occupied by the clamping circuit in the entire chip system.
[0040] It can be understood that in this embodiment Figure 1 and Figure 2 The clamp circuit is only briefly shown in part. In practice, the clamp circuit is used in the NOR flash reading system. Figure 2 The illustrated read cell module 20 is only a partial circuit structure. For example, the drain of the clamp transistor M5 in the read cell module 20 may have different connections in different SA (sense amplifier) structures. It may be connected to a read reference current to compare the cell current with the reference current, or it may be connected to a current mirror. The cell current is copied by mirroring and then compared with the reference current. Alternatively, it may be connected to a resistor. The cell current signal is converted into a voltage signal through the resistor. The converted voltage signal is then compared with the read reference voltage. Other circuits in the read cell module 20 and their implemented functions are not described in detail in this embodiment. For details, please refer to the NOR flash read system structure in the related art.
[0041] In some optional embodiments, please continue to refer to Figure 1 and Figure 2In this embodiment, the first transistor M1 and the third transistor M3 are of the same type, the ratio of the width-to-length ratio of the second transistor M2 constituting the current mirror to the width-to-length ratio of the fourth transistor M4 is A, and the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is A. It can be understood that the second transistor M2 and the fourth transistor M4 constituting the current mirror are of the same type, and the second transistor M2 and the fourth transistor M4 match, and the first transistor M1 and the third transistor M3 match. The matching of the first transistor M1 and the third transistor M3 can be understood as the first transistor M1 and the third transistor M3 are of the same type, the gate-source voltage is the same or approximately the same, and the threshold voltage has almost no difference. Among them, the gate-source voltage is the voltage difference between the gate and the source of the transistor, and the calculation formula for the current flowing through the transistor is generally: Where W is the width of the transistor channel, L is the length of the transistor channel, V th is the threshold voltage of the transistor in the process, μ is the electron mobility, C OX is the gate oxide capacitance per unit area (for μ and C OX The definition of is not repeated here), so we can get In order to clamp the source signal of the clamping transistor M5, i.e., the DL signal, i.e., the voltage signal electrically connected to the drain terminal of the cell, to the potential value of the stable reference voltage signal VREF, it is necessary to set that if the ratio of the width-to-length ratio of the second transistor M2 constituting the current mirror to the width-to-length ratio of the fourth transistor M4 is A, then the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is A. Because the ratio of the width-to-length ratio of the second transistor M2 constituting the current mirror to the width-to-length ratio of the fourth transistor M4 is A, the ratio of the current flowing through the second transistor M2 to the current flowing through the fourth transistor M4 is A, and the first transistor M1 is electrically connected to the second transistor M2 in series, and the third transistor M3 is electrically connected to the fourth transistor M4 in series, the ratio of the current flowing through the first transistor M1 to the current flowing through the third transistor M3 can also be A. The ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is A. From the above formula of the gate-source voltage Vgs, it can be obtained that the gate-source voltage Vgs of the first transistor M1 is equal to the gate-source voltage Vgs of the third transistor M3, that is, the gate voltage of the first transistor M1, that is, the potential value of the reference voltage signal VREF is copied to the gate of the third transistor M3, and the gate of the third transistor M3 is connected to the source of the clamping transistor M5. Then, the source signal of the clamping transistor M5, that is, the DL signal, is clamped to the stable potential value of the reference voltage signal VREF. Optionally, the second transistor M2 and the first transistor M1 are of different types. The first transistor M1 is one of an NMOS tube or a PMOS tube, and the second transistor M2 is the other of an NMOS tube or a PMOS tube. For example, the clamping transistor is generally an NMOS transistor, the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the third transistor is an NMOS transistor, and the fourth transistor is a PMOS transistor; the source of the first transistor M1 and the source of the third transistor M3 are both connected to the ground GND, and the source of the second transistor M2 and the source of the fourth transistor M4 are both connected to the power supply terminal VDD.
[0042] When the clamping circuit of this embodiment works, the reference voltage signal VREF is applied to the gate of the first transistor M1 of the read reference generation module 10. The source of the first transistor M1 is grounded. The first transistor M1 is an NMOS transistor. The conduction condition of the NMOS transistor is that the difference between its gate potential and source potential, i.e., Vg - Vs > Vthn (Vthn is the turn-on voltage of the NMOS transistor, also called the threshold voltage. There are differences in Vthn for different processes, but they are all positive values. Since the first transistor M1 and the third transistor M3 in this embodiment are matched, the difference in Vthn can be ignored). Therefore, the first transistor M1 conducts, and the first transistor M1 realizes the conversion of the reference voltage signal VREF to the reference current signal IREF. Since the gate and drain of the second transistor M2 are short-circuited, the source of the second transistor M2 is connected to the power supply terminal VDD. The second transistor M2 is a PMOS transistor. The conduction condition of the PMOS transistor is that the difference between its gate potential and source potential, i.e., Vg - Vs < Vthp (Vthp is the turn-on voltage of the PMOS transistor, also called the threshold voltage. There are differences in Vthp for different processes, but they are all negative values. Since the second transistor M2 and the fourth transistor M4 in this embodiment are matched, the difference in Vthp can be ignored). Therefore, the second transistor M2 conducts, and the second transistor M2 connected to the first transistor M1 receives the reference current signal IREF. The second transistor M2 and the fourth transistor M4 form a current mirror. On the basis that the current mirror works ideally (i.e., the replication of the current is based on the ratio of the aspect ratio of the second transistor M2 to the aspect ratio of the fourth transistor M4 being A), the fourth transistor M4 performs a fixed-ratio mirror replication of the reference current signal IREF received by the second transistor M2, that is, the current of the fourth transistor M4 is 1 / A of the reference current signal IREF, that is, the ratio of the current of the fourth transistor M4 to the current of the first transistor M1 is 1 / A. Since the first transistor M1 and the third transistor M3 are matched, the ratio of the aspect ratio of the first transistor M1 to the aspect ratio of the third transistor M3 is also A. Therefore, the gate-source voltage of the third transistor M3 is equal to the gate-source voltage of the first transistor M1, then the gate potential of the third transistor M3 is equal to the gate potential of the first transistor M1, and the gate potential of the third transistor M3 is also the reference voltage signal VREF. At this time, the third transistor M3 realizes the conversion of 1 / A of the reference current signal IREF to the reference voltage signal VREF.The gate of the third transistor M3 is electrically connected to the source (DL signal) of the clamping transistor M5, and then the source signal of the clamping transistor M5, i.e., the DL signal, is clamped to the reference voltage signal VREF and remains unchanged, thereby achieving the goal of clamping the source signal of the clamping transistor M5, i.e., the DL signal, that is, the voltage signal electrically connected to the drain of the cell, to the stable potential value of the reference voltage signal VREF, avoiding fluctuations in the potential of the drain of the cell to which the source of the clamping transistor M5 is electrically connected, and thus avoiding fluctuations in the current of the cell, thereby achieving the voltage clamping function of the clamping circuit and ensuring the reliability of the read operation.
[0043] It should be noted that, in actual implementation, in order to reduce the potential difference between the DL signal and the reference voltage signal VREF, the threshold voltage of the first transistor M1 and the threshold voltage of the third transistor M3 need to be kept consistent as much as possible, and the current mirror needs to work accurately (work in an ideal state). In order to keep the threshold voltage of the first transistor M1 and the threshold voltage of the third transistor M3 as consistent as possible, the first transistor M1 and the third transistor M3 need to be matched; in order to ensure that the current mirror works accurately (works in an ideal state), the second transistor M2 and the fourth transistor M4 need to be matched, or other current mirror structures are used. As a basic topic of integrated circuit design, the matching of devices and other current mirror structures will not be elaborated in depth here.
[0044] In some optional embodiments, please refer to Figure 1 and Figure 3 , Figure 3 yes Figure 1 Another schematic diagram of the electrical connection structure of the read reference generation module and the read unit module. In this embodiment, the first transistor M1 and the third transistor M3 are of the same type, the ratio of the width-to-length ratio of the second transistor M2 constituting the current mirror to the width-to-length ratio of the fourth transistor M4 is A, and the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is A. It can be understood that the second transistor M2 and the fourth transistor M4 constituting the current mirror are of the same type, and the second transistor M2 and the fourth transistor M4 match, and the first transistor M1 and the third transistor M3 match. The matching of the first transistor M1 and the third transistor M3 can be understood as the first transistor M1 and the third transistor M3 are of the same type, the gate-source voltage is the same or approximately the same, and the threshold voltage has almost no difference. Among them, the gate-source voltage is the voltage difference between the gate and the source of the transistor, and the calculation formula for the current flowing through the transistor is generally: Where W is the width of the transistor channel, L is the length of the transistor channel, V th is the threshold voltage of the transistor in the process, μ is the electron mobility, C OX is the gate oxide capacitance per unit area (for μ and C OX The definition of is not repeated here), so we can get In order to clamp the source signal of the clamping transistor M5, i.e., the DL signal, i.e., the voltage signal electrically connected to the drain terminal of the cell, to the potential value of the stable reference voltage signal VREF, it is necessary to set that if the ratio of the width-to-length ratio of the second transistor M2 constituting the current mirror to the width-to-length ratio of the fourth transistor M4 is A, then the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is A. Because the ratio of the width-to-length ratio of the second transistor M2 constituting the current mirror to the width-to-length ratio of the fourth transistor M4 is A, the ratio of the current flowing through the second transistor M2 to the current flowing through the fourth transistor M4 is A, and the first transistor M1 is electrically connected to the second transistor M2 in series, and the third transistor M3 is electrically connected to the fourth transistor M4 in series, the ratio of the current flowing through the first transistor M1 to the current flowing through the third transistor M3 can also be A. The ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is A. From the above formula of the gate-source voltage Vgs, it can be obtained that the gate-source voltage Vgs of the first transistor M1 is equal to the gate-source voltage Vgs of the third transistor M3, that is, the gate voltage of the first transistor M1, that is, the potential value of the reference voltage signal VREF is copied to the gate of the third transistor M3, and the gate of the third transistor M3 is connected to the source of the clamping transistor M5. Then, the source signal of the clamping transistor M5, that is, the DL signal, is clamped to the stable potential value of the reference voltage signal VREF. Optionally, the second transistor M2 and the first transistor M1 are of different types. The first transistor M1 is one of an NMOS tube or a PMOS tube, and the second transistor M2 is the other of an NMOS tube or a PMOS tube. For example, the clamping transistor is generally an NMOS transistor, the first transistor M1 is a PMOS transistor, the second transistor M2 is an NMOS transistor, the third transistor M3 is a PMOS transistor, and the fourth transistor M4 is an NMOS transistor; the source of the first transistor M1 and the source of the third transistor M3 are both connected to the power supply terminal VDD, and the source of the second transistor M2 and the source of the fourth transistor M4 are both connected to the ground GND.
[0045] When the clamping circuit of this embodiment is working, the reference voltage signal VREF is applied to the gate of the first transistor M1 of the read reference generation module 10. The source of the first transistor M1 is connected to the power supply terminal VDD. The first transistor M1 is a PMOS transistor. The conduction condition of the PMOS transistor is that the difference between its gate potential and source potential, i.e., Vg - Vs < Vthp (Vthp is the turn-on voltage of the PMOS transistor, also called the threshold voltage. Vthp varies with different processes, but it is negative. Since the first transistor M1 and the third transistor M3 in this embodiment are matched, the difference in Vthp can be ignored). Therefore, the first transistor M1 is turned on, and the first transistor M1 realizes the conversion of the reference voltage signal VREF to the reference current signal IREF. Since the gate and drain of the second transistor M2 are short-circuited, the source of the second transistor M2 is grounded to GND. The second transistor M2 is an NMOS transistor. The conduction condition of the NMOS transistor is that the difference between its gate potential and source potential, i.e., Vg - Vs > Vthn (Vthn is the turn-on voltage of the NMOS transistor, also called the threshold voltage. Vthn varies with different processes, but it is positive. Since the second transistor M2 and the fourth transistor M4 in this embodiment are matched, the difference in Vthp can be ignored). Therefore, the second transistor M2 is turned on, and the second transistor M2 connected to the first transistor M1 receives the reference current signal IREF. The second transistor M2 and the fourth transistor M4 form a current mirror. On the basis that the current mirror works ideally (i.e., the current replication is based on the ratio of the aspect ratio of the second transistor M2 to the aspect ratio of the fourth transistor M4 being A), the fourth transistor M4 performs a fixed-ratio mirror replication of the reference current signal IREF received by the second transistor M2, that is, the current of the fourth transistor M4 is 1 / A of the reference current signal IREF, that is, the ratio of the current of the fourth transistor M4 to the current of the first transistor M1 is 1 / A. Since the first transistor M1 and the third transistor M3 are matched, the ratio of the aspect ratio of the first transistor M1 to the aspect ratio of the third transistor M3 is also A. Therefore, the gate-source voltage of the third transistor M3 is equal to the gate-source voltage of the first transistor M1, then the gate potential of the third transistor M3 is equal to the gate potential of the first transistor M1, and the gate potential of the third transistor M3 is also the reference voltage signal VREF. At this time, the third transistor M3 realizes the conversion of 1 / A of the reference current signal IREF to the reference voltage signal VREF.The gate of the third transistor M3 is electrically connected to the source (DL signal) of the clamping transistor M5, and then the source signal of the clamping transistor M5, i.e., the DL signal, is clamped to the reference voltage signal VREF and remains unchanged, thereby achieving the goal of clamping the source signal of the clamping transistor M5, i.e., the DL signal, that is, the voltage signal electrically connected to the drain of the cell, to the stable potential value of the reference voltage signal VREF, avoiding fluctuations in the potential of the drain of the cell to which the source of the clamping transistor M5 is electrically connected, and thus avoiding fluctuations in the current of the cell, thereby achieving the voltage clamping function of the clamping circuit and ensuring the reliability of the read operation.
[0046] In some optional embodiments, the disclosed embodiments further provide a memory, which includes the clamp circuit applicable to the NOR flash read system of any of the above embodiments. The memory provided by this embodiment has the beneficial effects of the clamp circuit applicable to the NOR flash read system provided by the embodiment of the present invention. For details, reference may be made to the specific description of the clamp circuit applicable to the NOR flash read system in the above embodiments, which will not be repeated in this embodiment.
[0047] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0048] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A clamping circuit suitable for a NOR flash read system, characterized in that: It includes a read reference generation module and a plurality of read unit modules; the read reference generation module is used to provide a global reference voltage signal to the plurality of read unit modules respectively; The read reference generation module comprises a first transistor and a second transistor, the drain of the first transistor is electrically connected to the drain of the second transistor, the gate of the first transistor is electrically connected to a reference voltage signal, and the gate and drain of the second transistor are short-circuited; the first transistor is used to convert the reference voltage signal into a reference current signal; The read unit module includes a third transistor, a fourth transistor and a clamp transistor, the drain of the third transistor and the drain of the fourth transistor are both electrically connected to the gate of the clamp transistor, and the gate of the third transistor is electrically connected to the source of the clamp transistor; The gate of the second transistor is electrically connected to the gate of the fourth transistor, the second transistor and the fourth transistor form a current mirror, and the fourth transistor is used to mirror-copy the reference current signal received by the second transistor.
2. The clamping circuit suitable for a NOR flash read system according to claim 1, characterized in that: The first transistor and the third transistor are of the same type, the ratio of the width-to-length ratio of the second transistor constituting the current mirror to the width-to-length ratio of the fourth transistor is A, and the ratio of the width-to-length ratio of the first transistor to the width-to-length ratio of the third transistor is A.
3. The clamping circuit suitable for a NOR flash read system according to claim 2, characterized in that: The second transistor and the first transistor are of different types.
4. The clamping circuit suitable for a NOR flash read system according to claim 3, characterized in that: The clamp transistor is an NMOS transistor, the first transistor is one of an NMOS transistor and a PMOS transistor, and the second transistor is the other of the NMOS transistor and the PMOS transistor.
5. The clamping circuit suitable for a NOR flash read system according to claim 2, characterized in that: The clamping transistor is an NMOS tube; The first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the third transistor is an NMOS transistor, and the fourth transistor is a PMOS transistor; The source of the first transistor and the source of the third transistor are both grounded, and the source of the second transistor and the source of the fourth transistor are both connected to a power supply terminal.
6. The clamping circuit suitable for a NOR flash read system according to claim 2, characterized in that: The clamping transistor is an NMOS tube; The first transistor is a PMOS transistor, the second transistor is an NMOS transistor, the third transistor is a PMOS transistor, and the fourth transistor is an NMOS transistor; The source of the first transistor and the source of the third transistor are both connected to a power supply terminal, and the source of the second transistor and the source of the fourth transistor are both grounded.
7. A memory, characterized in that: The invention comprises a clamping circuit applicable to a NOR flash reading system as described in any one of claims 1 to 6.