Flash wear balancing method based on dual-storage chip data acquisition system

Abstract

The invention discloses a Flash wear balancing method based on a dual-storage chip data acquisition system, which comprises the following steps of: firstly, resetting each module by a master controller, and starting data transmission; reading the data in the address memory after data transmission is started, and determining the operation position of the data in the Flash; after the position is determined, erasing operation is started to be carried out on the Flash; storing the data after erasing is completed; in the storage process, judging whether a Flash tail address is reached or not, if not, continuing data storage, and otherwise, setting the address to the head address and continuing storage; and after storage is completed, the Flash address is refreshed into the address memory. Compared with a traditional balanced wear algorithm, the efficiency is higher, the service time of Flash is prolonged to the maximum extent, and in addition, the method has the advantage of portability so that the method can be directly applied to a related data acquisition system.

Description

Technical Field

[0001] The invention belongs to the technical field of data acquisition, and in particular relates to a Flash wear equalization method based on a dual storage chip data acquisition system. Background Art

[0002] In recent years, solid-state drives based on flash memory have gradually occupied an increasingly important position in the storage device market due to their excellent characteristics such as high access speed, low power consumption, non-volatility and shock resistance. Due to different physical structures, flash memory is mainly divided into two categories: NOR Flash and NAND Flash. NOR flash memory has a faster random read speed, supports local code on-chip execution, and is suitable for storing small-capacity code. NAND flash memory has a higher storage capacity and P / E (Program Erase) times, and occupies a mainstream position in the non-volatile large-capacity storage device market.

[0003] Flash memory has the feature of erase before write: when a flash memory page has stored data, the page cannot be written to. The data can only be rewritten to the block after erasing the block where the page is located. However, the number of erasures for each flash memory block is limited (the number of block erases for SLC (Signal-Level CELL) flash memory and MLC (Multi-Level CELL) flash memory is about 100,000 and 10,000 respectively). After the number of erases for a block reaches the maximum limit, the reliability of data access is significantly reduced. The wear leveling mechanism makes all storage blocks in the flash memory used as evenly as possible, avoiding some blocks from reaching the upper limit of the number of erases due to frequent erasures, thereby improving the reliability of data storage and the service life of the solid-state drive.

[0004] EEPROM chips can be repeatedly erased and written, solving the problem that PROM chips can only be written once. EEPROM can be erased without the help of other equipment. It uses electronic signals to modify its content, and the minimum modification unit is Byte. The upper limit of EEPROM reading and writing is 1 million times.

[0005] FRAM uses the ferroelectric effect of ferroelectric crystals to achieve data storage. The ferroelectric effect means that when a certain electric field is applied to a ferroelectric crystal, the central atoms of the crystal move under the action of the electric field and reach a stable state; when the electric field is removed from the crystal, the central atoms will remain in their original positions. This is because the middle layer of the crystal is a high energy level, and the central atoms cannot cross the high energy level to reach another stable position without external energy. Therefore, FRAM does not require voltage to maintain data, nor does it need to be refreshed periodically like DRAM. Since the ferroelectric effect is a polarization characteristic inherent in ferroelectric crystals and has nothing to do with electromagnetic effects, the content of the FRAM memory will not be affected by external conditions such as magnetic field factors, and can be used like ordinary ROM memory. It has non-volatile storage characteristics and the upper limit of FRAM read and write is on the order of 10 billion times.

[0006] Existing wear leveling algorithms or mechanisms can monitor the actual number of erases of each flash memory block and make adjustments to make the erase times between blocks more even. Depending on the triggering conditions, wear leveling mechanisms are mainly divided into two types: dynamic wear leveling and static wear leveling. The dynamic wear leveling algorithm only processes dynamic data that needs to be updated. Its basic idea is to prevent hot data from being written to storage blocks with a large number of erases, that is, to write updated data to blocks with the least number of erases as much as possible. Static wear leveling is to transfer as much cold data as possible to storage blocks that have been erased many times, reduce the wear on these storage blocks, and thus balance the wear of all storage blocks in the flash memory. The wear leveling algorithm also has some disadvantages, such as triggering multiple data migration and block erase operations. Summary of the invention

[0007] The purpose of the present invention is to solve the problems raised in the background technology and propose a new method to realize the balanced wear of Flash. The wear leveling method of this invention makes the erase operation occur evenly on each block. By changing the erase address each time, the reasonable use of Flash is realized to extend its life as much as possible. The design idea is to realize the balanced operation of each area by recording the address of Flash after erasing through the address memory. The address at the end of each data storage is stored in the data memory, and the storage address is loaded into the Flash data controller when the next data transmission starts to realize the erase and write operation of the specified address.

[0008] In order to achieve the purpose of the present invention, the present invention discloses a Flash wear leveling method based on a dual storage chip data acquisition system, comprising the following steps:

[0009] Step 1: The master controller resets each module and starts data transmission;

[0010] Step 2: After the data transmission starts, the data in the address memory is read to determine the operation position of the data in the Flash;

[0011] Step 3: After determining the location, start erasing the Flash;

[0012] Step 4: Store the data after erasing is completed;

[0013] Step 5: During the storage process, determine whether the Flash tail address has been reached. If not, continue to store data. Otherwise, set the address to the first address and continue to store.

[0014] Step 6: After the storage is completed, refresh the Flash address into the address memory.

[0015] Furthermore, in step 2, after the reset is completed, the information of the address memory is first loaded to determine the location of the Flash erase and write; the controller (host) sends a read command to the EEPROM or FRAM (slave) through the bus protocol; after waiting for the slave to respond, the erase address information is read to the address controller; the address controller sends the address information to the data controller to erase the corresponding Flash address.

[0016] Furthermore, in step 3, combined with the Nand Flash erase timing, the Flash is controlled to start the erase operation after the address information is loaded; the erase operation of the Nand Flash follows the accurate instruction and address sequence, and the erasure of any sector inside the Nand Flash is realized through the coordinated action of the command control line CLE and the address control line ALE; in this process, the execution of the erase operation is controlled according to the flag signal line RE output by the Nand Flash. When the Nand Flash detects a falling edge level on the RE pin, it starts to execute the operation corresponding to the CLE and ALE control lines. After the execution is completed, the Nand Flash pulls the RE pin high, and the operation is completed.

[0017] Furthermore, in step 4, when the erase operation is completed, the Flash is controlled to store data; when the chip select line signal CE is pulled low, the Nand Flash is selected, the command control line CLE is pulled high, and the 0x80 instruction is input to the Nand Flash through the IO pin; then, the address control line ALE is pulled high, and the sector address and the write page address are gradually input into the chip, and then the data of the Nand Flash is written; once the data transmission is completed, wait for the R / B signal to be pulled low, input the 0x70 instruction, and the write page operation is completed.

[0018] Furthermore, in step 5, a state machine is set in the address update controller, and when the erase address reaches the end address of the Flash, the erase address is reset to zero and erase starts from the beginning.

[0019] Furthermore, in step 6, after the data storage is completed, the address where the Flash erase and write ends is updated to the address memory; the write timing of the address memory is basically consistent with the read timing, the master sends a write command to the address memory, and the address memory is in a state of waiting to receive data; the address controller starts writing the address information of the Flash to the address memory.

[0020] Furthermore, when data is stored again, the data is stored in the next storage block of the last storage end address according to the address information in the address memory, ensuring that the number of erasing and writing times of each storage block of the Flash is substantially the same during the data storage process.

[0021] Compared with the prior art, the significant progress of the present invention is: 1) the address memory of the present invention interacts with the Flash data memory, and the initial address stored in the address memory is loaded into the Flash controller before the data storage starts. After the data storage ends, the end address is read from the Flash controller and the address is updated to the address memory. This method erases and writes the storage area uniformly, which is more efficient than the traditional wear-leveling algorithm, greatly prolongs the use time of Flash, and in addition, the present invention has the characteristics of portability so that it can be directly applied to the relevant data acquisition system; 2) because the use of the rear storage area is balanced, the design can significantly increase the number of times of use when erasing the data that is less than the Flash capacity in a single storage, and according to the difference in the amount of stored data, the number of storage times can be increased by several times or even more than its theoretical value; 3) the address memory with a longer service life is used to record the Flash address information, so that each data storage can be accurately located at the end of the last storage at the beginning; 4) the design uses the address update controller to realize that when the data is stored to the tail address, the address is reassigned to the head address to start a new round of storage.

[0022] In order to more clearly illustrate the functional characteristics and structural parameters of the present invention, further description is given below in conjunction with the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 This is a principle block diagram of a Flash wear-leveling method based on a dual-storage chip data acquisition system;

[0025] Figure 2 It is a specific operation flow chart of a Flash wear leveling method based on a dual storage chip data acquisition system;

[0026] Figure 3This is the EEPROM single read timing diagram;

[0027] Figure 4 This is the Nand Flash erase operation timing diagram;

[0028] Figure 5 This is the timing diagram of Nand Flash page write operation;

[0029] Figure 6 This is a schematic diagram of the specific implementation of Flash erasing;

[0030] Figure 7 This is a flow chart of wear leveling operation. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0032] Combination Figure 1 , Figure 2 The present invention provides a Flash wear leveling method based on a dual storage chip data acquisition system, comprising the following steps:

[0033] Step 1: The master controller resets each module and starts data transmission;

[0034] Step 2: After the data transmission starts, the data in the address memory is read to determine the operation position of the data in the Flash;

[0035] Step 3: After determining the location, start erasing the Flash;

[0036] Step 4: Store the data after erasing is completed;

[0037] Step 5: During the storage process, determine whether the Flash tail address has been reached. If not, continue to store data. Otherwise, set the address to the first address and continue to store.

[0038] Step 6: After the storage is completed, refresh the Flash address into the address memory.

[0039] Under the control of the controller, this method records the address at the end of each data storage, and erases and writes different areas of the storage to balance the wear on the Flash during the next data storage. The erase, write, and read operations of the Flash are completed through the command control line and the address control line. The reading and writing of the EEPROM can be completed through the I2C protocol, and the reading and writing of the FRAM can be completed through the SPI protocol. It is suitable for realizing the balanced wear of the Flash in the data acquisition system under the control of the main control chip such as FPGA, MCU, DSP, etc.

[0040] In order to balance the number of times the Flash is erased and written, the present invention implements a set of wear-balancing algorithms during the Flash erasing and writing process through a controller. Figure 2 The specific operation process is as follows: first perform the erase operation on sector 0. After the erase is completed, 64 pages of data can be written from the data module (one sector equals 64 pages); then, start erasing the next sector, gradually increase the address, and repeat the above operation. Since the Flash page read operation does not require the page interval to be erased in advance, when the data is written to the Flash, the last stored address is stored in the address memory through the bus protocol.

[0041] The address memory interacts with the Flash data memory. Before data storage begins, the initial address stored in the address memory is loaded into the Flash controller. After data storage ends, the end address is read from the Flash controller and updated to the address memory. This method evenly erases and writes the storage area, which is more efficient than the traditional wear-leveling algorithm and greatly extends the use time of the Flash. In addition, the present invention has the characteristics of portability, so that it can be directly applied to related data acquisition systems.

[0042] Because the use of the back storage area is balanced, the number of times it is used can be significantly increased when erasing and writing data that is less than the Flash capacity at a single storage. According to the difference in the amount of stored data, the number of storage times can be increased several times or even more than its theoretical value. The address memory with a longer service life is used to record the Flash address information, so that each data storage can be accurately located at the end of the last storage. The address update controller is used to reassign the address to the first address to start a new round of storage when the data is stored to the last address.

[0043] Example

[0044] Combination Figure 2The specific operation steps of this design are as follows: first, the master resets each module and starts data transmission; after the data transmission starts, the data in the address memory is read to determine the operation position of the data in the Flash; after the position is determined, the Flash is erased; after the erasing is completed, the data is stored; during the storage process, it is determined whether the Flash tail address is reached, if not, the data storage continues, otherwise the address is set to the first address and the storage continues; after the storage is completed, the Flash address is refreshed to the address memory. In the following description, the present invention is further explained in combination with the accompanying drawings and detailed operation steps.

[0045] Step 1: Combine Figure 3 For the EEPROM read timing, after the reset is completed, the address memory information is first loaded to determine the location of the Flash erase and write. Taking EEPROM reading as an example, the EEPROM data is read through the SCL clock line and SDA data line of the I2C protocol. After the host (controller) sends the word address, the slave (EEPROM) responds correctly and points the internal storage unit address pointer to the unit. Set the read-write control R / W bit to "1", which is the read command, and read the Flash address information from the EEPROM to the address controller. The reading and writing of FRAM address information is similar to the operation process of EEPROM.

[0046] Step 2: Combine Figure 4 This is the Nand Flash erase timing. After the address information is loaded, the Flash starts the erase operation. The Nand Flash erase operation must follow the accurate instruction and address sequence. Through the coordinated action of the command control line (CLE) and the address control line (ALE), any sector inside the Nand Flash can be erased. In this process, the execution of the erase operation is controlled according to the flag signal line RE output by the Nand Flash. When the Nand Flash detects a falling edge level on the RE pin, it starts to execute the operation corresponding to the CLE and ALE control lines. After the execution is completed, the Nand Flash will pull the RE pin high, and the operation is completed.

[0047] Step 3: Combine Figure 5This is the timing of writing a page to Nand Flash. When the erase operation of Flash is completed, it starts to control the data storage operation. When the chip select line signal CE is pulled low, Nand Flash is selected and starts to perform the corresponding operation. At this time, pull up the command control line (CLE) and input the 0x80 instruction to Nand Flash through the IO pin. Then, pull up the address control line (ALE), and gradually input the sector address and write page address into the chip, and then start writing data to Nand Flash. Once the data transmission is completed, wait for the R / B signal to be pulled low, input the 0x70 instruction, and the write page operation is completed.

[0048] Step 4: Combine Figure 6 It is the Flash erase and write process control. During the Flash erase and write process, it is determined whether the storage reaches the Flash tail address. If not, the data storage continues. Otherwise, the address is set to the first address and the storage continues.

[0049] Step 5: After the data storage is completed, the address where the Flash erase and write is completed is updated to the data storage. The EEPROM write timing is basically the same as the read timing. Set the read / write control bit R / W to "0" to write the command, and the EEPROM is in a state of waiting to receive data. The controller starts to write the address information of the Flash to the EEPROM.

[0050] Step 6: Combine Figure 7 To achieve wear balance, when data is stored again, the address information in the address memory is used to implement data storage in the next storage block of the last storage end address, ensuring that the number of erase and write times of each storage block of the Flash is basically the same during the data storage process.

[0051] Specifically, regarding the data acquisition system: the data storage Flash and address memory work under the coordination of the master control; common master control chips of data acquisition systems include FPGA, DSP, and MCU; balanced wear is achieved for the Flash data storage to extend its service life; EEPROM and FRAM can be used as address memory.

[0052] Specifically, regarding data storage: Flash is used in data acquisition systems to store large amounts of data without losing power, and to achieve balanced wear on Flash storage chips; Flash erase control: Flash performs erase operations in sectors. In program design, to ensure the accuracy of data writing, the current sector must be erased before writing; Flash read and write operations: Flash performs read and write operations in pages. Flash read, write, and erase operations must follow accurate instruction and address sequences.

[0053] Specifically, regarding the address memory: the address memory is used to store the address at the end of the Flash into the device, and to load the address information stored in the device before the next data storage begins; the reading and writing of the EEPROM is controlled by the I2C bus, and the I2C bus consists of a data line SDA and a clock line SCL to form a communication line. When SCL is high, the jump of SDA from high to low generates a start signal, and the jump of SDA from low to high generates an end signal. The data transmission of IIC is carried out when SCL is high; the reading and writing of FRAM is controlled by the SPI bus. When the controller needs to communicate with FRAM, the controller will pull down the CS signal to enable FRAM, and then initiate communication. After the communication is completed, the CS signal is pulled high.

[0054] Specifically, regarding the balanced wear of Flash: balanced wear should make the erase operation occur evenly on each Flash block; make data storage occur in the Flash storage block with fewer erase times, reduce the wear of the Flash storage block with more storage times, so as to balance the wear degree of Flash; after each erase and write of Flash data is completed, the Flash memory address is updated to the address memory; the interaction of the address memory and the Flash data memory address data is realized in the data acquisition system. This design does not need to record the number of times each storage area is erased, thereby simplifying the operation;

[0055] Specifically, a state machine is required to be designed in the update controller. When the erase address reaches the end address of the Flash, the erase address is reset to zero and erase starts from the beginning.

[0056] Specifically, each module works together. Under the control of the master, each module should coordinate and cooperate with each other to achieve balanced wear and tear of the Flash.

[0057] Specifically, the types of signals collected in the data acquisition system are various, including but not limited to low-speed or high-speed signals such as explosion shock wave signals, bridge vibration signals, and radar echo signals, which can be stored in non-volatile memory Flash. The position of the Flash erase block is controlled before each data storage, thereby maximizing the use of each storage area and greatly extending its use time.

[0058] Specifically, in programming, to ensure the accuracy of data writing, the current sector must be erased before writing. Flash performs erase operations in sectors and read and write operations in pages, so the Flash controller mainly implements three functions: erase, write page, and read page.

[0059] Specifically, for the address memory used in this experiment, the internal part is a series of sequentially addressed storage units. So when we read and write the storage unit in a device, we must first specify the address of the storage unit, that is, the word address, and then write the content to the address.

[0060] Specifically, the address update controller returns to the first address of the Flash when the Flash is erased to the last address, and ensures the correctness of the stored data when the address jumps.

[0061] Specifically, the main control chip coordinates the work of the address controller and the Flash data controller. At the beginning of the transmission, the address information is transmitted from the address memory to the address controller through the bus protocol, and the address controller then transmits the address information to the Flash data controller to complete the erasure and reading and writing of the specific address. After the data transmission is completed, the address information begins to be stored, and the address information is transmitted from the Flash data controller to the address controller. The address controller updates the address information to the address memory through the bus protocol as the first address of the next transmission.

[0062] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0063] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A Flash wear leveling method based on a dual storage chip data acquisition system, characterized in that: The following steps are involved: Step 1: The master controller resets each module and starts data transmission; Step 2: After the data transmission starts, the data in the address memory is read to determine the operation position of the data in the Flash; Step 3: After determining the location, start erasing the Flash; Step 4: Store the data after erasing is completed; Step 5: During the storage process, determine whether the Flash tail address has been reached. If not, continue to store data. Otherwise, set the address to the first address and continue to store. Step 6: After the storage is completed, refresh the Flash address into the address memory.

2. The Flash wear leveling method based on a dual memory chip data acquisition system according to claim 1, characterized in that: In step 2, after the reset is completed, the information of the address memory is first loaded to determine the location of the Flash erase and write; the controller sends a read command to the EEPROM or FRAM through the bus protocol; After waiting for the slave to respond, the erase address information is read to the address controller; the address controller sends the address information to the data controller to erase the corresponding Flash address.

3. The Flash wear leveling method based on a dual memory chip data acquisition system according to claim 1, characterized in that: In step 3, combined with the Nand Flash erase timing, the Flash is controlled to start the erase operation after the address information is loaded; the Nand Flash erase operation follows the accurate instruction and address sequence, and the erasure of any sector inside the Nand Flash is achieved through the coordinated action of the command control line CLE and the address control line ALE; in this process, the execution of the erase operation is controlled according to the flag signal line RE output by the Nand Flash. When the Nand Flash detects a falling edge level on the RE pin, it starts to execute the operation corresponding to the CLE and ALE control lines. After the execution is completed, the Nand Flash pulls the RE pin high, and the operation is completed.

4. The Flash wear leveling method based on a dual memory chip data acquisition system according to claim 1, characterized in that: In step 4, when the erase operation is completed, the Flash is controlled to store data; when the chip select line signal CE is pulled low, Nand Flash is selected, the command control line CLE is pulled high, and the 0x80 instruction is input to the Nand Flash through the IO pin; then, the address control line ALE is pulled high, and the sector address and write page address are gradually input into the chip, and then the data of Nand Flash is written; once the data transmission is completed, wait for the R / B signal to be pulled low, input the 0x70 instruction, and the write page operation is completed.

5. The Flash wear leveling method based on a dual memory chip data acquisition system according to claim 1, characterized in that: In step 5, a state machine is set in the address update controller. When the erase address reaches the end address of the Flash, the erase address is reset to zero and erase starts from the beginning.

6. The Flash wear leveling method based on a dual memory chip data acquisition system according to claim 1, characterized in that: In step 6, after the data storage is completed, the address where the Flash erase and write ends is updated to the address memory; the write timing of the address memory is basically consistent with the read timing, the master sends a write command to the address memory, and the address memory is in a state of waiting to receive data; the address controller starts writing the address information of the Flash to the address memory.

7. The Flash wear leveling method based on a dual memory chip data acquisition system according to claim 1, characterized in that: When data is stored again, data storage is realized in the next storage block of the last storage end address according to the address information in the address memory.

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