Multilayer ceramic capacitor and method of manufacturing the same

Abstract

The invention provides a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes: a capacitor body including a dielectric layer and an inner electrode layer; and an external electrode disposed on the capacitor body. The inner electrode layer includes nickel (Ni) and cerium (Ce), and includes, along a thickness direction of the inner electrode layer, an upper portion, a middle portion, referred to as a central region, and a lower portion, referred to as a lower region, in which the middle portion is disposed. And at least one of the upper portion and the lower portion having an interface between the inner electrode layer and the dielectric layer is referred to as an interface region, both the central region and the interface region of the inner electrode layer comprising cerium (Ce), and the percentage by weight of cerium (Ce) relative to nickel in the interface region is higher than the percentage by weight of cerium (Ce) relative to nickel in the central region.

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a method for manufacturing the multilayer ceramic capacitor. Background Art

[0002] Ceramic electronic components using ceramic materials include capacitors, inductors, piezoelectric elements, varistors, thermistors, etc. Multilayer ceramic capacitors (MLCCs) among ceramic electronic components can be used in various electronic devices due to their advantages of small size, high capacity, and easy installation.

[0003] For example, multilayer ceramic capacitors can be mounted on substrates of various electronic products (such as imaging devices (such as liquid crystal display devices (LCDs), plasma display device panels (PDPs), organic light emitting diodes (OLEDs), etc.), computers, personal portable terminals, and smart phones), so that the multilayer ceramic capacitors are used as chip capacitors that play a role in charging or discharging them.

[0004] Recently, high-performance and miniaturized multilayer ceramic capacitors are in great demand. In order to achieve high-capacity and small-sized multilayer ceramic capacitors, the dielectric layer and the inner electrode layer must be thin. As the dielectric layer and the inner electrode layer become thinner, reliability problems such as short circuit, DC degradation, breakdown voltage (BDV) degradation, etc. may occur. On the other hand, in the case of using multilayer ceramic capacitors for autonomous vehicles or electric vehicles, the multilayer ceramic capacitors need to be not only thin but also highly reliable. Summary of the invention

[0005] The embodiment provides a multilayer ceramic capacitor in which internal electrode layer connectivity is improved due to a reduction in sintering mismatch between a dielectric layer and an internal electrode layer, and reliability such as a breakdown voltage (BDV) is improved.

[0006] Another embodiment provides a method of manufacturing a multilayer ceramic capacitor.

[0007] A multilayer ceramic capacitor according to an embodiment includes: a capacitor body including a dielectric layer and an inner electrode layer; and an outer electrode disposed on the capacitor body. The inner electrode layer includes nickel (Ni) and cerium (Ce), and along the thickness direction of the inner electrode layer, the inner electrode layer includes an upper portion, a middle portion, and a lower portion, the middle portion is referred to as a central region, and at least one of the upper portion and the lower portion having an interface between the inner electrode layer and the dielectric layer is referred to as an interface region, the central region and the interface region of the inner electrode layer both include cerium (Ce), and the weight percentage of cerium (Ce) in the interface region relative to nickel is higher than the weight percentage of cerium (Ce) in the central region relative to nickel.

[0008] A weight percentage of cerium (Ce) relative to nickel in the interface region of the inner electrode layer may be 1.5 to 3 times a weight percentage of cerium (Ce) relative to nickel in the central region of the inner electrode layer.

[0009] The inner electrode layer may include cerium (Ce) in an amount of 0.01 parts by weight to 5 parts by weight based on 100 parts by weight of nickel (Ni).

[0010] The internal electrode layer may further include at least one of copper (Cu), silver (Ag), palladium (Pd), and gold (Au).

[0011] The dielectric layer may include a barium titanate-based main component including barium (Ba) and titanium (Ti), and cerium (Ce).

[0012] Along the thickness direction of the dielectric layer, the dielectric layer may include an upper portion, a middle portion and a lower portion, the middle portion of the dielectric layer is referred to as a central region, and at least one of the upper portion and the lower portion of the dielectric layer having an interface between the dielectric layer and the internal electrode layer is referred to as an interface region, and the interface region of the dielectric layer may include cerium (Ce).

[0013] The interface region of the dielectric layer may include cerium (Ce) in an amount of 0.05 parts by mole to 1 parts by mole based on 100 parts by mole of barium (Ba) in the interface region of the dielectric layer.

[0014] The interface region of the dielectric layer may include a region from the interface between the dielectric layer and the internal electrode layer to a depth of 10 nm to 100 nm, and may include cerium (Ce) in an amount of 0.05 to 1 mol parts based on 100 mol parts of barium (Ba).

[0015] The interface region of the dielectric layer may include a plurality of dielectric grains, at least one of the plurality of dielectric grains may have a structure including a core and a shell surrounding at least a portion of the core, and the shell may include cerium (Ce).

[0016] The size D50 of the plurality of dielectric grains may be 50 nm to 250 nm.

[0017] Cerium (Ce) included in the dielectric layer may be a component derived from cerium oxide (CeO 2 ) used to form the internal electrode layer and diffused into the dielectric layer after sintering.

[0018] A method for manufacturing a multilayer ceramic capacitor according to an embodiment includes: preparing a conductive paste by mixing raw materials including nickel (Ni) and cerium dioxide (CeO2); manufacturing a dielectric green sheet using a dielectric slurry, and printing the conductive paste on the surface of the dielectric green sheet to form a conductive paste layer; manufacturing a dielectric green sheet stack by stacking the dielectric green sheets on which the conductive paste layer is formed; manufacturing a capacitor body including a dielectric layer and an inner electrode layer by sintering the dielectric green sheet stack; and forming an outer electrode on the surface of the capacitor body. The inner electrode layer includes nickel (Ni) and cerium (Ce), and along the thickness direction of the inner electrode layer, the inner electrode layer includes an upper portion, a middle portion and a lower portion, the middle portion is referred to as a central region, and at least one of the upper portion and the lower portion having an interface between the inner electrode layer and the dielectric layer is referred to as an interface region, the central region and the interface region of the inner electrode layer both include cerium (Ce), and the weight percentage of cerium (Ce) in the interface region relative to nickel is higher than the weight percentage of cerium (Ce) in the central region relative to nickel.

[0019] Cerium oxide (CeO 2 ) may be mixed with cerium in an amount of 0.01 to 5 parts by weight relative to 100 parts by weight of the nickel (Ni).

[0020] The raw material may further include at least one of copper (Cu), silver (Ag), palladium (Pd), and gold (Au).

[0021] The dielectric slurry may be prepared by mixing a barium titanate-based main component powder and a sub-component powder.

[0022] The sintering may be performed at a temperature of 1000°C to 1400°C.

[0023] The sintering may be performed in a reducing atmosphere.

[0024] The sintering can be carried out at an oxygen partial pressure of 1.0×10 -14 MPa to 1.0×10 -10 MPa atmosphere.

[0025] The dielectric layer may include cerium (Ce), which may be obtained from cerium oxide (CeO 2 ) used to form the internal electrode layer and may be diffused into the dielectric layer after the sintering.

[0026] The subcomponent powder may include at least one of manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), germanium (Ge), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), and vanadium (V).

[0027] According to the multilayer ceramic capacitor of the embodiment, sintering mismatch between the dielectric layer and the internal electrode layer is reduced, thereby improving internal electrode layer connectivity and improving reliability such as breakdown voltage (BDV). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0029] Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor cut along line II'.

[0030] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor cut along line II-II'.

[0031] Figure 4 It is shown Figure 3 Schematic diagram of a portion of the effective area.

[0032] Figure 5 This is a scanning electron microscope (SEM)-energy dispersive spectroscopy (EDS) analysis image of the active area of ​​a multilayer ceramic capacitor.

[0033] Figure 6 is a SEM-EDS analysis image of an active area of ​​the multilayer ceramic capacitor according to Example 1.

[0034] Figure 7 is a thermomechanical analysis (TMA) graph of the inner electrode layer materials according to Example 6 and Comparative Example 1.

[0035] FIG. 8A to FIG. 8E These are scanning electron microscope (SEM) analysis images of the interface region of the dielectric layer according to Example 1, Example 2, Example 4, Example 5, and Example 7, respectively.

[0036] Fig. 9 is a graph showing dielectric constants of dielectric layers according to Example 1, Example 2, Example 4, and Example 5. DETAILED DESCRIPTION

[0037] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings showing embodiments of the present disclosure. In order to clearly describe the present disclosure, parts or portions not related to the description are omitted, and the same or similar constituent elements are represented by the same reference numerals throughout the specification. In addition, in the accompanying drawings, some constituent elements are exaggerated, omitted or schematically shown, and the size of each constituent element does not fully reflect the actual size.

[0038] The accompanying drawings are provided only to allow easy understanding of the embodiments disclosed in this specification and should not be interpreted as limiting the spirit disclosed in this specification, and it should be understood that the present disclosure includes all modifications, equivalents, and substitutes without departing from the scope and spirit of the present disclosure.

[0039] Terms including ordinal numbers such as "first", "second", etc. may be used to describe various constituent elements, but the constituent elements are not limited by these terms. These terms are used only for the purpose of distinguishing one constituent element from another constituent element.

[0040] It should be understood that when an element (such as a layer, film, region, area, or substrate) is referred to as being "on" or "over" another element, the element may be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly" "on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "above..." mean being disposed "on" or "below" an object part, and do not necessarily mean being disposed on the upper side of the object part based on the direction of gravity.

[0041] In the present application, terms such as "include" or "have" are intended to indicate the presence of the features, quantities, steps, operations, constituent elements, parts or combinations thereof described in the specification, and should be understood as not excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, constituent elements, parts or combinations thereof. In addition, unless explicitly described to the contrary, the word "include" and variations such as "include" or "contain" will be understood to imply the stated elements without excluding any other elements.

[0042] Furthermore, throughout the specification, the phrase “on a plane” means observing a target portion from the top, and the phrase “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0043] Throughout the specification, when it is described that a part is “connected” to another part, the part may be “directly connected” to the other part, or may be “connected” to the other part through a third part, or may be physically or electrically connected to the other part, or it may mean that parts represented by different names according to position or function but substantially integrated into one body can be connected to each other.

[0044] In the following, reference will be made to Figures 1 to 4 A multilayer ceramic capacitor according to an embodiment is described.

[0045] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to this embodiment, Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor cut along line I-I', Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor cut along line II-II', and Figure 4 It is shown Figure 3 Schematic diagram of a portion of the effective area.

[0046] Figures 1 to 4 The L-axis direction, W-axis direction, and T-axis direction shown in represent the length direction, width direction, and thickness direction of the capacitor body 110, respectively. Here, the thickness direction (T-axis direction) may be a direction perpendicular to the wide surface (main surface) of the constituent element having a sheet shape. For example, the thickness direction (T-axis direction) may be used as the same concept as the stacking direction of the stacked dielectric layer 111. The length direction (L-axis direction) may be a direction extending parallel to the wide surface (main surface) of the constituent element having a sheet shape and approximately perpendicular to the thickness direction (T-axis direction). For example, the length direction (L-axis direction) may be a direction in which the first external electrode 131 and the second external electrode 132 are opposite to each other. The width direction (W-axis direction) is a direction extending parallel to the wide surface (main surface) of the constituent element having a sheet shape and approximately perpendicular to the thickness direction (T-axis direction) and the length direction (L-axis direction), and the length of the constituent element having a sheet shape in the length direction (L-axis direction) may be greater than the length of the constituent element having a sheet shape in the width direction (W-axis direction).

[0047] Reference Figures 1 to 4 , the multilayer ceramic capacitor 100 according to this embodiment includes a capacitor body 110 and external electrodes 131 and 132 disposed on the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at both ends of the capacitor body 110 opposite to each other in the length direction (L-axis direction).

[0048] For example, the capacitor body 110 may substantially have a hexahedral shape.

[0049] For the convenience of describing the embodiments, two surfaces of the capacitor body 110 that are opposite to each other in the thickness direction (T-axis direction) are defined as a first surface and a second surface, two surfaces of the capacitor body 110 that are connected to the first surface and the second surface and are opposite to each other in the length direction (L-axis direction) are defined as a third surface and a fourth surface, and two surfaces of the capacitor body 110 that are connected to the first surface and the second surface and the third surface and the fourth surface and are opposite to each other in the width direction (W-axis direction) are defined as a fifth surface and a sixth surface.

[0050] For example, the first surface as the lower surface may be a mounting surface. In addition, the first to sixth surfaces may be flat, but the present disclosure is not limited thereto. For example, each of the first to sixth surfaces may be a curved surface having a convex central portion, and the corners of these surfaces as boundaries may be rounded.

[0051] The shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 are not limited to those shown in the drawings of the present disclosure.

[0052] The capacitor body 110 includes a plurality of dielectric layers 111 and a plurality of internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and a plurality of first internal electrode layers 121 and a plurality of second internal electrode layers 122, the first internal electrode layers 121 and the second internal electrode layers 122 are alternately arranged in the thickness direction (T-axis direction), and the dielectric layer 111 is interposed between the first internal electrode layers 121 and the second internal electrode layers 122.

[0053] In this case, the dielectric layers 111 of the capacitor body 110 adjacent to each other may be integrated to such an extent that it is difficult to recognize a boundary therebetween without using a scanning electron microscope (SEM).

[0054] Reference Figure 3 , the capacitor body 110 may include an active area.

[0055] The active region is a portion contributing to forming capacitance of the multilayer ceramic capacitor 100. For example, the active region may be a region where the first and second internal electrode layers 121 and 122 stacked in the thickness direction (T-axis direction) overlap each other.

[0056] In addition, the capacitor body 110 may further include a cover region and a side edge region.

[0057] The cover region may be an edge portion in the thickness direction and may be respectively disposed on the upper and lower surfaces of the active region in the thickness direction (T-axis direction). The cover region may be a single dielectric layer 111 or two or more dielectric layers 111 respectively stacked on the upper and lower surfaces of the active region.

[0058] The side edge regions may be edge portions in the width direction, and may be respectively provided on two side surfaces of the effective region that are opposite to each other in the width direction (W-axis direction). The side edge regions may be formed by stacking dielectric green sheets such that when a conductive paste for an inner electrode layer is applied on the surface of the dielectric green sheet, the conductive paste is applied only on some areas of the surface of the dielectric green sheet to form a conductive paste layer, and the conductive paste is not applied on both sides of the surface of the dielectric green sheet in the width direction, and then firing the stacked dielectric green sheets.

[0059] The cover region and the side edge region serve to prevent damage to the first and second internal electrode layers 121 and 122 due to physical stress and / or chemical stress.

[0060] The first inner electrode layer 121 and the second inner electrode layer 122 may be electrodes having different polarities, the first inner electrode layer 121 and the second inner electrode layer 122 may be alternately arranged to be opposite to each other along the T-axis direction, and the dielectric layer 111 is interposed between the first inner electrode layer 121 and the second inner electrode layer 122, and one end of each of the first inner electrode layer 121 and the second inner electrode layer 122 may be exposed through a corresponding one of the third surface and the fourth surface of the capacitor body 110.

[0061] The first and second internal electrode layers 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.

[0062] Ends of the first and second internal electrode layers 121 and 122 alternately exposed through the third and fourth surfaces of the capacitor body 110 may be electrically connected to the first and second external electrodes 131 and 132 , respectively.

[0063] The internal electrode layers 121 and 122 (ie, the first internal electrode layer 121 and the second internal electrode layer 122 according to the embodiment) include nickel (Ni) and cerium (Ce).

[0064] In order to achieve a thin inner electrode layer, the atomization of the material of the inner electrode layer can be achieved. If the material of the inner electrode layer is atomized to become a nanoparticle level, its melting point tends to decrease as the size of the particles becomes smaller. The phenomenon of melting point reduction leads to a decrease in the temperature at the beginning of thermal shrinkage, and the degree of melting point reduction of the metal is much greater than the degree of melting point reduction of the ceramic material. Therefore, in the firing process of the multilayer ceramic capacitor, the sintering mismatch between the inner electrode layer and the dielectric layer is further increased. For example, when the sintering mismatch is maximized, there may be a difference of 500°C or more between the sintering temperature of the dielectric layer and the sintering temperature of the inner electrode layer. When the inner electrode layer starts to sinter before the dielectric layer, the nearby particles gather, spheroidization occurs, rupture occurs first in the thin printed part, and connectivity deteriorates. In order to solve this problem, a method of adding a common material (i.e., the same material as the material of the dielectric layer) to the inner electrode layer is used. However, if the amount of the common material added increases, the film density of the inner electrode layer may decrease, and the common material may extrude toward the dielectric layer, resulting in the side effect of thickening the dielectric layer.

[0065] According to the present embodiment, cerium (Ce) having better thermal stability and a higher melting point than barium titanate (BaTiO3) used as a common material can be applied to the internal electrode layers 121 and 122 to solve the problem of deterioration of the connectivity of the internal electrode layers due to sintering mismatch. For reference, the melting point of nickel oxide (NiO) is 1455°C, the melting point of barium titanate (BaTiO3) is 1625°C, and the melting point of cerium dioxide (CeO2) is 2400°C. Cerium dioxide (CeO2) is a non-reducing material and has a large sintering delay effect.

[0066] In other words, the inner electrode layers 121 and 122 according to the embodiment may include cerium (Ce) to increase the thermal stability of the inner electrode layers during high temperature firing. Therefore, the sintering mismatch between the dielectric layer and the inner electrode layer can be reduced, thereby improving the connectivity of the inner electrode layer. In addition, cerium (Ce) can be diffused into the dielectric layer 111 during firing, thereby improving the degradation caused by oxygen vacancies. Therefore, reliability such as breakdown voltage (BDV) can be improved.

[0067] Specifically, in each of the inner electrode layers 121 and 122, cerium (Ce) may be included in an amount of 0.01 to 5 parts by weight based on 100 parts by weight of nickel (Ni). For example, in each of the inner electrode layers 121 and 122, cerium (Ce) may be included in an amount of 0.05 to 3 parts by weight (e.g., an amount of 0.08 to 2.5 parts by weight) based on 100 parts by weight of nickel (Ni). When cerium (Ce) within the content range is included in each of the inner electrode layers 121 and 122, thermal stability of the inner electrode layer may be increased during high temperature firing, thereby reducing sintering mismatch between the dielectric layer and the inner electrode layer, and cerium (Ce) may be diffused into the dielectric layer during firing, thereby improving degradation due to oxygen vacancies.

[0068] A sintering mismatch between a dielectric layer and an internal electrode layer may be reduced, thereby improving connectivity of the internal electrode layer, and reliability such as a breakdown voltage (BDV) may be improved.

[0069] Cerium (Ce) may exist in both the central region and the interface region of each of the internal electrode layers 121 and 122. Here, the central region and the interface region may refer to Figure 4 That is, when each of the internal electrode layers 121 and 122 is divided into three parts in the thickness direction to be divided into an upper part, a middle part, and a lower part, the middle part is referred to as a central region A, and at least one of the upper part and the lower part having an interface between the dielectric layer 111 and the internal electrode layers 121 and 122 is referred to as an interface region B.

[0070] Specifically, in each of the internal electrode layers 121 and 122, the content of cerium (Ce) included in the interface region B may be higher than the content of cerium (Ce) included in the central region A. Here, the content of cerium (Ce) in one region of the internal electrode layer may refer to: the weight percentage of cerium (Ce) relative to nickel (Ni) in the region. That is, in each of the internal electrode layers 121 and 122, the weight percentage of cerium (Ce) relative to nickel (Ni) in the interface region B may be higher than the weight percentage of cerium (Ce) relative to nickel (Ni) in the central region A. As an example, the content of cerium (Ce) included in the interface region B may be 1.5 times to 3 times the content of cerium (Ce) included in the central region A, for example, 1.7 times to 2.8 times or 2.0 times to 2.5 times. When the content of cerium (Ce) included in the interface region B is a multiple within the range of the content of cerium (Ce) included in the central region A, the sintering mismatch between the dielectric layer and the internal electrode layer can be reduced, thereby improving the connectivity of the internal electrode layer, and the interface reliability and reliability such as breakdown voltage (BDV) can be improved.

[0071] The content of cerium (Ce) in each of the internal electrode layers 121 and 122 and the cerium (Ce) content ratio of the interface region B relative to the central region A in each of the internal electrode layers 121 and 122 may be measured by a scanning electron microscope (SEM)-energy dispersive spectrometer (EDS).

[0072] Specifically, the multilayer ceramic capacitor 100 can be placed in an epoxy resin mixed liquid (or epoxy resin mixture) and the placed multilayer ceramic capacitor 100 can be cured, and then the surface (WT surface) in the W-axis direction and the T-axis direction of the capacitor body 110 can be polished to the 1 / 2 point in the L-axis direction, and the polished capacitor body can be maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample in which an effective area in which the dielectric layer 111 and the internal electrode layers 121 and 122 overlap each other can be observed.

[0073] Next, the active area of ​​the cross-sectional sample can be measured using a scanning electron microscope (SEM), e.g. Figure 3 The central portion represented by region C in FIG. For example, the scanning electron microscope may be a Verios G4 product from Thermo Fisher Scientific, the measurement conditions may be 10 kV and 0.2 nA, the magnification may be 50 k times, and the first layer, the third layer, the fifth layer, or the tenth layer of each of the dielectric layer 111 and the internal electrode layers 121 and 122 may be measured.

[0074] Subsequently, the content of cerium (Ce) may be analyzed by point EDS analysis in a scanning electron microscope (SEM) image of the measured cross-sectional sample. In the point EDS analysis, one point may be specified in each of the central region A and the interface region B of at least one of the inner electrode layers 121 and 122 and the interface region B' of the dielectric layer 111, or multiple points (e.g., three points, five points, or ten points) may be specified at intervals of 100nm to 1000nm (e.g., at intervals of 300nm to 700nm), and the content of cerium (Ce) at each point may be measured. Point EDS analysis may obtain the arithmetic mean of the measured values. For example, Figure 5 is an image showing the location of the SEM-EDS analysis for the active area of ​​the multilayer ceramic capacitor, as Figure 5 As shown, the location of the point EDS analysis can be represented by five points. Even if not described in the present disclosure, other methods and / or other tools understood by a person of ordinary skill in the art can also be used. The content of nickel (Ni) and barium (Ba) can be analyzed similarly.

[0075] In addition to nickel (Ni) and cerium (Ce), each of the internal electrode layers 121 and 122 (i.e., each of the first internal electrode layer 121 and the second internal electrode layer 122) may further include a conductive metal. An example of the conductive metal may be at least one of copper (Cu), silver (Ag), palladium (Pd), and gold (Au), for example, an alloy thereof (e.g., Ag-Pd alloy).

[0076] In addition, each of the internal electrode layers 121 and 122 may include dielectric particles having the same composition as the ceramic material included in the dielectric layer 111 .

[0077] Cerium (Ce) included in each of the internal electrode layers 121 and 122 may be an element derived from cerium oxide (CeO2) used to manufacture the internal electrode layers 121 and 122 of the multilayer ceramic capacitor 100. Specifically, each of the internal electrode layers 121 and 122 may be formed using a conductive paste obtained by mixing raw materials including nickel (Ni) and cerium oxide (CeO2). A printing method of the conductive paste may be a screen printing method or a gravure printing method.

[0078] The average thickness of the first inner electrode layer 121 and the second inner electrode layer 122 may be 0.1 μm to 2 μm. In the scanning electron microscope (SEM) image of the cross-sectional sample measured as described above, the center point of the first inner electrode layer 121 or the second inner electrode layer 122 in the width direction (W-axis direction) may be used as a reference point. The average thickness of the first inner electrode layer 121 and the second inner electrode layer 122 may be the arithmetic mean of the thickness of the first inner electrode layer 121 or the second inner electrode layer 122 at ten points spaced apart from the reference point. The interval of the ten points may be adjusted according to the scale of the scanning electron microscope (SEM) image. For example, the interval of the ten points may be 1 μm to 100 μm (e.g., 1 μm to 50 μm or 1 μm to 10 μm). In this case, all ten points must be located within the first inner electrode layer 121 or the second inner electrode layer 122. If all ten points are not located within the first inner electrode layer 121 or the second inner electrode layer 122, the position of the reference point may be changed, or the interval between the ten points may be adjusted.

[0079] The dielectric layer 111 according to an embodiment may include a barium titanate-based main component including barium (Ba) and titanium (Ti), and cerium (Ce).

[0080] The barium titanate-based main component is a dielectric base material, has a high dielectric constant, and contributes to formation of capacitance of the multilayer ceramic capacitor 100 .

[0081] For example, the barium titanate-based main component may include BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3, (Ba,Sr)(Ti,Sn)O3, or a combination thereof.

[0082] The cerium (Ce) included in the dielectric layer 111 may be an element derived from cerium dioxide (CeO2) of the internal electrode layers 121 and 122 used to manufacture the multilayer ceramic capacitor 100. Specifically, during the sintering process used to manufacture the multilayer ceramic capacitor 100, the cerium (Ce) present in the interface region B of each of the internal electrode layers 121 and 122 may be partially diffused into the dielectric layer 111 in contact with the interface region B. Therefore, the cerium (Ce) included in the dielectric layer 111 may be caused by the diffusion of the cerium (Ce) present in the interface region B of each of the internal electrode layers 121 and 122, and the diffusion may improve the degradation caused by oxygen vacancies.

[0083] Cerium (Ce) may be present in the interface region of the dielectric layer 111. Here, the interface region may refer to Figure 4 That is, when the dielectric layer 111 is divided into three parts in the thickness direction to be divided into an upper part, a middle part, and a lower part, the middle part is referred to as a central region A', and at least one of the upper part and the lower part having an interface between the dielectric layer 111 and the internal electrode layers 121 and 122 is referred to as an interface region B'.

[0084] Specifically, in the interface region B' of the dielectric layer 111, cerium (Ce) may be included in an amount of 0.05 to 1 mol parts relative to 100 mol parts of barium (Ba). For example, in the interface region B' of the dielectric layer 111, cerium (Ce) may be included in an amount of 0.1 to 0.8 mol parts relative to 100 mol parts of barium (Ba). When cerium (Ce) within this content range is included in the interface region B' of the dielectric layer 111, due to the diffusion of cerium (Ce) in each of the internal electrode layers 121 and 122 (specifically, cerium (Ce) present in the interface region B of each of the internal electrode layers 121 and 122), degradation due to oxygen vacancies may be improved. Therefore, reliability such as breakdown voltage (BDV) may be improved.

[0085] For example, in the interface region B' of the dielectric layer 111, in a region B" having a depth of 10 nm to 100 nm (e.g., 30 nm to 70 nm) from the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 (i.e., a distance from the interface), cerium (Ce) may be included in an amount of 0.05 mol part to 1 mol part (e.g., 0.1 mol part to 0.8 mol part) relative to 100 mol parts of barium (Ba). If the region B" of the dielectric layer 111 includes cerium (Ce) within the content range, degradation due to oxygen vacancies may be improved due to diffusion of cerium (Ce) present in the interface region B of each of the internal electrode layers 121 and 122. Therefore, reliability such as breakdown voltage (BDV) may be improved.

[0086] The content of cerium (Ce) in the dielectric layer 111 can be measured by a scanning electron microscope (SEM)-energy dispersive spectrometer (EDS). Specifically, in the scanning electron microscope (SEM) image of the cross-sectional sample measured as described above, the content of cerium (Ce) can be analyzed by point EDS analysis. In the point EDS analysis, one point can be specified in the interface region B' of the dielectric layer 111 or three points, five points, or ten points can be specified at intervals of 100nm to 1000nm (for example, at intervals of 300nm to 700nm), and the content of cerium (Ce) at each point can be measured. The point EDS analysis can obtain the arithmetic mean of the measured values.

[0087] The dielectric layer 111 may further include a secondary component. For example, the secondary component may include at least one of manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), germanium (Ge), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), and vanadium (V).

[0088] The interface region B' of the dielectric layer 111 according to the embodiment may include a plurality of dielectric grains. The dielectric grains may include a barium titanate-based main component and cerium (Ce), and may selectively include a subsidiary component.

[0089] At least one of the plurality of dielectric grains may have a core-shell structure including a core and a shell surrounding at least a portion of the core. Each of the core and the shell may include a barium titanate-based main component and cerium (Ce), and may selectively include a subsidiary component.

[0090] Specifically, according to an embodiment, the shell may include cerium (Ce). Here, cerium (Ce) may be caused by diffusion of cerium (Ce) present in each of the inner electrode layers 121 and 122, and cerium (Ce) may serve as a donor of the dielectric matrix material so that the dielectric layer 111 may be replaced by Ba at the A site of the dielectric. 2+ And a shell is formed to increase the dielectric constant and enhance reliability.

[0091] In addition, by including cerium (Ce) in each of the internal electrode layers 121 and 122, the size of the dielectric grains present in the interface region B' of the dielectric layer 111 in contact with the internal electrode layers 121 and 122 can be increased. Specifically, the size D50 of the dielectric grains can be 50nm to 250nm (for example, 70nm to 230nm). If the size D50 of the dielectric grains is within this range, the dielectric constant and reliability can be improved. The size D50 of the dielectric grains can be calculated as follows: in a scanning electron microscope image of the interface region of the dielectric layer in the central portion of the effective area of ​​the cross-sectional sample, the maximum major axis of at least 100 dielectric grains is measured to create a size distribution cumulative curve. D50 is the size at 50% of the size distribution cumulative curve.

[0092] The average thickness (average length in the T-axis direction) of the dielectric layer 111 may be 2.0 μm to 8.0 μm (eg, 2.4 μm to 7.8 μm). If the average thickness of the dielectric layer 111 is within this range, the reliability of the multilayer ceramic capacitor is excellent.

[0093] In the scanning electron microscope (SEM) image of the cross-sectional sample measured as described above, the center point of the dielectric layer 111 in the width direction (W-axis direction) can be used as a reference point. The average thickness of the dielectric layer 111 can be the arithmetic mean of the thickness of the dielectric layer 111 at ten points spaced apart from the reference point. The interval between the ten points can be adjusted according to the scale of the scanning electron microscope (SEM) image. For example, the interval between the ten points can be 1 μm to 100 μm (e.g., 1 μm to 50 μm or 1 μm to 10 μm). In this case, all ten points must be located within the dielectric layer 111. If all ten points are not located within the dielectric layer 111, the position of the reference point can be changed, or the interval between the ten points can be adjusted.

[0094] The first and second external electrodes 131 and 132 may be supplied with voltages of different polarities and may be electrically connected to exposed portions of the first and second internal electrode layers 121 and 122 , respectively.

[0095] If a predetermined voltage is applied to the first and second external electrodes 131 and 132, charges are accumulated between the first and second internal electrode layers 121 and 122 facing each other. In this case, the capacitance of the multilayer ceramic capacitor 100 is proportional to the overlapping area of ​​the first and second internal electrode layers 121 and 122 overlapping each other in the T-axis direction in the active region.

[0096] The first external electrode 131 may include a first connecting portion and a first band portion, the first connecting portion is arranged on the third surface of the capacitor body 110 to be connected to the first internal electrode layer 121, and the first band portion is arranged at the corner where the third surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface of the capacitor body 110, and the second external electrode 132 may include a second connecting portion and a second band portion, the second connecting portion is arranged on the fourth surface of the capacitor body 110 to be connected to the second internal electrode layer 122, and the second band portion is arranged at the corner where the fourth surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface of the capacitor body 110.

[0097] The first band portion may extend from the first connection portion to a portion of the first surface and a portion of the second surface and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110, and the second band portion may extend from the second connection portion to a portion of the first surface and a portion of the second surface and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The first band portion and the second band portion may be used to improve the bonding strength of the first external electrode 131 and the second external electrode 132 to the capacitor body 110, respectively.

[0098] Each of the first and second external electrodes 131 and 132 may include a sintered metal layer contacting the capacitor body 110 , a conductive resin layer disposed to cover the sintered metal layer, and a plated layer disposed to cover the conductive resin layer.

[0099] The sintered metal layer may include conductive metal and glass.

[0100] The conductive metal may include at least one of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and lead (Pb) (e.g., alloys thereof), and may include a copper (Cu) alloy. When the conductive metal includes copper, a metal other than copper may be included in an amount of 5 mol parts or less relative to 100 mol parts of copper.

[0101] The glass may include a composition of oxides, for example, the composition may be one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxides, alkali metal oxides, and alkaline earth metal oxides. The transition metal may be selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0102] Alternatively, the conductive resin layer may be formed on the sintered metal layer, for example, may be formed to completely cover the sintered metal layer. On the other hand, the first and second external electrodes 131 and 132 may not include the sintered metal layer, in which case the conductive resin layer may directly contact the capacitor body 110 .

[0103] The conductive resin layer may extend to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the band portion) where the conductive resin layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 may be greater than the length of the region (i.e., the band portion) where the sintered metal layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. In other words, the conductive resin layer may be formed on the sintered metal layer, and may be formed to completely cover the sintered metal layer.

[0104] The conductive resin layer includes resin and conductive metal.

[0105] The resin included in the conductive resin layer is not particularly limited as long as it has bonding properties and impact absorbency and can be mixed with conductive metal powder to form a paste. For example, the resin included in the conductive resin layer may include phenolic resin, acrylic resin, silicone resin, epoxy resin or polyimide resin.

[0106] The conductive metal included in the conductive resin layer serves to electrically connect with the first and second internal electrode layers 121 and 122 or the sintered metal layer.

[0107] The conductive metal included in the conductive resin layer may have a spherical shape, a flake shape, or a combination thereof. In other words, the conductive metal may be made only in a flake shape, may be made only in a spherical shape, or may have a mixed form of a flake shape and a spherical shape.

[0108] Here, the spherical shape may include a shape that is not a perfect sphere, for example, a shape having a ratio of the length of the major axis to the minor axis (major axis / minor axis) of less than or equal to 1.45. The flake shape refers to a flat and elongated shape, and the flake shape is not particularly limited, for example, the flake shape may include a shape having a ratio of the length of the major axis to the minor axis (major axis / minor axis) of greater than or equal to 1.95.

[0109] Each of the first and second external electrodes 131 and 132 may further include a plating layer disposed outside the conductive resin layer.

[0110] The plating layer may include nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb) or their alloys. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or may have a shape in which a nickel (Ni) plating layer and a tin (Sn) plating layer are stacked in sequence, or may have a shape in which a tin (Sn) plating layer, a nickel (Ni) plating layer and a tin (Sn) plating layer are stacked in sequence. In addition, the plating layer may include a plurality of nickel (Ni) plating layers and / or a plurality of tin (Sn) plating layers.

[0111] The plating layer may improve mountability with a substrate, structural reliability, durability to the outside, heat resistance, or equivalent series resistance (ESR) of the multilayer ceramic capacitor 100 .

[0112] Hereinafter, a method of manufacturing the multilayer ceramic capacitor 100 according to an embodiment will be described.

[0113] The multilayer ceramic capacitor 100 according to this embodiment can be manufactured by the following steps: a step of preparing a conductive paste by mixing raw materials including nickel (Ni) and cerium dioxide (CeO2); a step of manufacturing a dielectric green sheet using a dielectric slurry and printing the conductive paste on the surface of the dielectric green sheet to form a conductive paste layer; a step of manufacturing a dielectric green sheet stack by stacking dielectric green sheets having a conductive paste layer formed thereon; a step of manufacturing a capacitor body including a dielectric layer and an inner electrode layer by sintering the dielectric green sheet stack; and a step of forming an outer electrode on the surface of the capacitor body.

[0114] Cerium dioxide (CeO2) may be mixed with 0.01 to 5 parts by weight (e.g., 0.05 to 3 parts by weight or 0.08 to 2.5 parts by weight) of cerium (Ce) relative to 100 parts by weight of nickel (Ni). If cerium dioxide (CeO2) is mixed with cerium (Ce) within this content range, thermal stability of the inner electrode layer may be increased during high temperature firing, thereby reducing sintering mismatch between the dielectric layer and the inner electrode layer, and cerium (Ce) may diffuse into the dielectric layer during firing, thereby improving degradation due to oxygen vacancies.

[0115] The raw material including nickel (Ni) and cerium oxide (CeO2) may further include a conductive metal such as at least one of copper (Cu), silver (Ag), palladium (Pd) and gold (Au) (e.g., an alloy thereof). The conductive metal may be mixed in an amount of 0.01 to 5 parts by weight relative to 100 parts by weight of nickel (Ni).

[0116] The conductive paste may be prepared by mixing raw materials, conductive powder, a binder, and a solvent.

[0117] The dielectric slurry may be prepared by selectively mixing a barium titanate-based main component powder and a subsidiary component powder. The subsidiary component powder may be used in the form of a sol dispersed in an organic solvent.

[0118] The auxiliary component powder may use an oxide of the metal as the above-mentioned auxiliary component. For reference, the cerium (Ce) included in the dielectric layer 111 according to this embodiment is not obtained from the dielectric slurry, but the cerium (Ce) included in the dielectric layer 111 is a component derived from cerium dioxide (CeO2) added during the manufacture of the inner electrode layers 121 and 122, and diffused into the dielectric layer 111 due to firing.

[0119] In addition, the dielectric slurry may be prepared by further mixing additives (eg, a dispersant, a binder, a plasticizer, a lubricant, an antistatic agent, etc.) and a solvent.

[0120] For example, the dispersant may include a phosphate dispersant, a polycarboxylic acid dispersant, or a combination thereof. With respect to a total amount of 100 parts by weight of the barium titanate-based main component powder, a dispersant in an amount of 0.1 to 5 parts by weight (e.g., 0.3 to 3 parts by weight) may be mixed. When the mixed dispersant is within this content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities included in the manufactured dielectric layer can be reduced.

[0121] For example, the binder may be an acrylic resin, a polyvinyl butyl resin, a polyvinyl acetal resin, an ethyl cellulose resin, etc. The binder may be added in an amount of 0.1 to 50 parts by weight (e.g., 3 to 30 parts by weight) relative to 100 parts by weight of the barium titanate-based main component powder in total. When the mixed binder is within this content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities included in the manufactured dielectric layer can be reduced.

[0122] For example, the plasticizer may be a phthalic acid compound (such as dioctyl phthalate, butyl benzyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl)phthalate, di(2-ethylbutyl)phthalate, etc.), an adipic acid compound (such as dihexyl adipate, di(2-ethylhexyl) adipate, etc.), a glycol compound (such as ethylene glycol, diethylene glycol, triethylene glycol, etc.), a glycol ester compound (such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), triethylene glycol di(2-ethylhexanoate), etc.). The plasticizer may be added in an amount of 0.1 to 20 parts by weight (e.g., 1 to 10 parts by weight) relative to 100 parts by weight of the barium titanate-based main component powder in total. If the mixed plasticizer is within this content range, dispersibility of the dielectric slurry is excellent, and the amount of impurities included in the manufactured dielectric layer may be reduced.

[0123] The solvent may be an aqueous solvent (such as water, etc.), an alcohol solvent (such as ethanol, methanol, benzyl alcohol, methoxyethanol, etc.), a glycol solvent (such as ethylene glycol, diethylene glycol, etc.), a ketone solvent (such as acetone, methyl ethyl ketone, methyl isobutyl ketone, cyclohexanone, etc.), an ester solvent (such as butyl acetate, ethyl acetate, carbitol acetate, butyl carbitol acetate, etc.), an ether solvent (such as methyl cellosolve, ethyl cellosolve, butyl ether, tetrahydrofuran, etc.) or an aromatic solvent (such as benzene, toluene, xylene, etc.). For example, considering the solubility or dispersibility of various additives included in the dielectric slurry, the solvent may use an alcohol solvent or an aromatic solvent. With respect to a total amount of 100 parts by weight of the barium titanate-based main component powder, a solvent in an amount of 50 parts by weight to 1000 parts by weight (e.g., 100 parts by weight to 500 parts by weight) may be mixed. If the mixed solvent is within this content range, the components of the dielectric slurry may be fully mixed, and then the solvent may be easily removed.

[0124] The selective mixing of the barium titanate-based main component and the auxiliary component can be performed using a wet ball mill or a stirred mill. When zirconia balls are used in a wet ball mill, a plurality of zirconia balls having a diameter of 0.1 mm to 10 mm can be used for wet mixing for 8 to 48 hours, for example, 10 to 24 hours.

[0125] The prepared dielectric slurry is formed into a dielectric layer after sintering.

[0126] The method for molding the manufactured dielectric slurry into a sheet shape may include a belt molding method such as a doctor blade method, a calendar roll method, etc. For example, the method for molding the manufactured dielectric slurry may use a manifold discharge type roll-on molding coater, and a dielectric green sheet may be obtained by drying the molded body.

[0127] The conductive paste layer is formed by applying the manufactured conductive paste to the surface of the dielectric green sheet in a predetermined pattern using various printing methods such as screen printing or transfer methods. The manufactured conductive paste layer is formed into an internal electrode layer after sintering.

[0128] Next, the dielectric green sheets on which the inner electrode layer patterns are formed are stacked in multiple layers, and then the stacked dielectric green sheets are pressed in the stacking direction, thereby manufacturing a dielectric green sheet stack. In this case, the dielectric green sheets on which the inner electrode layer patterns are formed may be stacked so that the dielectric green sheets are arranged on the upper and lower surfaces of the dielectric green sheet stack in the stacking direction.

[0129] A step of cutting the manufactured dielectric green sheet stack into a predetermined size by dicing or the like may be selectively performed.

[0130] In addition, if necessary, the dielectric green sheet stack may be cured and dried to remove the plasticizer, etc., and after the dielectric green sheet stack is cured and dried, the cured and dried dielectric green sheet stack may be drum polished using a horizontal centrifugal drum machine, etc. During drum polishing, the dielectric green sheet stack may be placed in a drum container together with a medium and a polishing liquid, and a rotational motion or vibration may be applied to the drum container to polish unnecessary portions (such as burrs, etc.) generated during cutting. In addition, after drum polishing, the dielectric green sheet stack may be cleaned with a cleaning solution (such as water, etc.), and the cleaned dielectric green sheet stack may be dried.

[0131] Next, a capacitor body may be manufactured by removing the binder from the dielectric green sheet stack and sintering the dielectric green sheet stack from which the binder has been removed.

[0132] The conditions of the debinding treatment may be appropriately adjusted according to the composition of the dielectric layer or the composition of the inner electrode layer. For example, the temperature rise rate during the debinding treatment may be 5° C. / hour to 300° C. / hour, the carrier temperature during the debinding treatment may be 180° C. to 400° C., and the temperature holding time during the debinding treatment may be 0.5 hour to 24 hours. The atmosphere during the debinding treatment may be air or a reducing atmosphere.

[0133] The sintering of the dielectric green sheet stack may be performed at a temperature of 1000° C. to 1400° C. (eg, 1100° C. to 1350° C.) If sintering is performed at a temperature within this range, sintering mismatch between the dielectric layer and the internal electrode layer may be reduced, thereby improving connectivity of the internal electrode layer.

[0134] In addition, the sintering may be performed for 0.5 to 8 hours (e.g., 1 to 3 hours). In addition, the sintering may be performed in a reducing atmosphere (e.g., an atmosphere of a humidified mixed gas including nitrogen and hydrogen). If the inner electrode layer includes nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the sintering atmosphere may be 1.0×10 -14 MPa to 1.0×10 -10 MPa.

[0135] After sintering, annealing may be performed if necessary. Annealing may be a process for reoxidizing the dielectric layer, and may be performed if the sintering process is performed in a reducing atmosphere. The conditions of the annealing process may be appropriately adjusted according to the composition of the dielectric layer. For example, the temperature during annealing may be 950° C. to 1150° C., the holding time of annealing may be 0 hours to 20 hours, and the temperature rise rate during annealing may be 50° C. / hour to 500° C. / hour. The atmosphere of annealing may be a humidified nitrogen (N2) atmosphere, and the oxygen partial pressure in the annealing atmosphere may be 1.0×10 -9 MPa to 1.0×10 -5 MPa.

[0136] In the binder removal process, the sintering process, or the annealing process, for example, a wetting agent or the like may be used to wet the nitrogen gas or the mixed gas or the like. In this case, the temperature of the wetting agent may be 5° C. to 75° C. The binder removal process, the sintering process, or the annealing process may be performed sequentially, or may be performed independently.

[0137] Optionally, the third surface and the fourth surface of the manufactured capacitor body 110 may be subjected to surface treatment, such as sandblasting, laser irradiation, barrel polishing, etc. By performing the surface treatment, the end of the first inner electrode layer and the end of the second inner electrode layer may be exposed to the third surface and the fourth surface, respectively. Therefore, the electrical bonding between the first outer electrode and the first inner electrode layer and the electrical bonding between the second outer electrode and the second inner electrode layer may become good, and the alloy portion may be easily formed.

[0138] Next, external electrodes are formed on the surface of the manufactured capacitor body 110 .

[0139] For example, a paste for forming a sintered metal layer may be applied to the surface of the manufactured capacitor body 110 , and then the applied capacitor body may be sintered to form the sintered metal layer.

[0140] The paste for forming the sintered metal layer may include conductive metal and glass. The description of conductive metal and glass is the same as above, so the repeated description is omitted. In addition, the paste for forming the sintered metal layer may selectively include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, etc. For example, the binder may use ethyl cellulose, acrylic acid, butyral, etc., and for example, the solvent may use an organic solvent (e.g., terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0141] The method for applying the paste for forming the sintered metal layer onto the surface of the capacitor body 110 may include a dipping method, various printing methods (such as screen printing, etc.), a coating method using a dispenser, etc., a spraying method using a sprayer, etc. The paste for forming the sintered metal layer may be applied to at least the third and fourth surfaces of the capacitor body 110, and may be selectively applied to portions of the first, second, fifth, and / or sixth surfaces at the band portions where each of the first and second external electrodes is formed.

[0142] Thereafter, the capacitor body 110 on which the paste for forming the sintered metal layer is applied is dried, and the dried capacitor body is sintered at a temperature of 700° C. to 1000° C. for 0.1 to 3 hours to form a sintered metal layer.

[0143] Alternatively, a paste for forming a conductive resin layer may be applied to the outer surface of the capacitor body 110 , and then the applied capacitor body may be cured to form the conductive resin layer.

[0144] The paste for forming the conductive resin layer may include conductive metal and resin, and may optionally include non-conductive filler. The description of conductive metal and resin is the same as above, so its repeated description is omitted. In addition, the paste for forming the conductive resin layer may optionally include adhesive, solvent, dispersant, plasticizer, oxide powder, etc. For example, the adhesive may be ethyl cellulose, acrylic acid, butyral, etc., and for example, the solvent may be an organic solvent (for example, terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0145] As an example, the conductive resin layer may be formed by immersing the capacitor body 110 in a paste for forming a conductive resin layer and then curing the immersed capacitor body, the conductive resin layer may be formed by printing the paste for forming a conductive resin layer on the surface of the capacitor body 110 using screen printing, gravure printing, etc., or the conductive resin layer may be formed by coating the paste for forming a conductive resin layer onto the surface of the capacitor body 110 and then curing the coated capacitor body.

[0146] Next, a plating layer is formed on the outside of the conductive resin layer.

[0147] For example, the plated layer may be formed by a plating method, or may be formed by sputtering or electrodeposition.

[0148] Hereinafter, the above implementation examples will be described in more detail through the following examples. However, the following examples are only for illustrative purposes and do not limit the scope of the present disclosure.

[0149] (Manufacture of multilayer ceramic capacitors)

[0150] Example 1

[0151] The conductive paste was prepared by mixing raw materials including nickel (Ni) and cerium oxide (CeO2). In this case, CeO2 was mixed in an amount of 0.1 parts by weight relative to 100 parts by weight of Ni.

[0152] Next, a dielectric slurry is prepared by using barium titanate (BaTiO3) powder. In this case, the dielectric slurry can be prepared by using zirconium oxide (ZrO2) balls as a dispersion medium, adding ethanol (or toluene), a dispersant and a binder, and then mechanically grinding.

[0153] Next, a dielectric green sheet is manufactured using the manufactured dielectric slurry by a roller-molding coater of a manifold discharge type. The manufactured conductive paste is printed on the surface of the dielectric green sheet to form a conductive paste layer. A dielectric green sheet stack (width × length × height = 3.2 mm × 2.5 mm × 2.5 mm) is manufactured by stacking and pressing the dielectric green sheets on which the conductive paste layer is formed. The dielectric green sheet stack is plasticized at a temperature of 400° C. or less in a nitrogen atmosphere, and the dielectric green sheet stack is sintered at a sintering temperature of 1300° C. and a hydrogen (H2) concentration of 1.0% or less to form a capacitor body.

[0154] Subsequently, a multilayer ceramic capacitor is manufactured through processes such as forming external electrodes, plating, and the like.

[0155] Example 2

[0156] A multilayer ceramic capacitor was manufactured in the same method as in Example 1, except that the conductive paste was prepared by mixing CeO 2 in an amount of 0.2 parts by weight of Ce with respect to 100 parts by weight of Ni in Example 2.

[0157] Example 3

[0158] A multilayer ceramic capacitor was manufactured in the same method as in Example 1, except that the conductive paste was prepared by mixing CeO 2 in an amount of 0.3 parts by weight of Ce with respect to 100 parts by weight of Ni in Example 3.

[0159] Example 4

[0160] A multilayer ceramic capacitor was manufactured in the same method as in Example 1, except that the conductive paste was prepared by mixing CeO 2 in an amount of 0.4 parts by weight of Ce with respect to 100 parts by weight of Ni in Example 4.

[0161] Example 5

[0162] A multilayer ceramic capacitor was manufactured in the same method as in Example 1, except that the conductive paste was prepared by mixing CeO 2 in an amount of 0.6 parts by weight of Ce with respect to 100 parts by weight of Ni in Example 5.

[0163] Example 6

[0164] A multilayer ceramic capacitor was manufactured in the same method as in Example 1, except that the conductive paste was prepared by mixing CeO 2 in an amount of 1.0 parts by weight with respect to 100 parts by weight of Ni in Example 6.

[0165] Example 7

[0166] A multilayer ceramic capacitor was manufactured in the same manner as in Example 4, except that the dielectric green sheet stack was sintered at 1320° C. in Example 7.

[0167] Comparative Example 1

[0168] A multilayer ceramic capacitor was manufactured in the same method as in Example 1, except that the conductive paste was prepared without using CeO 2 in Comparative Example 1.

[0169] Evaluation 1: SEM-EDS Analysis of Multilayer Ceramic Capacitors

[0170] The multilayer ceramic capacitor manufactured in Example 1 was analyzed by scanning electron microscope (SEM)-energy dispersive spectroscopy (EDS), and the results are shown in FIG. Figure 6 middle.

[0171] The SEM-EDS analysis was performed using the following method. The multilayer ceramic capacitor manufactured in Example 1 was placed in an epoxy resin mixture (or epoxy resin mixture) and the placed multilayer ceramic capacitor was cured, and then the surface (WT surface) in the W-axis direction and the T-axis direction of the capacitor body was polished to the 1 / 2 point in the L-axis direction, and the polished capacitor body was kept in a vacuum atmosphere chamber, and then a cross-sectional sample in which an effective area where the dielectric layer and the inner electrode layer overlapped each other was obtained. The central part of the effective area of ​​the cross-sectional sample was measured using SEM ( Figure 3The SEM is a Verios G4 product from Thermo Fisher Scientific, the measurement conditions are 10 kV and 0.2 nA, the magnification is 50k times, and at least the fifth layer in the dielectric layer and at least the fifth layer in the inner electrode layer are measured. The content of cerium (Ce) can be confirmed by performing point EDS analysis in the SEM image of the measured cross-sectional sample. In the point EDS analysis, five points are specified at intervals of 500 nm in each of the central region A and the interface region B of the inner electrode layer and the interface region B' of the dielectric layer, and the content of cerium (Ce) at each point is measured. The point EDS analysis obtains the arithmetic mean of the measured values.

[0172] Figure 6 is a SEM-EDS analysis image of an active area of ​​the multilayer ceramic capacitor according to Example 1.

[0173] Reference Figure 6 , it can be confirmed that, in the case of Example 1, cerium (Ce) exists in the inner electrode layer. Specifically, it can be confirmed that cerium (Ce) exists in both the central region and the interface region of the inner electrode layer, and the content of cerium (Ce) included in the interface region is higher than the content of cerium (Ce) included in the central region. In addition, it can be confirmed that cerium (Ce) exists in the dielectric layer, specifically, it can be confirmed that cerium (Ce) exists in the interface region of the dielectric layer. Here, when the inner electrode layer is divided into three parts in the thickness direction so as to be divided into an upper part, a middle part, and a lower part, the middle part is referred to as the central region, and at least one of the upper part and the lower part having an interface between the dielectric layer and the inner electrode layer is referred to as the interface region. In addition, when the dielectric layer is divided into three parts in the thickness direction so as to be divided into an upper part, a middle part, and a lower part, the middle part is referred to as the central region, and at least one of the upper part and the lower part having an interface between the dielectric layer and the inner electrode layer is referred to as the interface region.

[0174] Evaluation 2: Thermomechanical analysis (TMA) of inner electrode layer materials

[0175] In order to confirm the thermal stability of the inner electrode layer of the multilayer ceramic capacitor manufactured in each of Example 6 and Comparative Example 1, a thermomechanical analysis (TMA) was performed on the inner electrode layer material, and the results thereof are shown in FIG. Figure 7 and Table 1 below.

[0176] TMA was performed using the following method. A pelletized sample prepared by pressing a mixed powder of a material for forming an inner electrode layer according to each of Example 6 and Comparative Example 1 was heated using a TMA apparatus (TMA450EM / RH from I-tube Corporation), and thermal shrinkage behavior was measured. The measurement conditions were 3% H2 gas and a heating rate of 10K / min.

[0177] Figure 7 is a thermomechanical analysis (TMA) graph of the inner electrode layer materials according to Example 6 and Comparative Example 1.

[0178] (Table 1)

[0179] Temperature at the initial shrinkage point Temperature at 5% shrinkage Final shrinkage Comparative Example 1 358℃ 452℃ -19.2％ Example 6 410℃ 515℃ -17.2％

[0180] It can be seen that, compared Figure 7 The temperature at which the inner electrode layer material shrinks by 5% in Table 1 is 452° C. for Comparative Example 1 using only Ni, but 515° C. for Example 6 including Ni and Ce, so a shrinkage delay of about 63° C. occurs. Therefore, it can be seen that the inner electrode layer including Ni and Ce according to the embodiment has a thermal shrinkage delay effect.

[0181] Evaluation 3: SEM analysis of dielectric layer

[0182] The dielectric layer of the multilayer ceramic capacitor manufactured in each of Example 1, Example 2, Example 4, Example 5 and Example 7 was analyzed by scanning electron microscope (SEM), and the results thereof are shown in FIG. FIG. 8A to FIG. 8E middle.

[0183] The following method is used for SEM analysis. The multilayer ceramic capacitor manufactured in each of Examples 1, 2, 4, 5 and 7 is placed in an epoxy resin mixture (or epoxy resin mixture) and the placed multilayer ceramic capacitor is cured, and then the surface (WT surface) in the W-axis direction and the T-axis direction of the capacitor body is polished to 1 / 2 point in the L-axis direction, and the polished capacitor body is kept in a vacuum atmosphere chamber, and then a cross-sectional sample of an effective area in which the dielectric layer and the inner electrode layer overlap each other is obtained. The interface area of ​​the dielectric layer is analyzed by SEM in the central part of the effective area of ​​the cross-sectional sample. In this case, when the dielectric layer is divided into three parts in the thickness direction to be divided into an upper part, a middle part and a lower part, at least one of the upper part and the lower part having an interface between the dielectric layer and the inner electrode layer is referred to as an interface area. The SEM is a Verios G4 product from Thermo Fisher Scientific, and the measurement conditions are 10kV and 0.2nA, and the magnification is 50k times.

[0184] FIG. 8A to FIG. 8E These are scanning electron microscope (SEM) analysis images of the interface region of the dielectric layer according to Example 1, Example 2, Example 4, Example 5, and Example 7, respectively.

[0185] Reference FIG. 8A to FIG. 8EIt can be seen that in the case of Examples 1, 2, 4, 5, and 7, since cerium (Ce) is added to the inner electrode layer, cerium (Ce) diffuses into the dielectric layer during firing, so that the size of the dielectric grains existing in the interface region of the dielectric layer in contact with the inner electrode layer increases. In addition, it can be seen that this can improve the dielectric constant and reliability.

[0186] Assessment 4: Reliability of Multilayer Ceramic Capacitors

[0187] The reliability of the following items of the multilayer ceramic capacitors manufactured according to each of Examples 1 to 5 and Comparative Example 1 was measured, and the results are shown in Fig. 9 and Table 2 below.

[0188] Each value shown in Table 2 below corresponds to a ratio relative to each result value of Comparative Example 1.

[0189] (1) Connectivity of the internal electrode layer

[0190] After obtaining a cross-sectional sample using the same method as in Evaluation 3, the central portion of the effective area of ​​the cross-sectional sample was measured using SEM. The SEM was a Verios G4 product from Thermo Fisher Scientific, the measurement conditions were 10 kV and 0.2 nA, the magnification was 10 k times, and about 30 inner electrode layers were measured per photo. After obtaining a total of three photo images, the average value of the connectivity of the inner electrode layer was calculated. The connectivity of each inner electrode layer was calculated by the following formula 1.

[0191] [Formula 1]

[0192] Internal electrode layer connectivity (%) = (total length of the connection parts of the plurality of internal electrode layers excluding the disconnected parts / total length of the plurality of internal electrode layers) × 100

[0193] (2) Dielectric constant of dielectric layer

[0194] The capacitance of the sample sheet, the thickness of the dielectric layer of the sample sheet, and the effective area of ​​the inner electrode layer of the sample sheet are measured, and the dielectric constant of the dielectric layer is calculated based on the measured values.

[0195] Fig. 9 is a graph showing dielectric constants of dielectric layers according to Example 1, Example 2, Example 4, and Example 5. Fig. 9 , it can be seen that in each of Example 1, Example 2, Example 4, and Example 5, the dielectric constant of the dielectric layer is improved.

[0196] (3) Capacitor

[0197] The capacitance (F) was measured under the conditions of a frequency of 1 kHz and a voltage of 0.5 V.

[0198] (4) Breakdown voltage (BDV)

[0199] The maximum voltage (V) at which the sample piece connected to the circuit was destroyed was measured by stepwise increasing the voltage at a voltage increasing speed of 20 V / s.

[0200] (5) Mean time to failure (MTTF)

[0201] The average failure time (hr) of each of the sample pieces was obtained by measuring under the conditions of a temperature of 125° C., a voltage of 9.45 V, and a time of 48 hours.

[0202] (Table 2)

[0203] Internal electrode layer connectivity Dielectric constant capacitance BDV MTTF Comparative Example 1 1 (reference or reference value) 1(reference) 1(reference) 1(reference) 1(reference) Example 1 1.05 1.02 1.02 1.03 1.04 Example 2 1.08 1.05 1.06 1.09 1.15 Example 3 1.13 1.07 1.09 1.14 1.22 Example 4 1.15 1.11 1.05 1.16 1.3 Example 5 1.17 1.08 1.02 1.1 1.12

[0204] Referring to Table 2, it can be seen that, compared with Comparative Example 1 which does not include cerium (Ce), Examples 1 to Examples 5 (in the inner electrode layer, the content of cerium (Ce) included in the interface region (i.e., the weight percentage of cerium (Ce) relative to nickel (Ni)) is higher than the content of cerium (Ce) included in the central region (i.e., the weight percentage of cerium (Ce) relative to nickel (Ni))) have excellent inner electrode layer connectivity, dielectric constant, capacitance and breakdown voltage (BDV) to improve reliability.

[0205] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A multilayer ceramic capacitor comprising: a capacitor body including a dielectric layer and an inner electrode layer; as well as An external electrode is disposed on the capacitor body, Wherein, the inner electrode layer includes nickel and cerium, and along the thickness direction of the inner electrode layer, the inner electrode layer includes an upper part, a middle part and a lower part, the middle part is called a central region, and at least one of the upper part and the lower part having an interface between the inner electrode layer and the dielectric layer is called an interface region, the central region and the interface region of the inner electrode layer both include cerium, and the weight percentage of cerium in the interface region relative to nickel is higher than the weight percentage of cerium in the central region relative to nickel.

2. The multilayer ceramic capacitor according to claim 1, wherein A weight percentage of cerium to nickel in the interface region of the inner electrode layer is 1.5 to 3 times a weight percentage of cerium to nickel in the central region of the inner electrode layer.

3. The multilayer ceramic capacitor according to claim 1, wherein The inner electrode layer includes cerium in an amount of 0.01 parts by weight to 5 parts by weight based on 100 parts by weight of nickel.

4. The multilayer ceramic capacitor according to claim 1, wherein The inner electrode layer further includes at least one of copper, silver, palladium and gold.

5. The multilayer ceramic capacitor according to claim 1, wherein The dielectric layer includes a barium titanate-based main component including barium and titanium, and cerium.

6. The multilayer ceramic capacitor according to claim 5, wherein: Along the thickness direction of the dielectric layer, the dielectric layer includes an upper portion, a middle portion and a lower portion, the middle portion of the dielectric layer is referred to as a central region, and at least one of the upper portion and the lower portion of the dielectric layer having an interface between the dielectric layer and the internal electrode layer is referred to as an interface region, and the interface region of the dielectric layer includes cerium.

7. The multilayer ceramic capacitor according to claim 6, wherein: The interface region of the dielectric layer includes cerium in an amount of 0.05 parts by mol to 1 parts by mol based on 100 parts by mol of barium in the interface region of the dielectric layer.

8. The multilayer ceramic capacitor according to claim 7, wherein: The interface region of the dielectric layer includes a region from the interface between the dielectric layer and the internal electrode layer to a depth of 10 nm to 100 nm, and includes cerium in an amount of 0.05 parts by mole to 1 part by mole based on 100 parts by mole of barium.

9. The multilayer ceramic capacitor according to claim 6, wherein: The interface region of the dielectric layer includes a plurality of dielectric grains, at least one of the plurality of dielectric grains has a structure including a core and a shell surrounding at least a portion of the core, and the shell includes cerium.

10. The multilayer ceramic capacitor according to claim 9, wherein The size D50 of the plurality of dielectric grains is 50 nm to 250 nm.

11. The multilayer ceramic capacitor according to claim 5, wherein: The cerium included in the dielectric layer is a component derived from cerium oxide used to form the internal electrode layer and diffused into the dielectric layer after sintering.

12. A method of manufacturing a multilayer ceramic capacitor, comprising: preparing a conductive paste by mixing raw materials including nickel and cerium oxide; manufacturing a dielectric green sheet using a dielectric slurry, and printing the conductive paste on a surface of the dielectric green sheet to form a conductive paste layer; manufacturing a dielectric green sheet stack by stacking the dielectric green sheets on which the conductive paste layers are formed; manufacturing a capacitor body including a dielectric layer and an internal electrode layer by sintering the dielectric green sheet stack; and forming external electrodes on a surface of the capacitor body, Wherein, the inner electrode layer includes nickel and cerium, and along the thickness direction of the inner electrode layer, the inner electrode layer includes an upper part, a middle part and a lower part, the middle part is called a central region, and at least one of the upper part and the lower part having an interface between the inner electrode layer and the dielectric layer is called an interface region, the central region and the interface region of the inner electrode layer both include cerium, and the weight percentage of cerium in the interface region relative to nickel is higher than the weight percentage of cerium in the central region relative to nickel.

13. The method according to claim 12, wherein: The cerium oxide is mixed with cerium in an amount of 0.01 to 5 parts by weight relative to 100 parts by weight of the nickel.

14. The method according to claim 12, wherein: The raw material further includes at least one of copper, silver, palladium and gold.

15. The method according to claim 12, wherein: The dielectric slurry is prepared by mixing a barium titanate-based main component powder and a sub-component powder.

16. The method according to claim 12, wherein: The sintering is performed at a temperature of 1000°C to 1400°C.

17. The method according to claim 16, wherein: The sintering is performed in a reducing atmosphere.

18. The method according to claim 16, wherein: The sintering was carried out at an oxygen partial pressure of 1.0×10 -14 MPa to 1.0×10 -10 MPa atmosphere.

19. The method according to claim 12, wherein: The dielectric layer includes cerium obtained from cerium oxide used to form the internal electrode layer and diffused into the dielectric layer after the sintering.

20. The method according to claim 15, wherein: The auxiliary component powder includes at least one of manganese, chromium, silicon, aluminum, magnesium, tin, antimony, germanium, gallium, indium, barium, lanthanum, yttrium, actinium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, lutetium, hafnium and vanadium.

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