Doping techniques

Abstract

A method of selectively and conformally doping a semiconductor material is disclosed. Some embodiments utilize a conformal dopant film selectively deposited on a semiconductor material by thermal decomposition. Some embodiments relate to a surface that is doped with non-line of sight (non-line of sight). Some embodiments relate to methods for forming highly doped crystalline semiconductor layers.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 9, 2019, application number 201980053532.2, and name “Doping Technology”. Technical Field

[0002] Embodiments of the present disclosure generally relate to methods of doping semiconductor materials. Some embodiments of the present disclosure relate to methods of selectively doping semiconductor materials relative to oxide materials. Some embodiments of the present disclosure relate to methods for conformally doping semiconductor materials. Background Art

[0003] Control of boron doping is important for p-type contact applications. Control of the process requires management of thickness, surface properties, thermal budget, and etch selectivity.

[0004] Furthermore, existing boron doping methods do not provide a method for conformally doping three-dimensional structures (eg, FINFETs). These methods (eg, implantation) are often limited to line of sight or fail to exhibit sufficient conformality.

[0005] Furthermore, existing boron doping methods do not provide a method for doping only semiconductor materials. Existing techniques often dope semiconductor materials as well as adjacent oxide materials.

[0006] Therefore, there is a need for methods of conformally doping semiconductor materials, particularly methods that are selective to the surface of the semiconductor material. Summary of the invention

[0007] One or more embodiments of the present disclosure are directed to a method of forming an electronic device. The method includes selectively depositing a substantially conformal dopant film on a first surface comprising a semiconductor material, the first surface being opposite to a second surface comprising an oxide material. The electronic device is annealed to drive dopant atoms from the dopant film into the semiconductor material such that the semiconductor material is conformally doped without substantially driving dopant atoms into the oxide material.

[0008] Other embodiments of the present disclosure relate to a method for forming an electronic device. The method includes providing a substrate having a first surface and a second surface, the first surface including a semiconductor material and the second surface including an oxide material. The first surface and the second surface are exposed to a boron precursor at a temperature range of about 700°C to about 800°C to selectively deposit a conformal dopant film by a non-line-of-sight, thermal decomposition process. The dopant film is deposited on the first surface above the second surface. The dopant film includes boron. The electronic device is annealed with a millisecond anneal at a temperature range of about 1150°C to about 1200°C to drive boron atoms from the dopant film into the semiconductor material to conformally dope the semiconductor material without substantially driving dopant atoms into the oxide material.

[0009] Other embodiments of the present disclosure relate to a method of forming an electronic device. The method includes forming an amorphous boron layer on a crystalline semiconductor material. Additional semiconductor material is deposited on the amorphous boron layer. The additional semiconductor material is substantially amorphous. The electronic device is annealed to crystallize the additional semiconductor material to form a boron-doped crystalline semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Thus, the above-described features of the present disclosure may be understood in detail, and a more particular description of the present disclosure, briefly summarized above, may be made by reference to the embodiments, some of which are depicted in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0011] Figure 1 shows an example substrate during processing according to one or more embodiments of the present disclosure;

[0012] Figure 2 illustrates an example substrate during processing according to one or more embodiments of the present disclosure; and

[0013] Figure 3 A system that may be used to process a substrate according to one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0014] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or processing steps set forth in the following description. The present disclosure is capable of other embodiments and can be implemented or carried out in various ways.

[0015] As used in this specification and the appended claims, the term "substrate" refers to a surface or a portion of a surface on which a process acts. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of a substrate. In addition, reference to a deposition on a substrate may mean a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0016] As used herein, "substrate surface" refers to any substrate or material surface formed on a substrate on which film processing is performed in a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, when a film / layer or portion of a film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0017] Embodiments of the present disclosure relate to methods of forming electronic devices with methods including conformal and selective doping processes. Some embodiments of the present disclosure advantageously provide methods of conformally doping semiconductor materials. Some embodiments of the present disclosure advantageously provide methods for doping semiconductor materials preferentially over oxide materials. Some embodiments of the present disclosure advantageously provide methods of doping non-line of sight surfaces.

[0018] As used in this specification and the appended claims, the phrase "selectively depositing a film on one surface over another surface" and the like means that a first amount of film is deposited on a first surface, a second amount of film is deposited on a second surface, wherein the second amount of film is less than the first amount of film, or no film is deposited on the second surface. The term "over" as used in this context does not imply a physical orientation of one surface on top of another surface, but rather means a relationship between the thermodynamic or kinetic properties of a chemical reaction of one surface relative to the other surface. For example, selectively depositing a cobalt film on a copper surface over a dielectric surface means that the cobalt film is deposited on the copper surface, while little or no cobalt film is deposited on the dielectric surface; or that forming a cobalt film on the copper surface is thermodynamically or kinetically favorable relative to forming a cobalt film on a dielectric surface.

[0019] Reference Figure 1 , some embodiments relate to a method 100 of forming an electronic device. Figure 1 A cross-sectional view of an example substrate for processing by method 100 is shown. Substrate 10 includes a first surface 20 comprising semiconductor material 25 and a second surface 30 comprising oxide material 35. In some embodiments, semiconductor material 25 includes or consists essentially of silicon.

[0020] In some embodiments, the semiconductor material 25 is a source / drain extension region of a transistor. In some embodiments, the electronic device comprises a 3D NAND device comprising a plurality of alternating first surfaces 10 and second surfaces 20 .

[0021] As used in this specification and the appended claims, the phrase "consisting essentially of" and the like means that the film or composition in question is greater than or equal to about 95%, 98%, 99%, or 99.5% of the active material. For gaseous compositions (e.g., reactant gases), the phrase "consisting essentially of" refers to the active ingredients of the composition, excluding diluents, carriers, or inert gases.

[0022] In some embodiments, method 100 begins by selectively depositing a substantially conformal dopant film 40 on first surface 20 over second surface 30. As used herein, a "substantially conformal" film refers to a film having a thickness that is substantially the same throughout the thickness (e.g., at the top, middle, and bottom of the sidewalls and at the bottom of the gap). A substantially conformal film varies in thickness by less than or equal to about 10%, 5%, 2%, 1%, or 0.5%.

[0023] In some embodiments, dopant film 40 has a thickness in a range from about 2 to about 10 monolayers.

[0024] In some embodiments, a non-line of sight deposition process is used to selectively deposit the conformal film 40. Thus, in some embodiments, the dopant film 40 is conformally deposited on all exposed first surfaces regardless of their "visibility". Figure 1 As shown, the bottom surfaces of the diamond fins will generally be difficult to dope because these surfaces are "invisible" to line-of-sight processing.

[0025] In some embodiments, selectively depositing dopant film 40 includes a thermal decomposition process. In some embodiments, the thermal decomposition process includes exposing the first and second surfaces to a dopant precursor at a temperature ranging from about 600°C to about 900°C or from about 700°C to about 800°C.

[0026] In some embodiments, the dopant precursor is a boron precursor and the dopant film includes boron. In some embodiments, the boron precursor comprises or consists essentially of borane (BH3), diborane (B2H6), triborane (B3H5, ​​B3H7), tetraborane (B4H6, B4H7), or tetraborane (B4H6, B4H7). 10 ), pentaborane (B5H9, B5H 11 ) or cyclic triborane (B3H6) or cyclic tetraborane (B4H8) or one or more thereof. Other examples of suitable boron precursors include boron halides, such as BCl3, or alkyl-substituted boron compounds having the chemical formula BHxR3-x, wherein each R is an independently selected C1-C6 alkyl group, and x is 0, 1, or 2. Specific examples of alkyl-substituted boron compounds include trimethylboron and triethylboron.

[0027] In some embodiments, the dopant precursor is a phosphorus precursor and the dopant film includes phosphorus. In some embodiments, the phosphorus precursor contains or consists essentially of phosphine (PH3). In some embodiments, the dopant precursor is an arsenic precursor and the dopant film contains arsenic. In some embodiments, the arsenic precursor contains or consists essentially of arsine (AsH3).

[0028] In some embodiments, method 100 continues by annealing the electronic device to drive dopant atoms from dopant film 40 into semiconductor material 25, such that semiconductor material 25 is conformally doped and substantially no dopant atoms are driven into oxide material 35. Figure 1As shown, conformal doping of semiconductor material 25 is shown by the bold lines on the doped surface. As used herein, "substantially free of dopant atoms" means that the surface of the material in question contains less than 5%, 2%, 1%, or 0.5% dopant atoms.

[0029] In some embodiments, annealing the electronic device comprises one or more of spike annealing, laser annealing, rapid thermal annealing, millisecond annealing, or a combination thereof. In some embodiments, annealing occurs at a temperature in the range of about 1000° C. to about 1300° C. or about 1150° C. to about 1200° C.

[0030] In some embodiments, the dopant atoms are driven into the semiconductor material 25 to a depth greater than or equal to about 1 nm, greater than or equal to about 2 nm, or greater than or equal to about 5 nm. In some embodiments, the conformally doped semiconductor material has a dopant concentration greater than or equal to about 1 nm at the surface of the semiconductor material. 20 atoms B / cm 3 , greater than or equal to approximately 2 20 atoms B / cm 3 , or greater than or equal to about 5 20 atoms B / cm 3 .

[0031] Reference Figure 2 , some embodiments relate to a method 200 of forming an electronic device. Figure 2 A cross-sectional view of an example substrate for processing by method 200 is shown. Substrate 210 includes crystalline semiconductor material 220.

[0032] In some embodiments, method 200 begins by forming an amorphous boron layer 230 on a crystalline semiconductor material 220. Forming the amorphous boron layer may be performed by any suitable process, including but not limited to the process for depositing dopant film 40 outlined above.

[0033] In some embodiments, method 200 continues by depositing additional semiconductor material 240 on amorphous boron layer 230. In some embodiments, additional semiconductor material 240 is substantially amorphous.

[0034] In some embodiments, the method 200 continues by annealing the substrate 210 to crystallize the additional semiconductor material 240 and melt the amorphous boron layer 230 and form a boron-doped crystalline semiconductor material 250. In some embodiments, the annealing process includes laser annealing. In some embodiments, the boron-doped crystalline semiconductor material 250 has the same stoichiometry as the crystalline semiconductor material 220. In some embodiments not shown, the method continues by forming a silicide from the boron-doped crystalline semiconductor material 250.

[0035] In some embodiments, the crystalline semiconductor material 220 and the additional semiconductor material are composed of the same material. In some embodiments, the semiconductor material includes silicon. In some embodiments, the semiconductor material includes silicon and germanium.

[0036] Reference Figure 3 , additional embodiments of the present disclosure relate to a processing tool 900 for performing the methods described herein. Figure 3 A system 900 that can be used to process substrates according to one or more embodiments of the present disclosure is shown. The system 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910 having a robot 912 therein. The robot 912 is shown as a single blade robot; however, those skilled in the art will appreciate that other configurations of the robot 912 are also within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers connected to the central transfer station 910.

[0037] At least one pre-cleaning / buffer chamber 920 is connected to the central transfer station 910. The pre-cleaning / buffer chamber 920 may include one or more of a heater, a free radical source, or a plasma source. The pre-cleaning / buffer chamber 920 may be used as a receiving area for a box of a single semiconductor substrate or a wafer for processing. The pre-cleaning / buffer chamber 920 may perform a pre-cleaning process, or may pre-heat a substrate for processing, or may simply serve as a staging area for a processing sequence. In some embodiments, there are two pre-cleaning / buffer chambers 920 connected to the central transfer station 910.

[0038] exist Figure 3 In the illustrated embodiment, the pre-clean chamber 920 can serve as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 can include one or more robots 906 to move substrates from the cassette to the pre-clean / buffer chamber 920. The robot 912 can then move the substrates from the pre-clean / buffer chamber 920 to other chambers in the system 900.

[0039] The first processing chamber 930 may be connected to the central transfer station 910. The first processing chamber 930 may be configured as an anisotropic etching chamber and may be in fluid communication with one or more reactive gas sources to provide one or more reactive gas flows to the first processing chamber 930. The substrate may be moved into and out of the deposition chamber 930 by the robot 912 through the isolation valve 914.

[0040] The processing chamber 940 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 940 includes an isotropic etching chamber and is in fluid communication with one or more reactive gas sources to provide reactive gas flow to the processing chamber 940 to perform an isotropic etching process. The substrate can be moved into and out of the deposition chamber 940 by the robot 912 through the isolation valve 914.

[0041] Process chamber 945 may also be connected to central transfer station 910. In some embodiments, process chamber 945 is of the same type as process chamber 940 and is configured to perform the same process as process chamber 940. Such an arrangement may be useful when the process occurring in process chamber 940 takes longer than the process in process chamber 930.

[0042] In some embodiments, the processing chamber 960 is connected to the central transfer station 910 and is configured to function as a selective epitaxial growth chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

[0043] In some embodiments, the anisotropic etching process occurs in the same process chamber as the isotropic etching process. In such embodiments, process chamber 930 and process chamber 960 can be configured to perform etching processes on two substrates simultaneously, and process chamber 940 and process chamber 945 can be configured to perform a selective epitaxial growth process.

[0044] In some embodiments, each of the process chambers 930, 940, 945, and 960 is configured to perform a different portion of a process recipe. For example, process chamber 930 may be configured to perform an anisotropic etch process, process chamber 940 may be configured to perform an isotropic etch process, process chamber 945 may be configured as a metrology station or to perform a first selective epitaxial growth process, and process chamber 960 may be configured to perform a second selective epitaxial growth process. Those skilled in the art will appreciate that the number and arrangement of the various process chambers on a tool may vary, and Figure 3 The embodiment shown in represents only one possible configuration.

[0045] In some embodiments, the processing system 900 includes one or more metrology stations. For example, the metrology station can be located within the pre-clean / buffer chamber 920, within the central transfer station 910, or within any individual processing chamber. The metrology station can be located anywhere within the system 900 that allows the distance of the groove to be measured without exposing the substrate to an oxidizing environment.

[0046] At least one controller 950 is coupled to one or more of the central transfer station 910, pre-clean / buffer chamber 920, processing chambers 930, 940, 945, or 960. In some embodiments, there is more than one controller 950 connected to each chamber or station, and a main control processor is coupled to each individual processor to control the system 900. The controller 950 can be one of any form of general purpose computer processor, microcontroller, microprocessor, etc., which can be used in an industrial setting for controlling various chambers and sub-processors.

[0047] At least one controller 950 may have a processor 952, a memory 954 coupled to the processor 952, an input / output device 956 coupled to the processor 952, and a support circuit 958 to communicate between different electronic components. The memory 954 may include one or more of a temporary memory (e.g., a random access memory) and a non-temporary memory (e.g., a storage device).

[0048] The processor's memory 954 or computer readable medium may be one or more of readily available memories, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. The memory 954 may retain an instruction set that is operable by the processor 952 to control parameters and components of the system 900. Support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. The circuits may include, for example, caches, power supplies, clock circuits, input / output circuits, subsystems, etc.

[0049] Processing can be typically stored in a memory as a software routine that, when executed by a processor, causes a processing chamber to implement the processing of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown), which is located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be implemented in hardware. Thus, processing may be implemented in software and may be performed using a computer system, implemented in hardware as, for example, an ASIC or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine converts a general-purpose computer into a special-purpose computer (controller) that controls chamber operations so that processing is implemented.

[0050] In some embodiments, the controller 950 has one or more configurations to perform individual processes or sub-processes to implement the method. The controller 950 can be connected to and configured to operate intermediate components to implement the functions of the method. For example, the controller 950 can be connected to and configured to control one or more of a gas valve, an actuator, a motor, a slit valve, a vacuum control, etc.

[0051] The controller 950 of some embodiments has one or more configurations selected from: a configuration for moving substrates on a robot between multiple processing chambers and metrology stations; a configuration for loading and / or unloading substrates from the system; a configuration for depositing dopant films; a configuration for annealing substrates; and a configuration for depositing semiconductor materials.

[0052] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "certain embodiments," "in an embodiment," or "in an embodiment" throughout this specification is not necessarily referenced to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in one or more embodiments in any suitable manner.

[0053] Although the present disclosure has been described with reference to specific embodiments, it will be appreciated by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming an electronic device, the method comprising the steps of: forming an amorphous boron dopant layer on the crystalline semiconductor material; depositing additional semiconductor material on the amorphous boron dopant layer, the additional semiconductor material being substantially amorphous; and The electronic device is annealed at a temperature in a range of about 1000° C. to about 1300° C. to crystallize the additional semiconductor material and melt the amorphous boron dopant layer to drive the boron from the dopant layer into the additional semiconductor material to a depth greater than or equal to about 1 nm to form a boron-doped crystalline semiconductor material.

2. The method of claim 1, wherein the crystalline semiconductor material comprises silicon. The method of claim 2 , wherein the crystalline semiconductor material further comprises germanium. The method of claim 3 , wherein annealing the electronic device comprises laser annealing.

5. The method of claim 4, wherein the boron-doped crystalline semiconductor material has a relative humidity greater than or equal to 1 20 atoms B / cm 3 of dopant concentration.

6. The method of claim 5, wherein forming the amorphous boron dopant layer comprises exposing the crystalline semiconductor material to a boron precursor comprising one or more of borane, diborane, triborane, tetraborane, or pentaborane.

7. The method of claim 6, wherein the boron precursor comprises one or more of cyclic triborane or cyclic tetraborane.

8. The method of claim 6, wherein the boron precursor comprises a haloborane.

9. The method of claim 6, wherein the boron precursor comprises an alkyl borane.

10. The method of claim 5, wherein the boron-doped crystalline semiconductor material has a relative humidity greater than or equal to 2 20 atoms B / cm 3 of dopant concentration.

11. The method of claim 5, wherein the boron-doped crystalline semiconductor material has a carbon content greater than or equal to 5 20 atoms B / cm 3 of dopant concentration.

12. The method of claim 1, wherein the amorphous boron dopant layer has a thickness in a range of about 2 to about 10 monolayers.

13. The method of claim 1, wherein annealing the electronic device occurs at a temperature in a range of about 1150°C to about 1200°C.

14. The method of claim 1, wherein the crystalline semiconductor material is a source / drain extension region of a transistor.

15. The method of claim 4, wherein annealing the electronic device comprises millisecond laser annealing.

16. The method of claim 15, wherein the boron-doped crystalline semiconductor material has a carbon content greater than or equal to 5 20 atoms B / cm 3 of dopant concentration.

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