Method for improving electric leakage of protection circuit

Abstract

The invention discloses a method for improving electric leakage of a protection circuit, which comprises the following steps of: forming an N + doped region in an MOS (Metal Oxide Semiconductor) manufacturing process: in a P well region of a silicon substrate, injecting arsenic ions into the surface layer of the silicon substrate, then performing high-temperature driving-in to form the N + doped region, and forming an oxide layer cover on the surface of the substrate by volume percentage, the high-temperature driving-in atmosphere comprises 10 percent of oxygen. According to the method, high-temperature driving-in is carried out in the oxygen-containing atmosphere, oxide layer covering is formed on the surface of the substrate, the thickness of the barrier layer is effectively increased, ion precipitation is avoided, the breakdown voltage of the device is increased, and the problem of electric leakage of a protection circuit is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving leakage of a protection circuit. Background Art

[0002] The breakdown voltage of a MOS (metal oxide semiconductor) transistor refers to the drain-source voltage when the current flowing through the drain-source is a specific value when the gate is grounded. It is the highest instantaneous voltage value that can be continuously applied to the drain-source before the MOS transistor breaks down. The breakdown voltage is a key parameter to measure the withstand voltage of a MOS transistor. The larger the breakdown voltage, the better the withstand voltage performance of the MOS transistor.

[0003] BCD 0.3μm MOS has leakage when using protection diode circuit. However, there are many reasons for MOS leakage, which may affect the normal operation of the equipment. On the one hand, it may be caused by the quality problem of the MOS itself. On the other hand, temperature may also be an important reason for MOS leakage. Long-term exposure to high temperature environment will cause the internal insulation material of the MOS to deteriorate, thus leaking. In addition, there are problems such as the influence of working voltage. However, from the analysis of MOS tube process, there is ion precipitation during ion implantation, which leads to poor product quality and easy leakage.

[0004] Therefore, there is a need in the prior art to improve the method of protecting circuit leakage. Summary of the invention

[0005] In view of this, the purpose of an embodiment of the present invention is to propose a method for improving leakage of a protection circuit by performing high-temperature driving in an oxygen-containing atmosphere to form an oxide layer covering the surface of the substrate, thereby effectively increasing the thickness of the barrier layer, avoiding ion precipitation, and increasing the breakdown voltage of the device.

[0006] Based on the above purpose, an embodiment of the present invention provides a method for improving leakage of a protection circuit. The steps of forming an N+ doping region in a MOS process are as follows:

[0007] In the P-well region of the silicon substrate, arsenic ions are implanted into the surface of the silicon substrate, and then driven in at high temperature to form an N+ doped region. The high-temperature driven-in atmosphere includes 10% oxygen by volume, forming an oxide layer covering the surface of the substrate.

[0008] In some embodiments, the method further comprises:

[0009] Boron ions are implanted into the surface layer of the silicon substrate, and then driven in at high temperature to form a P+ doped region;

[0010] A photoresist layer is coated on the substrate, exposed and developed to form a pattern, and the photoresist layer and the oxide layer are removed simultaneously.

[0011] In some embodiments, the oxide layer is a silicon dioxide layer.

[0012] In some embodiments, the thickness of the silicon dioxide layer is

[0013] In some embodiments, the arsenic ions are implanted by an ion implanter.

[0014] In some embodiments, the ion implantation energy is 80 keV to 200 keV.

[0015] In some embodiments, a rapid annealing process or a furnace thermal annealing process is used for high temperature drive-in.

[0016] In some embodiments, the photoresist layer is removed by dry etching and the oxide layer is removed simultaneously.

[0017] The present invention has at least the following beneficial technical effects:

[0018] The method of the present invention performs high temperature driving after implanting As+ ions, adds 10% oxygen during high temperature driving, forms an oxide layer on the surface of the substrate, and the thickness of the oxide layer is about Through the above improvements, the oxide layer can block the precipitation of ions, effectively improve the breakdown voltage and prevent leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of an embodiment of a method for improving leakage of a protection circuit provided by the present invention;

[0021] Figure 2 A comparison chart of the results of the WAT electrical test provided by the present invention. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0023] The terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions; the terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0024] In addition, reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0025] Since BCD MOS has leakage when using protection diode circuit, the main reason is that when the semiconductor device is implanted with N+ and then driven in at high temperature, the high temperature causes the ions to be highly active and easily escape from the substrate. The device prepared on this basis has a lower breakdown voltage parameter in the subsequent WAT (wafer acceptance test). The process in the prior art is to inject As+ ions to form an N+ region, and then drive in at high temperature to transfer As+ to the deep layer of the device. However, the high temperature drive-in process also causes the ions to be more active and escape from the substrate, which leads to the narrowing of the diode barrier layer and the reduction of the breakdown voltage. Therefore, the present invention improves the process method of BCDMOS based on the existing problems. Specifically, Figure 1 As shown, the steps of forming the N+ doped region in the MOS process are:

[0026] In the P-well region (PWELL) 2 of the silicon substrate 1, arsenic ions are implanted into the surface of the silicon substrate 1, and then high-temperature driving is performed to form an N+ doped region. The high-temperature driving atmosphere includes 10% oxygen by volume, and an oxide layer 3 is formed on the surface of the substrate.

[0027] Furthermore, the method further comprises: implanting boron ions into the surface layer of the silicon substrate 1, and then performing high temperature driving to form a P+ doping region;

[0028] A photoresist layer is coated on the silicon substrate, exposed and developed to form a pattern, and the photoresist layer and the oxide layer are removed simultaneously.

[0029] Furthermore, the oxide layer is a silicon dioxide layer, which is formed by adding 10% oxygen into the atmosphere during the high temperature drive-in process, and reacting the oxygen with the silicon substrate under high temperature conditions to form a silicon dioxide layer on the surface of the substrate. In some embodiments, the thickness of the oxide layer is Preferably, the thickness of silicon dioxide is The role of the oxide layer is that the high temperature drive-in process also leads to increased ion activity, which causes it to escape from the substrate, resulting in a narrower diode barrier and a smaller breakdown voltage.

[0030] Furthermore, ion implantation is performed by an ion implanter, and boron ions are implanted into the silicon substrate by the ion implanter, and then high temperature driving is performed to form a P+ substrate region. In some embodiments, the energy of the ion implantation is 80keV to 200keV.

[0031] Furthermore, a rapid annealing process or a furnace tube thermal annealing process is used for high temperature driving.

[0032] Furthermore, the photoresist layer is removed by dry etching and the oxide layer is removed simultaneously.

[0033] like Figure 2 The figure shows a comparison of the WAT electrical test of the devices, wherein V2 is a device prepared under a normal process, and V1 is a device prepared by the method of the present invention. It can be seen that the oxide layer introduced by the method of the present invention can block ion precipitation, effectively improve the breakdown voltage, and prevent leakage.

[0034] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0035] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0036] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0037] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for improving leakage protection circuit, characterized in that: The steps for forming the N+ doped region in the MOS process are: In the P-well region of the silicon substrate, arsenic ions are implanted into the surface of the silicon substrate, and then high-temperature driving is performed to form an N+ doped region. The high-temperature driving atmosphere includes 10% oxygen by volume, forming an oxide layer covering the surface of the substrate.

2. The method for improving leakage of a protection circuit according to claim 1, characterized in that: The method also includes: Implanting boron ions into the surface layer of the silicon substrate, and then driving them in at high temperature to form a P+ doped region; A photoresist layer is coated on the substrate, exposed and developed to form a pattern, and the photoresist layer and the oxide layer are removed simultaneously.

3. The method for improving leakage of a protection circuit according to claim 2, characterized in that: The oxide layer is a silicon dioxide layer.

4. The method for improving leakage of a protection circuit according to claim 3, characterized in that: The thickness of the silicon dioxide layer is 5. The method for improving leakage of a protection circuit according to claim 2, characterized in that: The arsenic ions are implanted by an ion implanter.

6. The method for improving leakage of a protection circuit according to claim 5, characterized in that: The ion implantation energy is 80keV to 200keV.

7. The method for improving leakage of a protection circuit according to claim 2, characterized in that: A rapid annealing process or a furnace tube thermal annealing process is used for high temperature driving.

8. The method for improving leakage of a protection circuit according to claim 2, characterized in that: The photoresist layer is removed by dry etching and the oxide layer is removed simultaneously.

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