Board level packaging method and packaging structure

Abstract

The embodiment of the present disclosure provides a board-level packaging method and a packaging structure. The method comprises the following steps: providing a square panel, and fixing a plurality of bridge chips on a first surface of the square panel; forming a plastic packaging layer wrapping the plurality of bridge chips on the first surface of the square panel; forming a plurality of first conductive columns penetrating through the thickness of the plastic packaging layer; forming a first redistribution layer on the surface of the plastic packaging layer and the functional surface of the bridge chip; forming a plurality of second conductive columns penetrating through the thickness of the square panel and electrically connected with the first conductive columns; forming a second redistribution layer electrically connected with the second conductive columns on a second surface of the square panel; forming a power management module on the second redistribution layer, and forming a chip operation module on the first redistribution layer. The large-area square panel is used as a carrier plate, high computing power integration of the board-level packaging structure is realized, and the vertical interconnection of the packaging structure is realized through the first conductive columns and the second conductive columns, so that the transmission path is effectively shortened.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a board-level packaging method and packaging structure. BACKGROUND

[0002] SoW (System on wafer) is to integrate a certain number of computing chips onto a whole wafer as a whole to form a HPC (High Performance Computing) chip system.

[0003] SoW is to reconfigure computing chips into a wafer by using FO technology with a glass carrier as a carrier, to complete interconnection between chips through plastic packaging and re-wiring, to peel off the carrier, and to form the whole SoW system by interconnecting power devices with computing chips in a flip-chip manner on the reconfigured wafer.

[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.

[0005] In view of the above problems, it is necessary to provide a board-level packaging method and packaging structure which are reasonable in design and effective in solving the above problems. SUMMARY

[0006] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a board-level packaging method and packaging structure.

[0007] The embodiment of the present disclosure provides a board-level packaging method, which comprises:

[0008] A square panel is provided, and a plurality of bridge chips are fixed to a first surface of the square panel;

[0009] A plastic packaging layer wrapping the plurality of bridge chips is formed on the first surface of the square panel;

[0010] A plurality of first conductive columns penetrating the thickness of the plastic packaging layer are formed;

[0011] A first re-wiring layer is formed on the surface of the plastic packaging layer away from the square panel and the functional surface of the bridge chip, wherein the first re-wiring layer is electrically connected with the first conductive column and the bridge chip, respectively;

[0012] A plurality of second conductive columns penetrating the thickness of the square panel and electrically connected with the first conductive column are formed on the square panel;

[0013] A second re-wiring layer electrically connected with the second conductive column is formed on the second surface of the square panel;

[0014] A power management module is formed on the second re-wiring layer, and a chip operation module is formed on the first re-wiring layer.

[0015] Optionally, the forming the second conductive pillars through the thickness of the square panel and electrically connected with the first conductive pillars comprises:

[0016] drilling holes along the second surface of the square panel to form a plurality of through holes through the thickness of the square panel, wherein the positions of the through holes correspond to the positions of the first conductive pillars;

[0017] electroplating conductive material in the through holes to form the second conductive pillars.

[0018] Optionally, the forming the second conductive pillars through the thickness of the square panel and electrically connected with the first conductive pillars further comprises:

[0019] when the square panel is provided, the first surface of the square panel is provided with a plurality of blind holes extending to the second surface thereof, and the blind holes are provided with conductive material, wherein the positions of the blind holes correspond to the positions of the first conductive pillars;

[0020] after the first redistribution layer is formed, the second surface of the square panel is thinned to expose the blind holes to form the second conductive pillars through the thickness of the square panel.

[0021] Optionally, the forming the power management module on the second redistribution layer comprises:

[0022] forming a plurality of power management chips and a plurality of first connectors on the second redistribution layer.

[0023] Optionally, the forming the chip operation module on the first redistribution layer comprises:

[0024] forming a chip operation layer and a plurality of second connectors on the first redistribution layer, wherein the chip operation layer comprises at least a plurality of computing chips.

[0025] Optionally, the forming the chip operation module on the first redistribution layer further comprises:

[0026] comprises:

[0027] forming a chip operation layer and a plurality of photoelectric conversion chips on the first redistribution layer, wherein the chip operation layer comprises at least a plurality of computing chips.

[0028] Optionally, after the plastic packaging layer is formed, the method further comprises:

[0029] thinning the side of the plastic packaging layer away from the square panel to expose the functional surface of the bridge chip.

[0030] Optionally, the forming the plurality of first conductive pillars through the thickness of the plastic sealing layer comprises:

[0031] drilling holes along a side of the plastic sealing layer away from the square panel to form a plurality of plastic sealing through holes through the thickness of the plastic sealing layer;

[0032] electroplating conductive material in the plastic sealing through holes to form the first conductive pillars.

[0033] Optionally, the square panel is a glass panel

[0034] Another aspect of the embodiments of the present disclosure provides a board-level packaging structure formed by the board-level packaging method described above.

[0035] The board-level packaging method and packaging structure of the embodiments of the present disclosure provide a square panel, form a board-level packaging structure on the square panel, and use a large-area square panel as a carrier board, which significantly improves the chip capacity, area utilization rate, and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high-computing-power integration of the board-level packaging structure. The chip computing module realizes high-density interconnection with the help of a plurality of bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL. A plurality of first conductive pillars are formed through the thickness of the plastic sealing layer, a plurality of second conductive pillars are formed through the thickness of the square panel and electrically connected with the first conductive pillars, vertical interconnection of the packaging structure is realized through the first conductive pillars and the second conductive pillars, and the transmission path is effectively shortened. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A flowchart of a board-level packaging method of an embodiment of the present disclosure;

[0037] Figures 2 to 16 A process flowchart of a board-level packaging method of an embodiment of the present disclosure;

[0038] Figures 17 to 31 A process flowchart of a board-level packaging method of another embodiment of the present disclosure;

[0039] Figure 32 A structure diagram of a board-level packaging system of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] To make the skilled in the art better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.

[0041] As shown in the drawings, Figure 1 an aspect of the embodiments of the present disclosure provides a board-level packaging method S100, the method S100 comprises:

[0042] S110. A square panel is provided, and a plurality of bridging chips are fixed to the first surface of the square panel.

[0043] S120, A molding layer is formed on the first surface of the square panel to encapsulate the plurality of the bridging chips.

[0044] S130, A plurality of first conductive pillars are formed in the molding layer, penetrating its thickness.

[0045] S140. A first rewiring layer is formed on the surface of the molding layer opposite to the square panel and the functional surface of the bridging chip, wherein the first rewiring layer is electrically connected to the first conductive post and the bridging chip respectively.

[0046] S150, A plurality of second conductive pillars are formed in the square panel, penetrating its thickness and electrically connected to the first conductive pillar.

[0047] S160, A second rewiring layer electrically connected to the second conductive post is formed on the second surface of the square panel.

[0048] S170. A power management module is formed on the second wiring layer, and a chip computing module is formed on the first wiring layer.

[0049] The board-level packaging method and packaging structure of this disclosure include a square panel on which a board-level packaging structure is formed. Using a large-area square panel as a carrier significantly improves chip capacity, area utilization, and I / O density, thereby significantly enhancing system performance and solving the problem of limited performance in a single SoW system. This achieves high-performance integration of the board-level packaging structure. The chip computing module achieves high-density interconnection through multiple bridging chips, eliminating the need to rely on constructing fine circuit structures in the RDL. Multiple first conductive pillars penetrating the thickness of the molding layer are formed, and multiple second conductive pillars penetrating the thickness of the square panel and electrically connected to the first conductive pillars are formed. Vertical interconnection of the packaging structure is achieved through the first and second conductive pillars, effectively shortening the transmission path.

[0050] The following describes the specific process of a board-level packaging method S100 according to several embodiments of this disclosure.

[0051] Example 1

[0052] In step S110, as Figure 2 As shown, a square panel 22 is provided. In providing the square panel 22, a plurality of blind holes 46' extending towards its second surface are provided on the first surface of the square panel 22, and conductive material is disposed within the blind holes 46'. For example... Figure 2As shown, the non-functional surfaces of the plurality of bridge chips 24 are fixed to the first surface of the square panel 22.

[0053] In this embodiment, a large-area square panel is used as a carrier board, which significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration of a board-level packaging structure.

[0054] In step S120, as shown, Figure 3 A plastic encapsulation layer 26 wrapping the plurality of bridge chips 24 is formed on the first surface of the square panel 22. The plastic encapsulation layer 26 protects the plurality of bridge chips 24.

[0055] As shown, Figure 4 The side of the plastic encapsulation layer 26 away from the square panel 22 is thinned by grinding or other methods to expose the bumps of the functional surfaces of the bridge chips 24.

[0056] In step S130, as shown, Figure 5 A plurality of first conductive pillars 48 penetrating the thickness of the plastic encapsulation layer 26 are formed on the plastic encapsulation layer 26.

[0057] The specific process of forming the first conductive pillars 48 can be as follows: drilling holes along the side of the plastic encapsulation layer 26 away from the square panel 22 to form a plurality of plastic encapsulation through holes penetrating the thickness of the plastic encapsulation layer, and electroplating conductive material in the plastic encapsulation through holes to form the first conductive pillars 48. That is, the first conductive pillars 48 are TMVs.

[0058] In step S140, as shown, Figure 6 A first redistribution layer is formed on the surface of the plastic encapsulation layer 26 away from the square panel 22 and the functional surfaces of the bridge chips 24, wherein the first redistribution layer is electrically connected to the first conductive pillars 48 and the bridge chips 24, respectively.

[0059] The specific process of forming the first redistribution layer can be as follows:

[0060] As shown, Figure 6 A first dielectric layer 28 is formed on the surface of the plastic encapsulation layer 26 away from the square panel 22 and the functional surfaces of the bridge chips 24. The first dielectric layer 28 is patterned to form a plurality of first openings, and a first metal layer 30 is formed in the plurality of first openings. The first dielectric layer 28 can be a PI layer, and the first metal layer 30 can be a copper metal layer.

[0061] As shown, Figure 7 The first redistribution layer is fixed to the carrier board 50 by temporary bonding glue. As shown, Figure 8 The carrier board 50 is turned over to be located at the lower side as a support.

[0062] In step S150, a plurality of second conductive pillars 46 are formed through the thickness of the square panel 22 and are electrically connected to the first conductive pillars 48.

[0063] Specifically, as shown in Figure 8 the specific process of forming the second conductive pillars 46 can be as follows:

[0064] The second surface of the square panel 22 is thinned to expose the blind hole, forming the second conductive pillars 46 through the thickness of the square panel 22. That is, the second conductive pillars 46 are TGV. Among them, the second conductive pillars 46 are electrically connected to the first conductive pillars 48, thereby realizing vertical interconnection on both sides of the square panel 22.

[0065] In this embodiment, a plurality of first conductive pillars are formed through the thickness of the plastic package layer, and a plurality of second conductive pillars are formed through the thickness of the square panel and are electrically connected to the first conductive pillars, thereby realizing vertical interconnection of the package structure through the first conductive pillars and the second conductive pillars, effectively shortening the transmission path.

[0066] In step S160, as shown in Figure 9 a second redistribution layer electrically connected to the second conductive pillars 46 is formed on the second surface of the square panel 22.

[0067] Among them, the specific process of forming the second redistribution layer is: forming a second dielectric layer 52 on the second surface of the square panel 22, patterning the second dielectric layer 52 to form a plurality of second openings, and forming a second metal layer 54 in the second openings, wherein the second metal layer 54 is electrically connected to the second conductive pillars 46. In this embodiment, the second dielectric layer 52 can be a PI layer, and the second metal layer 54 can be a copper metal layer.

[0068] In step S170, as shown in Figures 10 to 16 a power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

[0069] Among them, the power management module formed on the second redistribution layer specifically includes:

[0070] As shown in Figure 10 a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second redistribution layer. Specifically, a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second metal layer 54. Among them, the first connector 34 is provided with a first cable 36. The power management chip 56 is used to power the board-level package structure, and the first connector 34 can realize electrical connection between a plurality of board-level package structures.

[0071] It should be noted that the first connector 34 and the power management chip 56 can be arranged at intervals, and of course the first connector 34 can also be arranged on the second redistribution layer of the edge area of the square panel 22, facilitating electrical connection between multiple board-level packaging structures. The number and distribution position of the first connector 34 and the power management chip 56 are not specifically limited, and can be selected according to actual needs.

[0072] The chip operation module formed on the first redistribution layer can specifically include:

[0073] As shown in Figure 11 , the intermediate package is clamped on the jig 58 to realize structural suspension. As shown in Figure 10 , the intermediate package is flipped, and the carrier board 50 is removed. As shown in Figure 12 , the intermediate package is flipped, and the carrier board 50 is removed. As shown in Figure 11 , the intermediate package is flipped, and the carrier board 50 is removed. As shown in Figure 13 , the chip operation layer 32 and a plurality of second connectors 34' are formed on the first redistribution layer, wherein the second connector 34' is provided with a second cable 36'. The chip operation layer 32 at least includes a plurality of computing chips. The chip operation layer 32 can also include a storage chip or other types of computing chips. The second connector 34' is used for electrical connection between multiple board-level packaging structures.

[0074] The chip operation module formed on the first redistribution layer can specifically include:

[0075] As shown in Figure 14 , the chip operation layer 32 and a plurality of photoelectric conversion chips 38 are formed on the first redistribution layer, wherein the photoelectric conversion chip 38 is provided with an optical fiber 40. The optical fiber 40 on the photoelectric conversion chip 38 is used for electrical connection between multiple board-level packaging structures. The chip operation layer 32 at least includes a plurality of computing chips. The chip operation layer 32 can also include a storage chip or other types of computing chips.

[0076] As shown in Figure 15 and Figure 16 , the jig 58 is removed, and a board-level packaging structure is prepared.

[0077] Exemplarily, in the present embodiment, the square panel 22 can adopt a glass panel.

[0078] In existing technologies, the carrier board is peeled off during the packaging process, and the final package structure does not contain the carrier board. However, the board-level packaging structure of this disclosure retains the square glass panel. The rigidity of the glass panel effectively controls the warpage of the board-level packaging structure, solving the problem of large-area EMC and chip CTE mismatch in existing technologies, and improving the reliability of the board-level packaging structure. Furthermore, multiple second conductive pillars are provided on the retained square panel to achieve vertical interconnection of the packaging structure, effectively shortening the transmission path.

[0079] Example 2

[0080] In step S110, as Figure 17 As shown, a square carrier board 22 is provided, and the non-functional surfaces of multiple bridging chips 24 are fixed to the first surface of the square panel 22. In this embodiment, a large-area square panel is used as the carrier board, which significantly improves the chip capacity, area utilization, and I / O density, and significantly improves system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration of board-level packaging structure.

[0081] It should be noted that the number of the game bridging chips 24 is not specifically limited and can be limited according to actual needs.

[0082] In step S120, as Figure 18 As shown, a molding compound 26 is formed on the first surface of the square panel 22 to encapsulate the plurality of bridging chips 24. The molding compound 26 protects the plurality of bridging chips 24.

[0083] like Figure 19 As shown, the side of the molding layer 26 away from the square panel 22 is thinned by grinding and other methods to expose the bumps on the functional surface of the bridging chip 24.

[0084] In step S130, as Figure 20 As shown, a plurality of first conductive pillars 48 are formed in the molding layer 26, extending through its thickness.

[0085] The specific process for forming the first conductive post 48 can be as follows: drilling is performed along the side of the molding layer 26 away from the square panel 22 to form multiple through holes penetrating the thickness of the molding layer; conductive material is electroplated into the through holes to form the first conductive post 48. That is to say, the first conductive post 48 is TMV.

[0086] In step S140, as Figure 21 As shown, a first rewiring layer is formed on the surface of the molding layer 26 opposite to the square panel 22 and on the functional surface of the bridging chip 24, wherein the first rewiring layer is electrically connected to the first conductive post 48 and the bridging chip 24, respectively.

[0087] The specific process of forming the first redistribution layer can be as follows:

[0088] As shown in Figure 21 , a first dielectric layer 28 is formed on the surface of the square panel 22 away from the square panel 22 and the functional surface of the bridge chip 24. The first dielectric layer 28 is patterned to form a plurality of first openings, and a first metal layer 30 is formed in the plurality of first openings. The first dielectric layer 28 can be a PI layer, and the first metal layer 30 can be a copper layer.

[0089] As shown in Figure 22 , the first redistribution layer is fixed to the carrier plate 50 by temporary bonding glue. As shown in Figure 23 , the carrier plate 50 is turned over to be supported on the lower side.

[0090] In step S150, a plurality of second conductive pillars 46 are formed through the thickness of the square panel 22 and are electrically connected to the first conductive pillars 48.

[0091] Specifically, as shown in Figure 23 , the specific process of forming the second conductive pillars 46 can be as follows:

[0092] Drilling is performed along the second surface of the square panel 22 to form a plurality of through holes through the thickness of the square panel, wherein the positions of the through holes correspond to the positions of the first conductive pillars 48; and the through holes are electroplated with conductive material to form the second conductive pillars 46.

[0093] In this embodiment, a plurality of first conductive pillars are formed through the thickness of the encapsulation layer, and a plurality of second conductive pillars are formed through the thickness of the square panel and are electrically connected to the first conductive pillars, so that the vertical interconnection of the packaging structure is realized through the first conductive pillars and the second conductive pillars, effectively shortening the transmission path.

[0094] In step S160, as shown in Figure 24 , a second redistribution layer electrically connected to the second conductive pillars 46 is formed on the second surface of the square panel 22.

[0095] The specific process of forming the second redistribution layer is as follows: a second dielectric layer 52 is formed on the second surface of the square panel 22, the second dielectric layer 52 is patterned to form a plurality of second openings, and a second metal layer 54 is formed in the second openings, wherein the second metal layer 54 is electrically connected to the second conductive pillars 46. In this embodiment, the second dielectric layer 52 can be a PI layer, and the second metal layer 54 can be a copper layer.

[0096] In step S170, as shown in Figures 25 to 31 , a power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

[0097] The power management module formed on the second rewiring layer specifically includes:

[0098] like Figure 25 As shown, multiple power management chips 56 and multiple first connectors 34 are formed on the second redistribution layer. Specifically, multiple power management chips 56 and multiple first connectors 34 are formed on the second metal layer 54. Each first connector 34 has a first cable 36 mounted on it. The power management chips 56 supply power to the board-level package structure, and the first connectors 34 enable electrical connections between multiple board-level package structures.

[0099] It should be noted that the first connector 34 and the power management chip 56 can be arranged alternately. Alternatively, the first connector 34 can be located on the second wiring layer at the edge of the square panel 22 to facilitate electrical connections between multiple board-level package structures. The number and distribution of the first connector 34 and the power management chip 56 are not specifically limited and can be selected according to actual needs.

[0100] Specifically, the chip computing module formed on the first interconnect layer may include:

[0101] like Figure 26 As shown, Figure 25 The intermediate package is clamped onto fixture 58 to achieve structural suspension. For example... Figure 27 As shown, Figure 26 The intermediate package shown is flipped over, and the carrier plate 50 is removed. (As shown) Figure 28 As shown, a chip computing layer 32 and a plurality of second connectors 34' are formed on the first redistribution layer, wherein second cables 36' are disposed on the second connectors 34'. The chip computing layer 32 includes at least a plurality of computing chips. The chip computing layer 32 may also include memory chips or other types of computing chips. The second connectors 34' are used for electrical connections between multiple board-level package structures.

[0102] In this embodiment, the chip computing layer 32 is located on the second wiring layer in the central area of ​​the square panel 22, and the second connector 34' is located on the second wiring layer in the edge area of ​​the square panel, which facilitates electrical connection with the adjacent packaging structure.

[0103] Specifically, the chip computing module formed on the first wiring layer may further include:

[0104] like Figure 29As shown, the chip operation layer 32 and a plurality of photoelectric conversion chips 38 are formed on the first redistribution layer. The photoelectric conversion chip 38 is provided with an optical fiber 40. The optical fiber 40 on the photoelectric conversion chip 38 is used for electrical connection between a plurality of board-level packaging structures. The chip operation layer 32 at least includes a plurality of computing chips. The chip operation layer 32 can also include a storage chip or other types of computing chips.

[0105] In the embodiment, the chip operation layer 32 is located on the second redistribution layer in the central region of the square panel 22, and the photoelectric conversion chip 38 is located on the second redistribution layer in the edge region of the square panel, which is convenient for electrical connection with adjacent packaging structures.

[0106] It should be noted that the type of connector in the chip operation module is not limited in the embodiment, and can be selected as needed.

[0107] As shown in Figure 30 and Figure 31 The board-level packaging structure is prepared by removing the jig 58.

[0108] Exemplarily, in the embodiment, the square panel 22 can be a glass panel.

[0109] In the prior art, the carrier plate is peeled off during packaging, and the final packaging structure does not contain the carrier plate. The board-level packaging structure of the embodiment of the present disclosure retains the square glass panel, and effectively controls the warping of the board-level packaging structure by using the rigidity of the glass panel, solves the problem of mismatching between the large-area EMC and the chip CTE in the prior art, and improves the reliability of the board-level packaging structure. In addition, a plurality of second conductive pillars are arranged on the retained square panel, realizing vertical interconnection of the packaging structure, and effectively shortening the transmission path.

[0110] Another aspect of the embodiment of the present disclosure provides a board-level packaging structure, which is packaged by using the board-level packaging method S100 described above. The specific steps of the board-level packaging method S100 have been described in detail above, and will not be repeated here.

[0111] The board-level packaging structure of the embodiment of the present disclosure uses a large-area square panel, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration; the chip operation module realizes high-density interconnection with the help of a plurality of bridge chips, and no longer needs to rely on constructing fine line structures in the RDL; the plastic packaging layer is provided with a plurality of first conductive pillars penetrating through the thickness thereof, and the square panel is provided with a plurality of second conductive pillars penetrating through the thickness thereof, the vertical interconnection of the packaging structure is realized through the first conductive pillars and the second conductive pillars, the transmission path is effectively shortened, and the packaging thickness is reduced.

[0112] AsFigure 32 As shown, another aspect of the embodiments of the present disclosure provides a board-level packaging system A, comprising at least one board-level packaging structure 100 described above. Wherein, the specific structural features of the board-level packaging structure 100 have been described in detail above, and will not be repeated here.

[0113] Wherein, when the board-level packaging system A comprises a plurality of board-level packaging structures 100, the plurality of board-level packaging structures 100 are electrically connected through the first connector 34 and the second connector 34’ / optoelectronic conversion chip 38.

[0114] In an embodiment, the first surfaces between the plurality of board-level packaging structures 100 can be electrically connected through the first cables 36 of the first connector 34, and the second surfaces between the plurality of board-level packaging structures 100 can be electrically connected through the second cables 36’ of the second connector 34’, forming Figure 32 the board-level packaging system A as shown.

[0115] In another embodiment, the first surfaces between the plurality of board-level packaging structures A can be electrically connected through the first cables 36 of the first connector 34, and the second surfaces between the plurality of board-level packaging structures 100 can be electrically connected through the optical cables 40 of the optoelectronic conversion chip 38, forming Figure 32 the board-level packaging system A as shown.

[0116] It should be noted that in the present embodiment, the electrical connection mode between the plurality of board-level packaging structures 100 is not specifically limited, and can be selected according to actual needs.

[0117] It should be further noted that the number of board-level packaging structures 100 in the board-level packaging system A is not specifically required, and can be selected according to the size of the board-level packaging structure.

[0118] The board-level packaging system of the embodiments of the present disclosure comprises at least one board-level packaging structure described above, the board-level packaging structure adopts a large-area square panel, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high-computing power integration; the chip computing module realizes high-density interconnection with the aid of a plurality of bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL; the plastic packaging layer is provided with a plurality of first conductive pillars penetrating through the thickness thereof, and the square panel is provided with a plurality of second conductive pillars penetrating through the thickness thereof, the vertical interconnection of the packaging structure is realized through the first conductive pillars and the second conductive pillars, the transmission path is effectively shortened, and the packaging thickness is reduced.

[0119] It can be understood that the above implementation is only an exemplary implementation adopted for illustrating the principles of the embodiments of the present disclosure, however, the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and principle of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the embodiments of the present disclosure.

Claims

1. A board-level packaging method, characterized in that, The method includes: A square panel is provided, and multiple bridging chips are fixed to a first surface of the square panel; A molding compound is formed on the first surface of the square panel to encapsulate the plurality of bridging chips; A plurality of first conductive pillars are formed throughout the thickness of the molding layer; A first rewiring layer is formed on the surface of the molding layer opposite to the square panel and on the functional surface of the bridging chip, wherein the first rewiring layer is electrically connected to the first conductive pillar and the bridging chip, respectively. A plurality of second conductive pillars are formed in the square panel, penetrating its thickness and electrically connected to the first conductive pillar; A second rewiring layer electrically connected to the second conductive pillar is formed on the second surface of the square panel; A power management module is formed on the second wiring layer, and a chip computing module is formed on the first wiring layer; wherein... Forming a power management module on the second rewiring layer specifically includes: forming a plurality of power management chips and a plurality of first connectors on the second rewiring layer, wherein the first connectors are spaced apart from the power management chips; Forming a chip computing module on the first rewiring layer specifically includes: forming a chip computing layer and multiple second connectors on the first rewiring layer, and / or forming a chip computing layer and multiple photoelectric conversion chips on the first rewiring layer, wherein the chip computing layer includes at least multiple computing chips.

2. The board-level packaging method according to claim 1, characterized in that, The method of forming multiple second conductive pillars that penetrate the thickness of the square panel and are electrically connected to the first conductive pillar includes: Drilling is performed along the second surface of the square panel to form a plurality of through holes penetrating the thickness of the square panel, wherein the positions of the through holes correspond to the positions of the first conductive post; Conductive material is electroplated inside the through hole to form the second conductive pillar.

3. The board-level packaging method according to claim 1, characterized in that, The method of forming multiple second conductive pillars that penetrate the thickness of the square panel and are electrically connected to the first conductive pillar further includes: When the square panel is provided, a plurality of blind holes extending to its second surface are provided on the first surface of the square panel, and conductive material is disposed in the blind holes, wherein the position of the blind holes corresponds to the position of the first conductive post; After the first redistribution layer is formed, the second surface of the square panel is thinned to expose the blind hole, forming the second conductive pillar that penetrates the thickness of the square panel.

4. The board-level packaging method according to any one of claims 1 to 3, characterized in that, After forming the molding layer, the method further includes: The molding layer is thinned on the side opposite to the square panel to expose the functional surface of the bridging chip.

5. The board-level packaging method according to any one of claims 1 to 3, characterized in that, The formation of a plurality of first conductive pillars penetrating the thickness of the molding layer includes: Drill holes along the side of the molding layer away from the square panel to form multiple through holes that penetrate the thickness of the molding layer; Conductive material is electroplated inside the plastic-sealed through-hole to form the first conductive pillar.

6. The board-level packaging method according to any one of claims 1 to 3, characterized in that, The square panel is made of glass.

7. The board-level packaging method according to any one of claims 1 to 3, characterized in that, The first rewiring layer is formed, including: A first dielectric layer is formed on the surface of the molding layer opposite to the square panel and on the functional surface of the bridging chip. The first dielectric layer is patterned to form multiple first openings, and a first metal layer is formed within the multiple first openings.

8. The board-level packaging method according to any one of claims 1 to 3, characterized in that, Forming a second routing layer includes: A second dielectric layer is formed on the second surface of the square panel; The second dielectric layer is patterned to form a plurality of second openings, and a second metal layer is formed at the second openings; wherein the second metal layer is electrically connected to the second conductive pillar.

9. The board-level packaging method according to any one of claims 1 to 3, characterized in that, The chip computing layer is located on the second overlay layer in the central region of the square panel; The second connector and the photoelectric conversion chip are located on the second wiring layer in the edge area of ​​the square panel.

10. A board-level packaging structure, characterized in that, It is packaged using the board-level packaging method according to any one of claims 1 to 9.

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