Method for manufacturing electronic device

Abstract

The invention provides a manufacturing method of an electronic device, which is characterized by comprising the following steps: a carrier and a circuit substrate are provided, the carrier comprises a plurality of spacers, the circuit substrate comprises a plurality of electronic units, and the electronic units are detected and judged to be normal or defective; providing a plurality of cover plate units on the carrier; the circuit substrate is arranged on the cover plate unit, the distance piece supports the circuit substrate, a gap is formed between the circuit substrate and the cover plate unit, and the cover plate unit corresponds to the normal electronic unit; vacuumizing a gap between the circuit substrate and the cover plate unit; moving the spacer to bring the cover plate unit and the circuit substrate into contact with each other; and pressing the cover plate unit and the circuit substrate to fix the cover plate unit and the circuit substrate to each other.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing an electronic device, and more particularly to a method for manufacturing an electronic device package. Background Art

[0002] Generally, in the manufacturing process of electronic devices, such as in the packaging process, the cover plate and the circuit substrate are assembled and then cut into a plurality of independent units.

[0003] However, the traditional process still suffers from poor vacuum after assembly or material waste due to abnormal packaging of electronic units.

[0004] Therefore, there is an urgent need to provide a method for manufacturing an electronic device in order to improve the existing defects. Summary of the invention

[0005] The present disclosure provides a method for manufacturing an electronic device, characterized in that it includes the following steps: providing a carrier and a circuit substrate, wherein the carrier includes a plurality of spacers, the circuit substrate includes a plurality of electronic units, and the electronic units are detected and judged to be normal or defective; providing a plurality of cover units on the carrier; arranging the circuit substrate on the cover units so that the spacers support the circuit substrate, wherein there is a gap between the circuit substrate and the cover units, and the cover units correspond to the normal electronic units; evacuating the gap between the circuit substrate and the cover units; moving the spacers so that the cover units and the circuit substrate are in contact with each other; and pressing the cover units and the circuit substrate so that the cover units and the circuit substrate are fixed to each other.

[0006] The present disclosure further provides a method for manufacturing an electronic device, characterized in that it includes the following steps: providing a carrier and a circuit substrate, wherein the carrier includes a plurality of first marks, and the circuit substrate includes a plurality of second marks and a plurality of electronic units, in a top-view direction of the carrier, the second marks and the electronic units are separated from each other, and the electronic units are detected and judged to be normal or defective; providing a plurality of cover units on the carrier; arranging the circuit substrate on the cover units so that the first marks of the carrier overlap with the second marks of the circuit substrate in a top-view direction of the carrier, wherein the cover units correspond to the normal electronic units; evacuating the circuit substrate and the cover units; and pressing the cover units and the circuit substrate to fix the cover units and the circuit substrate to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2A is a schematic top view of a carrier according to an embodiment of the present disclosure;

[0009] Figure 2B is a bottom view schematically showing a circuit substrate according to an embodiment of the present disclosure;

[0010] Figure 2C It is a top view schematic diagram of a carrier and a circuit substrate after being assembled in one embodiment of the present disclosure;

[0011] Figure 3A and Figure 3B is a side view schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0012] Figure 4A and Figure 4B is a cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of the present disclosure;

[0013] Figure 5A and Figure 5B is a cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of the present disclosure;

[0014] Fig. 6A is a schematic top view of a carrier according to an embodiment of the present disclosure;

[0015] Figure 6B is a bottom view schematically showing a circuit substrate according to an embodiment of the present disclosure;

[0016] Figure 6C It is a top view schematic diagram of a carrier and a circuit substrate after being assembled in one embodiment of the present disclosure;

[0017] Fig. 7A is a schematic top view of a carrier according to an embodiment of the present disclosure;

[0018] Figure 7B is a bottom view schematically showing a circuit substrate according to an embodiment of the present disclosure;

[0019] Figure 7C It is a top view schematic diagram of a carrier and a circuit substrate after being assembled in one embodiment of the present disclosure;

[0020] Fig. 8A and Figure 8B FIG. 4 is a schematic side view of a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0021] In the above drawings, the meanings of the reference numerals are as follows:

[0022] 1-Carrier

[0023] 11-Limiting part

[0024] 11s-Concave surface

[0025] 12- Accommodation space

[0026] 13- Spring

[0027] 2-Circuit substrate

[0028] 21-Substrate

[0029] 3-Cover unit

[0030] 31-Substrate

[0031] 311-concave

[0032] 32-First optical film

[0033] 33-Second optical film

[0034] 4-Laminating machine

[0035] 5-Drive circuit

[0036] 51-Buffer layer

[0037] 52-Active Layer

[0038] 53-First insulation layer

[0039] 54-First metal layer

[0040] 54a-gate

[0041] 55-Second insulation layer

[0042] 56-Second metal layer

[0043] 56a-Source

[0044] 56b-Drain

[0045] 57-Third insulation layer

[0046] 6-Sensing element

[0047] 61-Reflection layer

[0048] 62-Support layer

[0049] 63-Third metal layer

[0050] 64-Sensing unit

[0051] 641-Absorption layer

[0052] 642-Fourth metal layer

[0053] 643-First passivation layer

[0054] 644-Sensing Layer

[0055] 645-Second passivation layer

[0056] 6a-Supporting element

[0057] B1-First bonding material

[0058] B11-first sub-metal layer B12-second sub-metal layer B13-third sub-metal layer B2-second bonding material B21-fourth sub-metal layer B22-fifth sub-metal layer B23-sixth sub-metal layer B3-third bonding material CL-fixing part CP-carrying part CP1-top surface E-electronic unit E1-normal electronic unit E2-defective electronic unit G1-gap G2-gap M1-first mark M2-second mark P-connecting part S-sealed space SP-spacer SP1-top surface TFT-thin film transistor U-monomer V1-through hole H1, H3-height H2-depth X, Y-direction Z-top view direction DETAILED DESCRIPTION

[0059] The following is an explanation of the implementation of the present disclosure through specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways according to different viewpoints and applications without departing from the spirit of the present invention.

[0060] It should be noted that, in this document, unless otherwise specified, "having an element" is not limited to having a single element, but may have one or more elements. In addition, the ordinal numbers used in the specification and claims, such as "first" and "second", to modify the elements of the claims, do not themselves imply or represent any previous ordinal numbers of the claimed elements, nor do they represent the order of one claimed element and another claimed element, or the order of the manufacturing method. The use of these ordinals is only used to make a claimed element with a certain name clearly distinguishable from another claimed element with the same name.

[0061] Certain words are used throughout the specification and the claims that follow to refer to specific components. It will be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. It is not intended herein to distinguish between components that have the same function but different names. In the following specification and claims, words such as "include", "contain", "have" are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and / or "have" are used in the description of the present disclosure, they specify the presence of corresponding features, regions, steps, operations and / or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations and / or components.

[0062] In the text, the terms "about", "approximately", "substantially", and "roughly" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The numbers given here are approximate numbers, that is, in the absence of specific instructions for "about", "approximately", "substantially", and "roughly", the meanings of "about", "approximately", "substantially", and "roughly" can still be implied. In addition, the terms "range from a first value to a second value" and "range between a first value and a second value" mean that the range includes the first value, the second value, and other values ​​therebetween.

[0063] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined herein.

[0064] In addition, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawings to another element. It is understood that if the device of the drawings is turned upside down, the element described on the "below" side will become the element on the "above" side. When a corresponding component (such as a film layer or region) is referred to as "on another component", it can be directly on the other component, or there can be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when a component is referred to as "on another component", the two have an up-and-down relationship in the top-view direction, and this component can be above or below the other component, and this up-and-down relationship depends on the orientation of the device.

[0065] In the present disclosure, the distance, width, length and thickness can be measured by an optical microscope, and the distance, width, length and thickness can be measured by a cross-sectional image in an electron microscope, but the present disclosure is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0066] The electronic device disclosed in the present invention may include, for example, a display device, a sensing device, an antenna device, a touch device (TouchDevice), a splicing device or other suitable electronic devices, but is not limited thereto. The display device disclosed in the present invention may be a non-self-luminous display device or a self-luminous display device, such as a liquid crystal display (Liquid Crystal Display), a cholesterol liquid crystal display (Cholesteric Liquid Crystal Display), an electrophoretic display (Electro-PhoreticDisplay), an organic light emitting diode display (Organic Light Emitting Diode Display), a light emitting diode display (Light Emitting Diode Display), but is not limited thereto. The display device may include a light emitting diode, a light conversion layer or other suitable materials, or a combination thereof, but is not limited thereto. The light emitting diode may include, for example, an organic light emitting diode (Organic Light Emitting Diode, OLED), a sub-millimeter light emitting diode (Mini LED), a micro light emitting diode (Micro LED) or a quantum dot light emitting diode (Quantum Dot LED, which may include QLED, QDLED), but is not limited thereto. The light conversion layer may include a wavelength conversion material and / or a filter material, and the light conversion layer may include, for example, fluorescence, phosphorescence, quantum dots (QD), other suitable materials or a combination of the above, but not limited thereto. The sensing device may include, for example, a biosensor, a touch sensor, a fingerprint sensor, a temperature sensor, or other suitable sensors or a combination of the above types of sensors. The antenna device may be, for example, a liquid crystal antenna or other types of antenna types, but not limited thereto. The splicing device may include, for example, a splicing display device or a splicing antenna device, but not limited thereto. The electronic device may include an electronic component, and the electronic component may include a passive component, an active component or a combination of the above, such as a capacitor, a resistor, an inductor, a varactor diode, a variable capacitor, a filter, a diode, a transistor, a sensor, a micro-electromechanical system component (MEMS), a chip, etc., but not limited thereto. It should be noted that the electronic device of the present disclosure may be various combinations of the above devices, but not limited thereto.

[0067] Features from several different embodiments may be replaced, reorganized, or mixed to create other embodiments without departing from the spirit of the present disclosure.

[0068] Figure 1 The figure is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0069] In one embodiment of the present disclosure, Figure 1 As shown, the manufacturing method of the electronic device may include: providing a carrier and a circuit substrate, and detecting an electronic unit in the circuit substrate; providing a cover unit on the carrier; arranging the circuit substrate on the cover unit; evacuating the gap between the circuit substrate and the cover unit; bringing the cover unit into contact with the circuit substrate; and pressing the cover unit and the circuit substrate to fix the cover unit and the circuit substrate to each other, thereby achieving the effect of packaging the cover unit and the circuit substrate. The features of each step will be disclosed in detail below.

[0070] Figure 2A It is a schematic top view of a carrier according to an embodiment of the present disclosure. Figure 2B FIG. 4 is a bottom view of a circuit substrate according to an embodiment of the present disclosure. Figure 2C The figure is a top view schematically showing an assembled carrier and a circuit substrate according to an embodiment of the present disclosure. Figure 3A and Figure 3B FIG. 1 is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 3A and Figure 3B The carrier and circuit substrate in FIG. 2A to FIG. 2C Schematic diagram of the cross section of line segment A-A'.

[0071] In one embodiment of the present disclosure, a method for manufacturing an electronic device includes the following steps: providing a carrier 1 and a circuit substrate 2, wherein: Figure 2A and Figure 2B As shown, the carrier 1 may include a plurality of spacers SP; the circuit substrate 2 may include a plurality of electronic units E, and the electronic units E may be detected and judged to be normal or defective. Figure 2B The defective electronic unit E2 is represented by a black filling pattern. Next, a plurality of cover units 3 are provided on the carrier 1. In the present disclosure, the "normal electronic unit E1" refers to, for example, that the appearance, electrical, etc. of the electronic unit E are normal, and the electronic unit E can be operated. The "defective electronic unit E2" refers to, for example, that the appearance, electrical, or a combination thereof of the electronic unit E is abnormal, resulting in abnormal operation of the electronic unit E. Therefore, the step of detecting the electronic unit E may include performing electrical testing, electrostatic discharge testing, appearance testing, other suitable testing, or a combination of the above on the electronic unit E, but the present disclosure is not limited thereto.

[0072] Afterwards, if Figure 3AAs shown, the circuit substrate 2 is arranged on the cover unit 3, so that the spacer SP supports the circuit substrate 2, wherein there is a gap G1 between the circuit substrate 2 and the cover unit 3, and the cover unit 3 corresponds to the normal electronic unit E1. In one embodiment of the present disclosure, the cover unit 3 may not be arranged on the carrier 1 at the corresponding position of the defective electronic unit E2, so that the waste of the cover unit 3 can be reduced, and the effect of reducing the manufacturing cost can be achieved. Then, the gap G1 between the circuit substrate 2 and the cover unit 3 is evacuated. In more detail, for example, the circuit substrate 2 and the carrier 1 provided with the cover unit 3 can be placed in a reaction chamber (not shown in the figure), and then the reaction chamber is evacuated, but the present disclosure is not limited to this. In the present disclosure, since the spacer SP can provide support, a gap G1 is formed between the circuit substrate 2 and the cover unit 3, which will be beneficial to the vacuuming step and can improve the vacuum effect between the circuit substrate 2 and the cover unit 3. In the present disclosure, the term "vacuum" refers to a pressure in the reaction chamber that is less than or equal to 1 torr. For example, the pressure in the reaction chamber may be 10 -3 torr to 1torr or 10 -7 torr to 1torr, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, before the step of bringing the cover plate unit 3 and the circuit substrate 2 into contact with each other, a step of preheating the cover plate unit 3 and / or the circuit substrate 2 may be included. The preheating step may, for example, evaporate water vapor on the cover plate unit 3 and / or the circuit substrate 2 by heating, or volatilize organic solvents in the cover plate unit 3 and / or the circuit substrate 2, thereby increasing the vacuum degree inside the final product.

[0073] Then, if Figure 3B As shown, the spacer SP is moved to make the cover unit 3 and the circuit substrate 2 contact each other. Here, the circuit substrate 2 can contact the spacer SP and the cover unit 3 respectively, but the present disclosure is not limited thereto. Next, the cover unit 3 and the circuit substrate 2 are pressed together to fix the cover unit 3 and the circuit substrate 2 to form a Figure 2C The structure shown.

[0074] In the present disclosure, the electronic unit E may include a driving circuit, a thin film transistor, a thermal sensing element, a sensing element, a micro-electromechanical system unit, or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the material of the cover unit 3 may include silicon, germanium (Ge), zinc sulfide (ZnS), zinc selenide (ZnSe), gallium arsenide (GaAs), chalcogenide (Chalcogenide), or a combination thereof, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the cover unit 3 may, for example, allow light of a specific wavelength (for example, light of a wavelength of 5 μm to 15 μm) to penetrate, but the present disclosure is not limited thereto. In the present disclosure, the material of the spacer SP may include metal, its alloy, stainless steel, or a combination thereof, and the metal may, for example, include copper, nickel, and brass, or a combination thereof, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, Figure 2B As shown, when viewed in the top-view direction Z of the circuit substrate 2 , the circuit substrate 2 may be circular, but the present disclosure is not limited thereto.

[0075] In one embodiment of the present disclosure, Figure 2A and Figure 3A As shown, the carrier 1 may further include a carrying portion CP and a plurality of fixing members CL, wherein the carrying portion CP is used to carry the cover unit 3, and the fixing members CL are used to fix the carrying portion CP of the carrier 1 to the circuit substrate 2. Before the vacuuming step, the fixing members CL fix the carrier 1 and the circuit substrate 2, and release the fixing after the vacuuming step begins, as shown in FIG. Figure 3B More specifically, in one embodiment of the present disclosure, after the vacuuming step is started, for example, the fixing member CL may be removed first, and then the spacer SP may be moved to make the cover unit 3 and the circuit substrate 2 contact each other to perform subsequent steps. Figure 2A and Figure 3A As shown in the figure, in the top view direction Z of the carrier 1, the fixing member CL, part of the circuit substrate 2 and the spacer SP may partially overlap, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, although not shown in the figure, the fixing member CL and the spacer SP may be arranged adjacent to each other, that is, in the top view direction Z of the carrier 1, the fixing member CL may not overlap with the spacer SP. In the present disclosure, the material of the carrier portion CP may include, for example, metal, stainless steel or other suitable materials. In the present disclosure, as shown in the figure, Figure 2A As shown, when viewed in the top view direction Z of the carrier 1, the carrier portion CP may be circular, but the present disclosure is not limited thereto. In the present disclosure, the fixing member CL includes an elastic material, for example, the material of the fixing member CL may include metal, its alloy, stainless steel, or a combination thereof, wherein the metal may include copper, nickel, and brass, or a combination thereof, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the fixing member CL may be, for example, a clamp, but the present disclosure is not limited thereto.

[0076] In one embodiment of the present disclosure, Figure 2AAs shown, the carrying portion CP of the carrier 1 may further include a plurality of limiting portions 11. With respect to the cover unit 3, in more detail, the limiting portions 11 may be used to accommodate the cover unit 3. In the top view direction Z of the carrier 1, the cover unit 3 overlaps with the limiting portions 11. Figure 2A In the embodiment, the limiting portion 11 corresponding to the normal electronic unit E1 may have the cover unit 3, while the limiting portion 11 corresponding to the defective electronic unit E2 does not have the cover unit 3, so that the limiting portion 11 may be exposed.

[0077] In one embodiment of the present disclosure, Figure 2A and Figure 2B As shown, the carrying portion CP of the carrier 1 may include a plurality of first marks M1, and the circuit substrate 2 may include a connecting portion P and a plurality of second marks M2, and the plurality of second marks M2 may be arranged on the connecting portion P. Before the step of pressing the cover unit 3 and the circuit substrate 2, the manufacturing method may further include: in the top-view direction Z of the carrier 1, overlapping the first mark M1 of the carrier 1 and the second mark M2 of the circuit substrate 2. Then, the step of pressing the cover unit 3 and the circuit substrate 2 for assembly is performed. In the present disclosure, the first mark M1 and the second mark M2 may be used as alignment marks for aligning and assembling the cover unit 3 and the circuit substrate 2, so that the cover unit 3 may correspond to the normal electronic unit E1, such as Figure 3A In the present disclosure, Figure 2A and Figure 2B As shown, in the top-view direction Z of the carrier 1 or the circuit substrate 2, the first mark M1 does not overlap with the spacer SP or the fixing member CL, and the second mark M2 does not overlap with the electronic unit E. In this way, the accuracy of the pairing of the cover unit 3 and the circuit substrate 2 can be improved. In one embodiment of the present disclosure, the first mark M1 and the second mark M2 can be a convex structure, a concave structure or a combination thereof, respectively. The convex structure, for example, means that when the cover unit 3 and the circuit substrate 2 are paired, the first mark M1 protrudes toward the circuit substrate 2, and the second mark M2 protrudes toward the cover unit 3. The concave structure, for example, means that when the cover unit 3 and the circuit substrate 2 are paired, the first mark M1 is recessed away from the circuit substrate 2, and the second mark M2 is recessed away from the cover unit 3. In one embodiment of the present disclosure, there is no special limitation on the shapes of the first mark M1 and the second mark M2. For example Figure 2A and Figure 2B As shown, in the top view direction Z of the carrier 1 or the circuit substrate 2, the first mark M1 and the second mark M2 may be respectively in a "+" shape, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first mark M1 and the second mark M2 may be respectively in a circular, rectangular, L-shaped or other suitable shapes. In the present disclosure, the connection portion P of the circuit substrate 2 refers to, for example, an area in the circuit substrate 2 where no circuit is provided, and the connection portion P may surround a plurality of electronic units E, but the present disclosure is not limited thereto.

[0078] In one embodiment of the present disclosure, before providing the cover unit 3 on the carrier 1, the manufacturing method further includes: forming a first bonding material B1 on the electronic unit E, and forming a second bonding material B2 on the substrate 31 (e.g. Figure 5A In more detail, Figure 2B As shown, for example, the electronic unit E may be formed first, and the electronic unit E may be detected and judged to be normal or defective, and then the first bonding material B1 may be formed on the electronic unit E, wherein in the top view direction Z of the circuit substrate 2, the first bonding material B1 may overlap with the electronic unit E; Figure 2A As shown, for example, the second bonding material B2 may be first formed on the substrate 31 (eg Figure 5A ), and then providing a cover unit 3 on the carrier 1. In one embodiment of the present disclosure, after the step of pressing the cover unit 3 and the circuit substrate 2, the first bonding material B1 and the second bonding material B2 are bonded to form a third bonding material B3 (as shown in FIG. Figure 5B As shown), the cover unit 3 and the circuit substrate 2 are fixed to each other. In one embodiment of the present disclosure, when the first mark M1 of the carrier 1 overlaps with the second mark M2 of the circuit substrate 2 in the top-view direction Z of the carrier 1, the first bonding material B1 may at least partially overlap with the second bonding material B2 in the top-view direction Z of the carrier 1. In the present disclosure, the first bonding material B1 and the second bonding material B2 may be the same or different, and the first bonding material B1 and the second bonding material B2 may each include a metal, an alloy thereof, a glass paste (Frit Paste) or a combination thereof, and the metal may include, for example, gold, silver, copper, aluminum, chromium, platinum, titanium, nickel, tin, tungsten, palladium, molybdenum, zinc or a combination thereof, but the present disclosure is not limited thereto.

[0079] In one embodiment of the present disclosure, Figure 3B As shown, the step of pressing the cover plate unit 3 and the circuit substrate 2 may further include: heating the first bonding material B1 and the second bonding material B2 to bond the first bonding material B1 and the second bonding material B2 to form a third bonding material B3 (such as Figure 5B As shown). In the present disclosure, the temperature for heating the first bonding material B1 and the second bonding material B2 may be, for example, 90°C to 450°C, 150°C to 450°C, or 200°C to 400°C, and this temperature may be greater than the temperature of the aforementioned preheating step, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the step of pressing the cover plate unit 3 and the circuit substrate 2 may further include: applying pressure to the first bonding material B1 and the second bonding material B2, so that the first bonding material B1 and the second bonding material B2 are bonded to form a third bonding material B3 (such as Figure 5BIn the present disclosure, applying pressure to the first bonding material B1 and the second bonding material B2 refers to, for example, applying a stress greater than 0.1 MPa during the process, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, Figure 3A and Figure 3B As shown, pressure may be applied to the first bonding material B1 and the second bonding material B2 by, for example, moving the press machine 4 , but the present disclosure is not limited thereto.

[0080] In one embodiment of the present disclosure, before the step of providing the cover unit 3 on the carrier 1, the manufacturing method may further include: providing a mother substrate (not shown), wherein the mother substrate (not shown) may include a plurality of adjacent cover units 3; forming a second bonding material B2 on the cover unit 3; and cutting the mother substrate (not shown) to form separate cover units 3 (such as Figure 2A In one embodiment of the present disclosure, after the step of pressing the cover unit 3 and the circuit substrate 2 together, the method for manufacturing the electronic device may further include: cutting the circuit substrate 2 to form a plurality of monomers U (such as Figure 5B In the present disclosure, the step of cutting the mother substrate may be performed by a wheel cutter, laser cutting or a combination thereof, but the present disclosure is not limited thereto.

[0081] Figure 4A and Figure 4B FIG. 4 is a cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of the present disclosure.

[0082] in, Figure 4A A schematic diagram before moving the spacer is shown. Figure 4B A schematic diagram after moving the spacer is shown.

[0083] In one embodiment of the present disclosure, Figure 4A As shown, when the circuit substrate 2 is placed on the cover unit 3 and the spacer SP supports the circuit substrate 2, there is a gap G1 between the circuit substrate 2 and the cover unit 3, and the circuit substrate 2 can contact the spacer SP. At this time, the cover unit 3 may correspond to the normal electronic unit E1, while the cover unit 3 does not exist at the defective electronic unit E2, so that the limiting portion 11 can be exposed. The "limiting portion" refers to, for example, an area on the surface of the carrier portion CP of the carrier 1 that is recessed in a direction away from the circuit substrate 2.

[0084] In this disclosure, Figure 4AAs shown, the cover unit 3 has a height H1, and the height H1 may be between 0.3mm and 2mm (0.3mm≦height H1≦2mm), for example, between 0.5mm and 2mm or between 0.5mm and 1mm, but the present disclosure is not limited thereto. The "height of the cover unit" refers, for example, to the maximum dimension of the cover unit 3 in the top-view direction Z of the carrier 1. In the present disclosure, the limiting portion 11 has a depth H2, and the depth H2 may be between 0.1mm and 1mm (0.1mm≦depth H2≦1mm), for example, between 0.1mm and 0.8mm or between 0.1mm and 0.5mm, but the present disclosure is not limited thereto. The "depth of the limiting portion" refers, for example, to the maximum distance between the top surface CP1 of the carrier portion CP and the recessed surface 11s in the top-view direction Z of the carrier 1. In the present disclosure, the spacer SP has a height H3, and the height H3 may be between 0.3 mm and 2 mm (0.3 mm≦height H3≦2 mm), for example, between 0.5 mm and 2 mm or between 0.5 mm and 1 mm, but the present disclosure is not limited thereto. The "height of the spacer" refers, for example, to the maximum dimension between the top surface SP1 of the spacer SP and the top surface CP1 of the carrier portion CP in the top view direction Z of the carrier 1.

[0085] In one embodiment of the present disclosure, Figure 4B As shown in FIG. 1 , after the step of moving the spacer SP to bring the cover unit 3 and the circuit substrate 2 into contact with each other, the circuit substrate 2 may be in contact with the spacer SP and the cover unit 3, respectively. Figure 4A and Figure 4B As shown, the carrier portion CP of the carrier 1 may further include a plurality of accommodating spaces 12, each corresponding to the spacer SP. In the step of moving the spacer SP, the spacer SP may be at least partially moved to the accommodating space 12, so that the spacer SP and the cover unit 3 are coplanar, so that the circuit substrate 2 is in contact with the spacer SP and the cover unit 3, respectively. In one embodiment of the present disclosure, as Figure 4A and Figure 4B As shown, the purpose of partially moving the spacer SP to the accommodating space 12 can be achieved by disposing elements such as a spring 13 in the accommodating space 12 and applying stress to the spacer SP, but the present disclosure is not limited thereto.

[0086] Figure 5A and Figure 5B FIG. 4 is a cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of the present disclosure.

[0087] in, Figure 5A for Figure 3A A partial enlarged view of Figure 5B for Figure 3B A partial enlarged view of .

[0088] In one embodiment of the present disclosure, Figure 5A As shown, the circuit substrate 2 includes: an electronic unit E; and a first bonding material B1, which is disposed on the electronic unit E. In one embodiment of the present disclosure, Figure 3A and Figure 5A As shown in FIG. 1 , the circuit substrate 2 is disposed on the cover unit 3 so that the spacer SP supports the circuit substrate 2, and a gap G1 may exist between the circuit substrate 2 and the cover unit 3. In more detail, as shown in FIG. Figure 5A As shown, the gap G1 refers to, for example, the gap between the first bonding material B1 of the circuit substrate 2 and the second bonding material B2 of the cover unit 3. Figure 3B and Figure 5B As shown, when the step of pressing the cover unit 3 and the circuit substrate 2 is performed, that is, when the first bonding material B1 and the second bonding material B2 are heated, pressure is applied, or a combination thereof, the first bonding material B1 and the second bonding material B2 can be bonded to form a third bonding material B3, so as to achieve the purpose of fixing the cover unit 3 and the circuit substrate 2 to each other. In the present disclosure, the third bonding material B3 may be a compound produced by a chemical reaction between a part of the first bonding material B1 and a part of the second bonding material B2, and therefore, the third bonding material B3 may be different from the first bonding material B1 and the second bonding material B2, but the present disclosure is not limited thereto. In the present disclosure, the cover unit 3 and the circuit substrate 2 can form a sealed space S through the first bonding material B1, the second bonding material B2, and the third bonding material B3. The sealed space S may be a vacuum or near a vacuum, which can reduce the interference of other external environments (such as water vapor, air, etc.) on the electronic unit E.

[0089] In one embodiment of the present disclosure, Figure 5A As shown, the first bonding material B1 may include a first sub-metal layer B11, a second sub-metal layer B12 and a third sub-metal layer B13, wherein the second sub-metal layer B12 is located between the first sub-metal layer B11 and the third sub-metal layer B13; the second bonding material B2 may include a fourth sub-metal layer B21, a fifth sub-metal layer B22 and a sixth sub-metal layer B23, wherein the fifth sub-metal layer B22 is located between the fourth sub-metal layer B21 and the sixth sub-metal layer B23. When the first bonding material B1 and the second bonding material B2 are heated, pressure is applied or a combination thereof, a part of the first sub-metal layer B11 of the first bonding material B1 and a part of the fourth sub-metal layer B21 of the second bonding material B2 may chemically react to generate a third bonding material B3, wherein the third bonding material B3 is located between the first sub-metal layer B11 and the fourth sub-metal layer B21.

[0090] In the present disclosure, the material of the first sub-metal layer B11 and the material of the fourth sub-metal layer B21 may be the same or different, and the material of the first sub-metal layer B11 and the material of the fourth sub-metal layer B21 may each include copper, tin, gold, nickel or a combination thereof, but the present disclosure is not limited thereto. The material of the second sub-metal layer B12 and the material of the fifth sub-metal layer B22 may be the same or different, and the material of the second sub-metal layer B12 and the material of the fifth sub-metal layer B22 may each include copper, tin, gold, nickel or a combination thereof, but the present disclosure is not limited thereto. The material of the third sub-metal layer B13 and the material of the sixth sub-metal layer B23 may be the same or different, and the material of the third sub-metal layer B13 and the material of the sixth sub-metal layer B23 may each include molybdenum, copper, titanium or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the material of the first sub-metal layer B11 is different from the material of the second sub-metal layer B12, and the material of the fourth sub-metal layer B21 is different from the material of the fifth sub-metal layer B22. In an embodiment of the present disclosure, the third bonding material B3 may be, for example, copper tin, such as Cu3Sn, but the present disclosure is not limited thereto.

[0091] In one embodiment of the present disclosure, after the step of pressing the cover plate unit 3 and the circuit substrate 2 together, the method for manufacturing the electronic device may further include: cutting the circuit substrate 2 to form a plurality of circuit substrates as shown in FIG. Figure 5B The unit U shown. In the present disclosure, the electronic device may include a single unit U, or may include a plurality of units U. In the present disclosure, the unit U may be used to receive a signal or release a signal, such as receiving a signal of a specific wavelength or emitting a signal of a specific wavelength, but the present disclosure is not limited thereto.

[0092] In one embodiment of the present disclosure, Figure 5A and Figure 5BAs shown, the electronic unit E may include, for example, a substrate 21; a driving circuit 5 disposed on the substrate 21; and a sensing element 6 disposed on the driving circuit 5 and electrically connected to the driving circuit 5. The driving circuit 5 may include, for example: a buffer layer 51 disposed on the substrate 21; an active layer 52 disposed on the buffer layer 51; a first insulating layer 53 disposed on the active layer 52; a first metal layer 54 disposed on the first insulating layer 53, and the first metal layer 54 includes a gate 54a; a second insulating layer 55 disposed on the first metal layer 54; a second metal layer 56 disposed on the second insulating layer 55, and the second metal layer 56 includes a source 56a and a drain 56b; and a third insulating layer 57 disposed on the second metal layer 56, wherein the active layer 52, the first insulating layer 53, the gate 54a, the second insulating layer 55, the source 56a and the drain 56b form a thin film transistor TFT. The sensing element 6 may include, for example: a reflective layer 61 disposed on the third insulating layer 57, wherein the reflective layer 61 may be electrically connected to the drain 56b through the through hole V1 of the third insulating layer 57; a support layer 62 disposed on the reflective layer 61; a third metal layer 63 disposed on the support layer 62, wherein the support layer 62 and the third metal layer 63 may form a support element 6a for supporting the sensing unit 64 above; and a sensing unit 64 disposed on the support element 6a. The sensing unit 64 may include: an absorption layer 641 disposed on the support layer 62; a fourth metal layer 642 disposed on the absorption layer 641; a first passivation layer 643 disposed on the absorption layer 641 and the fourth metal layer 642; a sensing layer 644 disposed on the first passivation layer 643; and a second passivation layer 645 disposed on the sensing layer 644. In the present disclosure, heat can be generated by absorbing light of a specified wavelength range through the absorption layer 641, and the heat is transferred to the sensing layer 644 through the fourth metal layer 642 and the first passivation layer 643. The sensing layer 644 changes resistance as the heat changes to form an electrical signal, so that the sensing element 6 senses light of a specified wavelength range. In the present disclosure, the specified wavelength range may be, for example, between 8 μm and 14 μm, but the present disclosure is not limited thereto. In the present disclosure, the support layer 6a may allow a gap G2 to exist between the sensing unit 64 and the reflective layer 61. The gap G2 may be formed by respectively setting a sacrificial layer (not shown) on the reflective layer 61 and the support element 6a, and then removing the sacrificial layer (not shown). The gap G2 may be used to prevent heat conduction from affecting the sensing signal.

[0093] In the present disclosure, the substrate 21 may be a hard substrate or a soft substrate. The material of the substrate 21 may include quartz, glass, wafer, sapphire, resin, epoxy resin, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethylmethacrylate (PMMA), other plastic materials or combinations thereof, but the present disclosure is not limited thereto. In the present disclosure, the materials of the buffer layer 51, the first insulating layer 53, the second insulating layer 55 and the third insulating layer 57 may be the same or different, wherein the materials of the buffer layer 51, the first insulating layer 53, the second insulating layer 55 and the third insulating layer 57 may each include silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the material of the active layer 52 may include amorphous silicon, polycrystalline silicon (e.g., low temperature polycrystalline silicon (LTPS)), or an oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), but the present disclosure is not limited thereto. In the present disclosure, the materials of the first metal layer 54, the second metal layer 56, and the reflective layer 61 may be the same or different, wherein the materials of the first metal layer 54, the second metal layer 56, and the reflective layer 61 may each include gold, silver, copper, palladium, platinum (Pt), ruthenium (Ru), aluminum, cobalt, nickel, titanium, molybdenum (Mo), manganese, zinc, alloys thereof, or combinations thereof, but the present disclosure is not limited thereto.

[0094] In the present disclosure, the material of the support layer 62 may include titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum oxide (TiAlO), titanium silicon aluminum (TiSiAl), titanium tungsten (TiW), titanium tungsten nitride (TiWN), aluminum nitride (AlNx), or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the materials of the third metal layer 63 and the fourth metal layer 642 may be the same or different, wherein the materials of the third metal layer 63 and the fourth metal layer 642 may each include molybdenum, molybdenum nitride (MoN), molybdenum tungsten (MoW), tungsten, or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the material of the absorption layer 641 may include titanium, titanium nitride (TiN), platinum, gold, nickel, niobium (Nb), an alloy thereof or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the materials of the first passivation layer 643 and the second passivation layer 645 may be the same or different, wherein the materials of the first passivation layer 643 and the second passivation layer 645 may each include silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, resin, polymer, photoresist material or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the material of the sensing layer 644 may include amorphous silicon, vanadium oxide (VOx), yttrium barium copper oxide (YBaCuO), silicon germanium oxide (GeSiO), silicon germanium (SiGe), bismuth lanthanum strontium manganese oxide (BiLaSrMnO) or a combination thereof, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the sensing layer 644 includes a thermistor, but the present disclosure is not limited thereto.

[0095] In one embodiment of the present disclosure, Figure 5A and Figure 5BAs shown, the cover unit 3 may include: a substrate 31; a first optical film 32, disposed on a side of the substrate 31 away from the circuit substrate 2; a second optical film 33, disposed on a side of the substrate 31 close to the circuit substrate 2; and a second bonding material B2, disposed on the substrate 31. The first optical film 32 and the second optical film 33 may be used to reduce the reflection of the incident light and / or block the light of the unnecessary wavelength range, so as to improve the transmittance of the light within the specified wavelength range, thereby improving the sensing effect of the sensing element 5. In one embodiment of the present disclosure, at least one of the first optical film 32 and the second optical film 33 may be selected, for example, the cover unit 3 may contain the first optical film 32 but not the second optical film 33; or, the cover unit 3 may contain the second optical film 33 but not the first optical film 32; or, the cover unit 3 may contain the first optical film 32 and the second optical film 33. In one embodiment of the present disclosure, the substrate 31 may have a recess 311, wherein the second optical film 33 may be disposed in the recess 311, but the present disclosure is not limited thereto. In the present disclosure, the material of the substrate 31 may include silicon, germanium (Ge), zinc sulfide (ZnS), zinc selenide (ZnSe), gallium arsenide (GaAs), chalcogenide (Chalcogenide) or a combination thereof, but the present disclosure is not limited thereto. In the present disclosure, the materials of the first optical film 32 and the second optical film 33 may be the same or different, wherein the materials of the first optical film 32 and the second optical film 33 may each include germanium (Ge), zinc sulfide (ZnS), zinc selenide (ZnSe), magnesium fluoride (MgF2), beryllium fluoride (BeF2), potassium chloride, arsenic trisulfide (As2S3) or a combination thereof, but the present disclosure is not limited thereto.

[0096] Fig. 6A It is a schematic top view of a carrier according to an embodiment of the present disclosure. Figure 6B FIG. 4 is a bottom view of a circuit substrate according to an embodiment of the present disclosure. Figure 6C FIG. 1 is a top view of a carrier and a circuit substrate after being assembled in accordance with an embodiment of the present disclosure. FIG. 6A to FIG. 6C The carrier and circuit substrate in FIG. 2A to FIG. 2C Similar, except for the following differences.

[0097] In one embodiment of the present disclosure, FIG. 6A to FIG. 6C As shown in the figure, when viewed from the top view direction Z of the carrier 1 or the circuit substrate 2, the carrier portion CP of the carrier 1 and the circuit substrate 2 may be rectangular, but the present disclosure is not limited thereto. Although not shown in the figure, in other embodiments of the present disclosure, the shapes of the carrier portion CP of the carrier 1 and the circuit substrate 2 are not limited to rectangular. FIG. 2A to FIG. 2C The circle shown, and FIG. 6A to FIG. 6CIn addition to the rectangle shown, the shape of the carrier portion CP of the carrier 1 or the circuit substrate 2 can be designed as needed, such as an ellipse, a prism or other suitable shapes. In one embodiment of the present disclosure, the shapes of the carrier portion CP of the carrier 1 and the circuit substrate 2 can be the same or different.

[0098] In this disclosure, due to FIG. 6A to FIG. 6C The carrier 1 and the circuit substrate 2 in FIG. 2A to FIG. 2C Similar, therefore, Figure 3A and Figure 3B The carrier 1 and the circuit substrate 2 are also considered FIG. 6A to FIG. 6C The cross-sectional schematic diagram of the line segment BB', the detailed features of which can be described above, will not be repeated here.

[0099] Fig. 7A It is a schematic top view of a carrier according to an embodiment of the present disclosure. Figure 7B FIG. 4 is a bottom view of a circuit substrate according to an embodiment of the present disclosure. Figure 7C The figure is a top view schematically showing an assembled carrier and a circuit substrate according to an embodiment of the present disclosure. Fig. 8A and Figure 8B FIG. 1 is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Fig. 8A and Figure 8B The carrier and circuit substrate in FIG. 7A to FIG. 7C A schematic cross-sectional view of the line segment C-C'. In addition, FIG. 7A to FIG. 7C The carrier and circuit substrate in FIG. 2A to FIG. 2C resemblance, Fig. 8A and Figure 8B The manufacturing method and Figure 3A and Figure 3B Similar, except for the following differences.

[0100] In one embodiment of the present disclosure, a method for manufacturing an electronic device may include the following steps: providing a carrier 1 and a circuit substrate 2, wherein: Fig. 7A and Figure 7B As shown, the carrier portion CP of the carrier 1 may include a plurality of first marks M1, the circuit substrate 2 may include a plurality of second marks M2 and a plurality of electronic units E, in the top view direction Z of the carrier 1, the second marks M2 and the electronic units E are separated from each other, and the electronic units E are detected and judged to be normal or defective. Here, Figure 7B The defective electronic unit E2 is represented by a black filling pattern. In one embodiment of the present disclosure, Fig. 7A and Figure 7BAs shown, in the top view direction of the carrier 1 or the circuit substrate 2, the first mark M1 does not overlap with the limiting portion 11 of the carrier 1, and the second mark M2 does not overlap with the electronic unit E. Next, a plurality of cover units 3 are provided on the carrier 1. In one embodiment of the present disclosure, the cover unit 3 may correspond to a normal electronic unit E1, and the cover unit 3 may not be provided on the carrier 1 at the corresponding position of the defective electronic unit E2, so that the waste of the cover unit 3 can be reduced, thereby achieving the effect of reducing the manufacturing cost.

[0101] Afterwards, if Fig. 8A As shown, the circuit substrate 2 is disposed on the cover unit 3 so that the first mark M1 of the carrier 1 and the second mark M2 of the circuit substrate 2 overlap in the top view direction Z of the carrier 1. In one embodiment of the present disclosure, Fig. 7A As shown, the carrier 1 may not include Figure 2A Therefore, the carrier 1 and the circuit substrate 2 can be temporarily fixed on the pressing machine 4 by electrostatic adsorption, pore vacuum grabbing or other suitable methods, so that the first mark M1 of the carrier 1 and the second mark M2 of the circuit substrate 2 overlap in the top view direction Z of the carrier 1. Then, the circuit substrate 2 and the cover unit 3 are evacuated. In more detail, for example, the circuit substrate 2 and the carrier 1 provided with the cover unit 3 can be placed in a reaction chamber (not shown) first, and then the reaction chamber is evacuated, but the present disclosure is not limited thereto.

[0102] Then, if Figure 8B As shown, the cover unit 3 and the circuit substrate 2 are pressed together to fix the cover unit 3 and the circuit substrate 2 to each other, thereby forming a Figure 7C In more detail, the cover plate unit 3 and the circuit substrate 2 can be brought into contact by moving the press machine 4, and then the step of pressing the cover plate unit 3 and the circuit substrate 2 can be performed. Figure 5B As shown, no further details are given here.

[0103] In one embodiment of the present disclosure, Fig. 7A and Figure 7B As shown in the figure, when viewed from the top view direction Z of the carrier 1 or the circuit substrate 2, the carrier portion CP of the carrier 1 and the circuit substrate 2 may be rectangular, but the present disclosure is not limited thereto. Although not shown in the figure, in other embodiments of the present disclosure, the shapes of the carrier portion CP of the carrier 1 and the circuit substrate 2 are not limited to rectangular. FIG. 2A to FIG. 2C The circle shown, and FIG. 7A to FIG. 7C In addition to the rectangular shape shown, the outer shape of the carrier portion CP of the carrier 1 or the circuit substrate 2 can be designed as needed, for example, it can be an ellipse, a prism or other suitable shapes.

[0104] In this embodiment, except for the above-mentioned differences, the materials and detailed features of the carrier 1 , the cover unit 3 and the circuit substrate 2 are as described above and will not be described in detail here.

[0105] The present disclosure can reduce the waste of cover plate unit 3 by not setting the cover plate unit 3 at the corresponding position of the defective electronic unit E2, thereby reducing the manufacturing cost. Alternatively, the present disclosure can improve the vacuum effect after the cover plate unit 3 and the circuit substrate 2 are assembled by setting a spacer SP.

[0106] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for manufacturing an electronic device, characterized in that: The following steps are involved: A carrier and a circuit substrate are provided, wherein the carrier includes a plurality of spacers, the circuit substrate includes a plurality of electronic units, and the electronic units are detected and judged to be normal or defective; providing a plurality of cover plate units on the carrier; The circuit substrate is disposed on the cover units so that the spacers support the circuit substrate, wherein a gap is provided between the circuit substrate and the cover units, and the cover units correspond to the normal electronic units; evacuating the gap between the circuit substrate and the cover plate units; Moving the spacers to bring the cover units and the circuit substrate into contact with each other; and The cover plate units and the circuit substrate are pressed together to fix the cover plate units and the circuit substrate to each other.

2. The manufacturing method according to claim 1, characterized in that: The carrier also includes a plurality of fixing members, wherein the fixing members fix the carrier and the circuit substrate before the vacuuming step and release the fixing after the vacuuming step starts.

3. The manufacturing method according to claim 1, characterized in that: The carrier further comprises a plurality of accommodating spaces respectively corresponding to the spacers, wherein in the step of moving the spacers, the spacers are partially moved to the accommodating spaces.

4. The manufacturing method according to claim 1, characterized in that: The carrier also includes a plurality of limiting portions corresponding to the cover plate units.

5. The manufacturing method according to claim 1, characterized in that: The step of inspecting the electronic units includes inspecting the appearance of the electronic units and conducting electrical tests.

6. The manufacturing method according to claim 1, characterized in that: The carrier comprises a carrying portion, and the cover plate units are arranged on the carrier, wherein the carrying portion of the carrier and the circuit substrate are respectively rectangular.

7. The manufacturing method according to claim 1, characterized in that: The carrier includes a plurality of first marks, and the circuit substrate includes a plurality of second marks, wherein, before the step of pressing the cover units and the circuit substrate, the manufacturing method further includes: in the top view direction of the carrier, making the first marks of the carrier overlap with the second marks of the circuit substrate.

8. The manufacturing method according to claim 1, characterized in that: Before providing the cover unit on the carrier, the manufacturing method further includes: forming a first bonding material on the electronic units, and forming a second bonding material on a substrate of the cover units.

9. The manufacturing method according to claim 8, characterized in that: After the step of pressing the cover units and the circuit substrate, the first bonding material is bonded with the second bonding material to form a third bonding material.

10. A method for manufacturing an electronic device, characterized in that: The following steps are involved: A carrier and a circuit substrate are provided, wherein the carrier includes a plurality of first marks, the circuit substrate includes a plurality of second marks and a plurality of electronic units, the second marks and the electronic units are separated from each other in a top view direction of the carrier, and the electronic units are detected and judged to be normal or defective; providing a plurality of cover plate units on the carrier; The circuit substrate is disposed on the cover units so that the first marks of the carrier overlap with the second marks of the circuit substrate in a top view direction of the carrier, wherein the cover units correspond to the normal electronic units; evacuating the circuit substrate and the cover plate units; and The cover plate units and the circuit substrate are pressed together to fix the cover plate units and the circuit substrate to each other.

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