Contact structure and forming method thereof

Abstract

Contact structures and methods of forming the same are provided. A method of forming a contact structure according to the present disclosure includes: receiving a workpiece including a conductive feature embedded in a first dielectric layer; treating the workpiece with a nitrogen-containing plasma; after the processing, depositing a first etch stop layer (ESL) over the workpiece; depositing a second ESL over the first ESL; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, and the first ESL to expose the conductive feature; and forming a contact via in the opening. The first ESL includes aluminum nitride or silicon carbonitride, and the second ESL includes aluminum oxide or silicon oxycarbide.

Description

Technical Field

[0001] Embodiments of the present application provide a contact structure and a method for forming the same. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can support more and more complex and advanced functions at the same time. Accordingly, there is a continuous trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved to a large extent by reducing the size of semiconductor ICs (e.g., minimum feature size), thereby improving production efficiency and reducing related costs. However, this scaling has also led to increased complexity in semiconductor manufacturing processes. Therefore, the continued progress of semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and technology.

[0003] As device geometries continue to shrink, back-end-of-line (BEOL) interconnect structures are subject to tighter power, performance, and area (PPA) process windows and requirements. Etch stop layers in BEOL play an important role in reducing leakage, improving adhesion, improving resistance-capacitance matching, or reducing resistance-capacitance delay. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for forming a contact structure is provided, comprising: receiving a workpiece comprising a conductive component embedded in a first dielectric layer; treating the workpiece with a nitrogen-containing plasma; after the treatment, depositing a first etch stop layer over the workpiece; depositing a second etch stop layer over the first etch stop layer; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, and the first etch stop layer to expose the conductive component; and forming a contact through-hole in the opening, wherein the first etch stop layer comprises aluminum nitride or silicon carbonitride, and wherein the second etch stop layer comprises aluminum oxide or silicon carbide oxide.

[0005] According to another aspect of an embodiment of the present application, a contact structure is provided, comprising: a conductive component embedded in a first dielectric layer; a first etch stop layer located above the conductive component and the first dielectric layer; a second etch stop layer located above the first etch stop layer; a second dielectric layer located above the second etch stop layer; and a contact via extending through the second dielectric layer, the second etch stop layer, and the first etch stop layer to connect to the conductive component, wherein the first etch stop layer comprises aluminum nitride or silicon carbonitride, and wherein the second etch stop layer comprises aluminum oxide or silicon carbide.

[0006] According to another aspect of an embodiment of the present application, a method for forming a contact structure is provided, comprising: receiving a workpiece comprising a conductive component embedded in a first dielectric layer; depositing a first etch stop layer over the workpiece so that the first etch stop layer is in direct contact with the conductive component and a top surface of the first dielectric layer; depositing a second etch stop layer over the first etch stop layer; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, and the first etch stop layer to expose the conductive component; and forming a contact through-hole in the opening, wherein the first etch stop layer comprises a metal oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a flow chart of a method 100 for forming a contact structure according to one or more aspects of the present disclosure;

[0009] Figure 2-Figure 16 According to one or more aspects of the present disclosure, Figure 1 Partial cross-sectional views of the workpiece at various stages of manufacturing;

[0010] Fig.17 is a flow chart of a method 400 for forming a contact structure according to one or more aspects of the present disclosure;

[0011] Figure 18-Figure 25 According to one or more aspects of the present disclosure, Fig.17 Partial cross-sectional views of the workpiece at various stages of manufacturing;

[0012] Fig.26 A partial cross-sectional view of a fin field effect transistor (FinFET) 500 and contact structures connected thereto according to one or more aspects of the present disclosure is shown;

[0013] Fig. 27 A partial cross-sectional view of a full-all-around-gallon (GAA) transistor 600 and contact structures connected thereto according to one or more aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range that take into account variations inherently caused during manufacturing as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having features associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, for example, within + / -10% of the described number. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with the deposited material layer is + / -15%. The source / drain region may refer to the source or drain individually or collectively, depending on the context.

[0017] As device dimensions continue to shrink, the industry is striving to meet Moore's Law. As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a larger role in meeting power, performance, and area requirements. For example, BEOL interconnect structures can include low dielectric constant (low-k) dielectric layers to reduce parasitic capacitance. To achieve etch endpoint detection, an etch stop layer (ESL) that is more etch-resistant than the low-k dielectric layer can be deposited to provide different etch rates. When applied to device structures with fine pitch metals, thick metal structures, radio frequency (RF) devices, and high-performance computing (HPC) devices, existing etch stop layers may not have a large enough process window.

[0018] The present disclosure provides several etch stop layer (ESL) structures to meet different device performance requirements. When used above a copper conductive component in a dielectric layer, the copper conductive component and the dielectric layer are first plasma treated. A metal nitride layer or a nitrogen-doped silicon carbide layer can be deposited above the copper conductive component as a lower ESL. A metal oxide layer or an oxygen-doped silicon carbide layer can be deposited above the lower ESL as an upper ESL. In some embodiments, where the lower ESL includes a metal nitride and the upper ESL includes a metal oxide, an intermediate ESL can be deposited to improve the adhesion between the lower ESL and the upper ESL. When used above a tungsten conductive component in a dielectric layer, a metal oxide layer can be deposited above the tungsten conductive component and the dielectric layer as a lower ESL to improve adhesion. A metal nitride layer or another metal oxide layer can be deposited above the lower ESL as an upper ESL.

[0019] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 and Fig.17 1 is a flowchart illustrating methods 100 and 400 for forming contact structures on workpiece 200. Methods 100 and 400 are merely examples and are not intended to limit the present disclosure to the content explicitly shown in method 100 or method 400. Additional steps may be provided before, during, and after method 100 or method 400, and some of the steps described may be replaced, removed, or changed in order for additional embodiments of method 100 or method 400. For simplicity, not all steps are described in detail here. Figure 2-Figure 16 Describing method 100, Figure 2-Figure 16 is a partial cross-sectional view of a workpiece 200 at different stages of manufacture according to an embodiment of the method 100. Figure 18-Figure 25 Describing method 400, Figure 18-Figure 254 is a partial cross-sectional view of a workpiece 200 at different stages of manufacturing according to an embodiment of method 400. Since the workpiece 200 will be manufactured into a semiconductor structure 200 after the manufacturing process is completed, the workpiece 200 can be referred to as a semiconductor structure 200 as required by the context. In addition, throughout the present application and different embodiments, unless otherwise specified, the same reference numerals represent the same features with similar structures and compositions. The source / drain region can refer to the source or drain individually or collectively as required by the context.

[0020] refer to Figure 1 and Figure 2 , the method 100 includes a frame 102, wherein a workpiece 200 is received, the workpiece 200 including a first contact feature 204 disposed in a first dielectric layer 202. The first contact feature 204 includes copper (Cu), and may also include cobalt (Co) or nickel (Ni). The first contact feature 204 may be a metal line, a contact via, or a source / drain contact. The first dielectric layer 202 may be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. In some embodiments, the first dielectric layer 202 may include silicon oxide, or include a low-k dielectric material having a k value (dielectric constant) less than the k value of silicon oxide (which is approximately 3.9). In some embodiments, the low-k dielectric material includes a porous organic silicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbon nitride (SiOCN), spin-on silicon-based polymer dielectrics, or combinations thereof. Although not explicitly shown in the figure, the first contact feature 204 can be separated from the first dielectric layer 202 by a barrier layer. The barrier layer can include titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN), or tantalum nitride (TaN). Figure 2 As shown in FIG. 1 , by a planarization process, the top surfaces of the first contact member 204 and the first dielectric layer 202 may be coplanar.

[0021] refer to Figure 1 and Figure 2, the method 100 includes a block 104, wherein a plasma treatment 300 is applied to the top surface of the workpiece 200. In order to passivate the top surface of the first contact member 204 and improve the adhesion between the first contact member 204 and the lower ESL 208, the top surface of the workpiece 200 is treated with the plasma treatment 300. The plasma treatment 300 includes a plasma using ammonia (NH3) and nitrogen (N2), and can produce a nitrogen-rich top surface 206 on the workpiece 200. Prior to the plasma treatment 300, the top surface of the first contact member 204 may be oxidized to include copper oxide due to a planarization process or exposure to oxygen, and the top surface of the first dielectric layer 202 may include dangling bonds, oxygen bonds, and alkyl groups. Experimental results show that the plasma treatment 300 can reduce the surface copper oxide to copper, remove dangling bonds, or replace alkyl groups with nitrogen atoms. In addition, the plasma treatment 300 at the block 104 can produce low-orbit metal-nitrogen bonds, such as nitrogen-copper bonds. Surface reduction and nitridation caused by plasma treatment promotes adhesion and reduces electromigration of copper. In some embodiments, the ratio of the flow rate of nitrogen (N2) to the flow rate of ammonia (NH3) in plasma treatment 300 can be between about 45 and about 15.

[0022] refer to Figure 1 and Figure 3 , method 100 includes box 106, in which a lower etch stop layer (ESL) 208 is deposited over the workpiece 200. In some embodiments, the lower ESL 208 may include a metal nitride, such as aluminum nitride (AlN). When the lower ESL 208 includes aluminum nitride (AlN), the lower ESL 208 may be deposited using atomic layer deposition (ALD), which includes multiple thermal ALD cycles at a temperature between about 300°C and about 400°C. The deposition of the lower ESL 208 may include using an aluminum-containing precursor such as trimethylaluminum (Al(CH3)3), and a nitrogen-containing precursor such as ammonia (NH3). In some alternative embodiments, the lower ESL 208 may be deposited using chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD). In embodiments where the lower ESL 208 includes aluminum nitride (AlN), the lower ESL 208 may have a thickness of about 1000 nm. Peace Since the lower ESL 208 is deposited on the nitrogen-rich top surface 206 , the bottom surface of the lower ESL 208 has a greater nitrogen content than the top surface of the lower ESL 208 .

[0023] refer to Figure 1 and Figure 4, the method 100 includes an optional block 108, in which an intermediate ESL 210 is deposited above the workpiece 200. The operation at block 108 is optional. When implemented, the intermediate ESL 210 is deposited directly on the lower ESL 208 to serve as an adhesion promoting layer between the lower ESL 208 and the upper ESL 212 (described below). In some embodiments, the intermediate ESL 210 includes oxygen-doped silicon carbide (SiC:O or O-SiC). The intermediate ESL 210 can be deposited using CVD or PECVD using tetramethylsilane (Si(CH3)4), silane (SiH4), trimethylsilane (Si(CH3)3H), carbon dioxide (CO2), xenon (Xe), oxygen (O2), etc. It is worth noting that when forming the intermediate ESL 210, it is purposefully and intentionally deposited using an oxygen atomic percentage between about 20% and about 30%. The middle ESL 210 can not only enhance the adhesion between the lower ESL 208 and the upper ESL 212, but also suppress the hillock formation in the first metal contact part 204. When the middle ESL 210 is implemented, it can have a thickness of about Peace This thickness range is not insignificant. When the thickness of the middle ESL 210 is less than When the thickness of the middle ESL 210 is greater than In some embodiments, the operation at block 108 is omitted, and the upper ESL 212 is deposited directly on the lower ESL 208.

[0024] refer to Figure 1 and Figure 5 , method 100 includes an optional block 110, in which an upper ESL 212 is deposited over workpiece 200. The operation at block 110 is also optional. When implemented, upper ESL 212 is deposited directly on intermediate ESL 210 (when the operation at block 108 is implemented) or on lower ESL 208 (when the operation at block 108 is not implemented). Upper ESL 212 includes a metal oxide. In some embodiments, upper ESL 212 may include aluminum oxide (AlO), hafnium silicate (HfSiO4), or hafnium aluminum oxide (HfAlO). In one embodiment, upper ESL 212 includes aluminum oxide. Upper ESL 212 may be deposited using CVD, ALD, PECVD, or plasma enhanced ALD (PEALD). Upper ESL 212 and lower ESL 208 may have the same thickness to facilitate etching endpoint detection. In some cases, upper ESL 212 may have a thickness of about 100 Å. Peace For ease of reference, the lower ESL 208, the middle ESL 210, and the upper ESL 212 may be collectively referred to as the first ESL stack 2002. Although not explicitly shown, oxygen-doped silicon carbide (SiC:O or O-SiC) may be deposited over the upper ESL 212 to improve adhesion to a subsequently formed low-k dielectric layer (e.g., the second dielectric layer 230).

[0025] refer to Figure 1 and Figure 6 , the method 100 includes block 112, where a second dielectric layer 230 is deposited over the workpiece 200. In some embodiments, the composition of the second dielectric layer 230 can be similar to the composition of the first dielectric layer 202. In some embodiments, the second dielectric layer 230 can be deposited over the upper ESL 212 using spin coating, CVD, or flowable chemical vapor deposition (FCVD). In some cases, in order to improve the quality and density of the second dielectric layer 230 to withstand subsequent patterning operations, an annealing process can be performed to improve the quality of the second dielectric layer 230. After the deposition of the second dielectric layer 230, a planarization process, such as a chemical mechanical polishing (CMP) process, can be performed on the second dielectric layer 230 to provide a flat top surface.

[0026] refer to Figure 1 and Figure 7, the method 100 includes block 114, where a first conductive feature 240 is formed through the second dielectric layer 230, the upper ESL 212, the middle ESL 210, and the lower ESL 208. The operations at block 114 may include: forming a dual damascene opening through the second dielectric layer 230, the upper ESL 212, the middle ESL 210 (when formed), and the lower ESL 208 to expose the first contact feature 204; and, forming the first conductive feature 240 in the dual damascene opening. In an exemplary process, a first patterned mask is first formed by a photolithography process, and a dry etching process is performed to form a via opening through the second dielectric layer 230 and the first ESL stack 2002. A second patterned mask is then formed, and another dry etching process is performed to form a trench opening overlapping the via opening. The dry etching at box 114 can be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, CH3F, C4H8, C4F6, and / or C2F6), carbon-containing gas (e.g., CO, CH4, and / or C3H8), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In some embodiments, the fluorine in the dry etching process can form compounds or polymers with the upper ESL 212, the lower ESL 208, and the first contact member 204. These compounds or polymers can be redeposited in the dual-damascene opening. In order to remove these compounds and polymers, a wet cleaning process can be implemented. In some cases, the wet cleaning process can include ammonium hydroxide (NH4OH) and a copper corrosion inhibitor. Copper inhibitors may include, for example, 5-methyl-1H-benzotriazole (MBTA) and 1H-benzotriazole (BTA).

[0027] After forming the dual damascene opening, block 114 includes depositing a barrier layer 242 in the dual damascene opening. In some embodiments, the barrier layer 242 may include a metal nitride, such as titanium nitride, cobalt nitride, manganese nitride, nickel nitride, tungsten nitride, or tantalum nitride. In one embodiment, the barrier layer 242 includes titanium nitride. The barrier layer 242 may be deposited using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or plasma enhanced ALD (PEALD). After depositing the barrier layer 242, a metal fill layer 244 may be deposited over the barrier layer 242. The metal fill layer 244 may include copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), or tungsten (W). In one embodiment, the metal fill layer 244 includes copper (Cu). The metal fill layer 244 may be deposited using PVD, electroplating, or chemical plating. As an example, the metal fill layer 244 may be deposited using electroplating. In this exemplary process, a seed layer may be deposited over the workpiece 200 using PVD or CVD. The seed layer may include titanium, copper, or both. Copper is then deposited over the seed layer using electroplating. After the barrier layer 242 and the metal fill layer 244 are deposited, the workpiece 200 is planarized to expose the second dielectric layer 230, thereby forming the first conductive feature 240. Planarization may include chemical mechanical polishing (CMP). Figure 7 As shown in FIG. 2 , the workpiece 200 is planarized until the planar top surface of the workpiece 200 includes the top surfaces of the second dielectric layer 230 , the barrier layer 242 , and the metal filling layer 244 .

[0028] As shown by the dashed lines, the through-hole portion of the first conductive feature 240 has a varying sidewall profile. Since the lower ESL 208 and the upper ESL 212 etch more slowly and their etching can produce compounds and polymers that can be redeposited above the dual-damascene opening, the sidewalls extending through the first ESL stack 2002 are substantially straight along the Z direction. This is not the case for the second dielectric layer 230. First, the etching rate of the second dielectric layer 230 is much faster than the etching rate of the lower ESL 208 and the upper ESL 212. During the dry etching of the second dielectric layer 230, the byproducts are easily removed and will not be redeposited. Therefore, the sidewalls extending through the second dielectric layer 230 can taper downward. As shown in FIG. Figure 7 As shown in FIG. 2 , the sidewall profile in the via portion changes from a downward taper to a smaller downward taper along the Z direction from the second dielectric layer 230 to the first contact member 204 .

[0029] The method 100 may be applied to form an alternative ESL stack above the first contact component 204. Figure 8-Figure 10In some embodiments, the operation at block 108 is omitted and the intermediate ESL 210 is not deposited on the lower ESL 208. Figure 8 , at block 110 , an upper ESL 212 is deposited directly on the lower ESL 208 . Figure 8 The lower ESL 208 and the upper ESL 212 in the second ESL stack 2004 may be collectively referred to as a second ESL stack 2004. Then, the method 100 continues to block 112, which forms a second dielectric layer 230 (eg, Fig. 9 At block 114, a first conductive feature 240 is formed through the second dielectric layer 230 and the second ESL stack 2004 to contact the first contact feature 204. Since the lower ESL 208 is deposited on the nitrogen-rich top surface 206, the bottom surface of the lower ESL 208 has a greater nitrogen content than the top surface of the lower ESL 208.

[0030] Reference now Figure 11-13 In some embodiments, the operation at block 110 is omitted and the intermediate ESL 210 is deposited on the lower ESL 208. Fig.11 , after the intermediate ESL 210 is deposited on the lower ESL 208 at block 108 , the method 100 skips block 110 and continues to block 112 . Fig.12 or Fig.13 The lower ESL 208 and the middle ESL 210 in the embodiment may be collectively referred to as a third ESL stack 2006. At block 112, a second dielectric layer 230 is deposited directly on the third ESL stack 2006 (eg, Fig.12 At block 114, a first conductive feature 240 is formed through the second dielectric layer 230 and the third ESL stack 2006 to contact the first contact feature 204. Since the lower ESL 208 is deposited on the nitrogen-rich top surface 206, the bottom surface of the lower ESL 208 has a greater nitrogen content than the top surface of the lower ESL 208.

[0031] Then refer to Figure 14-16. In some embodiments, a carbide ESL 214 is deposited at box 106 to replace the lower ESL 208. In some embodiments, the carbide ESL 214 includes nitrogen-doped silicon carbide (SiC:N or N-SiC). The carbide ESL 214 can be deposited using CVD or PECVD using tetramethylsilane (Si(CH3)4), silane (SiH4), trimethylsilane (Si(CH3)3H), ammonia (NH3), xenon (Xe), nitrogen (N2), etc. It is worth noting that when forming the carbide ESL 214, it is purposefully and intentionally deposited using a nitrogen atomic percentage between about 20% and about 30%. In some cases, the thickness of the carbide ESL 214 can be about Peace Since the carbide ESL 214 is deposited on the nitrogen-rich top surface 206, the bottom surface of the carbide ESL 214 has a greater nitrogen content than the top surface of the carbide ESL 214. At block 108, the intermediate ESL 210 is deposited directly on the carbide ESL 214. The operation at block 110 is omitted and the upper ESL 212 is not deposited. Fig.15 The carbide ESL 214 and the intermediate ESL 210 in the fourth ESL stack 2008 may be collectively referred to as a fourth ESL stack 2008. In these embodiments, the intermediate ESL 210 is not used to improve adhesion between the lower ESL 208 and the upper ESL 212. Instead, the intermediate ESL 210 is used to provide etching selectivity. Therefore, when deposited over the carbide ESL 214, the intermediate ESL 210 may have a thickness similar to that of the carbide ESL 212. Then, the method 100 continues to block 112, which is formed on the fourth ESL stack 2008 (e.g., Fig.15 1 and 1 . A second dielectric layer 230 is formed above the first contact member 204 (shown in FIG. 1 ). At block 114, a second conductive component 250 is formed through the second dielectric layer 230 and the fourth ESL stack 2008 to contact the first contact member 204. Like the first conductive component 240, the second conductive component also includes a barrier layer 242 and a metal fill layer 244. However, the second conductive component 250 has a different sidewall profile from the first conductive component 240. Since the carbide ESL 214 and the middle ESL 210 etch faster than the lower ESL 208 or the upper ESL 212, and their etching does not produce compounds or polymers, the sidewall profile of the through-hole portion of the second conductive component 250 tapers downward substantially uniformly.

[0032] Unlike the method 100 which is more suitable for a first contact member 204 containing copper, Fig.17 The method 400 is more suitable for contact parts formed of refractory metals. Figure 18-Figure 25 To describe method 400, Figure 18-Figure 25Included are partial cross-sectional views of workpiece 200 at various stages of method 400 .

[0033] refer to Fig.17 and Fig.18 , method 100 includes frame 402, in which a workpiece 200 is received, and the workpiece 200 includes a second contact member 205 disposed in a first dielectric layer 202. The second contact member 205 is formed of a refractory metal such as tungsten (W) and ruthenium (Ru). In one embodiment, the second contact member 205 includes tungsten (W). The second contact member 205 can be a metal line, a contact via, or a source / drain contact. The first dielectric layer 202 has been described above, and for the sake of brevity, its detailed description will not be repeated here. Although not explicitly shown, the second contact member 205 can be separated from the first dielectric layer 202 by a barrier layer. The barrier layer may include titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN), or tantalum nitride (TaN). Since the second contact member 205 is less affected by electromigration, the barrier layer can be omitted. As Fig.18 As shown in FIG. 1 , by the planarization process, the top surfaces of the second contact member 205 and the first dielectric layer 202 may be coplanar.

[0034] refer to Fig.17 and Fig.19 , the method 400 includes a block 404, in which a first ESL 218 is deposited over the workpiece 200. The first ESL 218 includes a metal oxide. In one embodiment, the first ESL 218 may include aluminum oxide (AlO), hafnium silicate (HfSiO4), or hafnium aluminum oxide (HfAlO). In one embodiment, the first ESL 218 includes aluminum oxide. The first ESL 218 may be deposited by CVD, ALD, PECVD, or plasma enhanced ALD (PEALD) using trimethylaluminum (TMA, Al(CH3)3), aluminum chloride, nitrous oxide (N2O), or oxygen (O2). In some embodiments, the oxygen content in the first ESL 218 may be varied over its depth by varying the flow rate of oxygen-containing precursors such as nitrous oxide (N2O) and oxygen (O2). For example, to enhance adhesion to a dielectric layer containing silicon oxide (eg, first dielectric layer 202 or second dielectric layer 230), the oxygen content of the contact surface of first ESL 218 may be increased. In some cases, first ESL 218 may have a thickness of about 100 nm. Peace The thickness between.

[0035] refer to Fig.17 and Fig. 20, method 400 includes an optional block 406, in which a second ESL 220 is deposited over the workpiece 200. The operation at block 406 is optional and may be omitted entirely. The second ESL 220 may include a metal nitride. In some embodiments, the second ESL 220 includes aluminum nitride (AlN). When the second ESL 220 includes aluminum nitride (AlN), the second ESL 220 may be deposited using atomic layer deposition (ALD), which includes multiple thermal ALD cycles at a temperature between about 300° C. and about 400° C. The deposition of the second ESL 220 may include using an aluminum-containing precursor such as trimethylaluminum (TMA, Al(CH3)3), and a nitrogen-containing precursor such as ammonia (NH3). In some alternative embodiments, the second ESL 220 may be deposited using chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD). The second ESL 220 and the first ESL 218 may have the same thickness to facilitate etching endpoint detection. In some embodiments, the second ESL 220 may have a thickness of about Peace The thickness between Fig. 20 , the second ESL 220 is deposited directly on the first ESL 218. The first ESL 218 and the second ESL 220 may be collectively referred to as a fifth ESL stack 2010.

[0036] refer to Fig.17 and Fig.21 , the method 400 includes block 408, where a second dielectric layer 230 is deposited over the workpiece 200. In some embodiments, the composition of the second dielectric layer 230 can be similar to the composition of the first dielectric layer 202. In some embodiments, the second dielectric layer 230 can be deposited over the second ESL 220 using spin coating, CVD, or flowable chemical vapor deposition (FCVD). In some cases, in order to improve the quality and density of the second dielectric layer 230 to withstand subsequent patterning operations, an annealing process can be performed to improve the quality of the second dielectric layer 230. After the deposition of the second dielectric layer 230, a planarization process, such as a chemical mechanical polishing (CMP) process, can be performed on the second dielectric layer 230 to provide a flat top surface.

[0037] refer to Fig.17 and Fig. 22, the method 400 includes a block 410, wherein a first conductive feature 240 is formed through the second dielectric layer 230, the second ESL 220, and the first ESL 218. The operation at block 410 may include: forming a dual damascene opening through the second dielectric layer 230, the second ESL 220, and the first ESL 218 to expose the second contact feature 205; and forming the first conductive feature 240 in the dual damascene opening. In an exemplary process, a first patterned mask is first formed by a photolithography process, and a dry etching process is performed to form a through-hole opening through the second dielectric layer 230 and the fifth ESL stack 2010. Then a second patterned mask is formed, and another dry etching process is performed to form a trench opening overlapping the through-hole opening. The dry etching at box 410 can be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, CH3F, C4H8, C4F6, and / or C2F6), carbon-containing gas (e.g., CO, CH4, and / or C3H8), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In some embodiments, the fluorine in the dry etching process can form compounds or polymers with the second ESL 220, the first ESL 218, and the second contact member 205. These compounds or polymers can be redeposited in the dual-damascene opening. In order to remove these compounds and polymers, a wet cleaning process can be implemented. In some cases, the wet cleaning process can include ammonium hydroxide (NH4OH) and a tungsten corrosion inhibitor. The tungsten inhibitor can include, for example, benzethylammonium chloride. After forming the dual damascene opening, block 410 includes depositing a barrier layer 242 in the dual damascene opening and then depositing a metal fill layer 244. The composition and deposition of the barrier layer 242 and the metal fill layer 244 have been described above and will not be repeated here.

[0038] like Fig. 22 As shown by the dashed lines in , the through-hole portion of the first conductive component 240 has a variable sidewall profile. Since the first ESL 218 and the second ESL 220 etch more slowly and their etching can produce compounds and polymers that can be redeposited above the dual-damascene opening, the sidewalls extending through the fifth ESL stack 2010 along the Z direction are substantially straight. This is not the case for the second dielectric layer 230. The etching rate of the second dielectric layer 230 is much faster than the etching rate of the first ESL 218 and the second ESL 220. During the dry etching of the second dielectric layer 230, the byproducts are easily removed and will not be redeposited. Therefore, the sidewalls extending through the second dielectric layer 230 can taper downward. As shown in FIG. Fig. 22As shown in FIG. 2 , the sidewall profile in the via portion changes from a downward taper to a smaller downward taper along the Z direction from the second dielectric layer 230 to the second contact member 205 .

[0039] The method 400 may be applied to form an alternative ESL stack above the second contact feature 205. Referring now to Figure 23-Figure 25 In some embodiments, block 404 deposits a gradient ESL 2180 instead of the first ESL 218. Although still formed of a metal oxide, the gradient ESL 2180 includes an oxygen concentration gradient. Fig.23 As shown in FIG. 2 , the gradient ESL 2180 includes a bottom surface 222 adjacent to the first dielectric layer 202 and the second contact member 205, and a top surface 224 facing away from the first dielectric layer 202 and the second contact member 205. In the depicted embodiment, the flow rate of the oxygen-containing precursor is controlled such that the oxygen content at the top surface 224 is greater than the oxygen content at the bottom surface 222. In some embodiments, the gradient ESL 2180 may have a thickness between about 100 and about 100 mm. Peace The oxygen content (atomic percent) at the bottom surface 222 of the gradient ESL 2180 can be between about 40% and about 60%, while the oxygen content at the top surface 224 of the gradient ESL 2180 can be between about 60% and about 75%. This increased oxygen content at the top surface 224 is used to improve adhesion with the second dielectric layer 230. The operation at block 406 is omitted, and the second ESL 220 is not deposited on the gradient ESL 2180. Then, the method 400 continues to block 408, which forms the second dielectric layer 230 (such as Fig.24 At block 410, a first conductive feature 240 is formed through the second dielectric layer 230 and the gradient ESL 2180 to contact the second contact feature 205. Fig.25 As shown by the dashed line in FIG. 2 , the through hole portion of the first conductive component 240 has a varying sidewall profile.

[0040] The first ESL stack 2002, the second ESL stack 2004, the third ESL stack 2006, the fourth ESL stack 2008, the fifth ESL stack 2010, and the gradient ESL 2180 are suitable for implementation at different locations in the BEOL interconnect structure. First, since the fifth ESL stack 2010 and the gradient ESL 2180 contact the contact part with an oxygen-containing metal oxide layer, they are more suitable for being formed above the contact part formed by a refractory metal rather than copper (Cu). In contrast, since the first ESL stack 2002, the second ESL stack 2004, the third ESL stack 2006, and the fourth ESL stack 2008 contact the contact part below with an oxygen-free layer such as the lower ESL 208 or the carbide ESL 214, and their formation process includes plasma treatment, they are more suitable for being formed above the contact part formed by copper (Cu). In addition, the cost-effectiveness of reducing parasitic capacitance also plays an important role in selective ESL. The BEOL interconnect structure may include about 5 to about 20 metallization layers. Each metallization layer includes metal features (i.e., vias and metal lines) spaced apart from each other by IMD layers and ESLs. The metallization layers have different thicknesses depending on their distance from the FEOL structure. In the metallization layers closer to the FEOL structure, such as the first 4 to 7 metallization layers with a line spacing greater than 90nm, the total thickness is small and the ESL accounts for a larger percentage of the total thickness. In the metallization layers farther from the FEOL structure, such as the last 6 to 15 metallization layers with a line spacing greater than 90nm, the overall thickness increases sharply and the thickness of the ESL may become negligible. In general, the parasitic capacitance caused by the ESL is proportional to the product of the dielectric constant of the ESL and the thickness of the ESL. Metal nitrides, such as aluminum nitride, have a dielectric constant between about 13 and about 15. Compared with other ESL materials having a dielectric constant less than about 7, metal nitrides seem to be an unlikely choice. However, it has been observed that when used as an ESL, metal nitrides only require a smaller thickness. In some embodiments, the thickness of the metal nitride ESL can be between about one-fifth (1 / 5) and about one-tenth (1 / 10) of the thickness of the silicon nitride ESL or the silicon carbide ESL. The smaller thickness allows the metal nitride ESL (e.g., the lower ESL 208) to produce a smaller capacitance. Since the capacitance caused by the ESL plays a more prominent role in the lower metallization layer, the implementation of the first ESL stack 2002 and the second ESL stack 2004 is more suitable for the first 4-7 metallization layers. Since the capacitance caused by the ESL plays a negligible role in the higher metallization layers, and the deposition of the metal nitride layer is associated with higher costs and slower process times, the implementation of the third ESL stack 2006 is more suitable for the last 6 to 15 metallization layers.

[0041] Fig.26 The implementation of the ESL of the fin field effect transistor (FinFET) 500 is shown. The FinFET 500 includes a fin structure 504 raised from a substrate 502. The fin structure 504 extends longitudinally along the X direction between the source component 506S and the drain component 506D. The portion of the fin structure 504 between the source component 506S and the drain component 506D defines a channel region. A gate structure 508 surrounds the channel region of the fin structure 504. The gate structure 508 extends longitudinally along the Y direction and is defined between two gate spacers 510 along the X direction. A contact etch stop layer (CESL) 512 is disposed above the source component 506S and the drain component 506D. An interlayer dielectric (ILD) layer 514 is disposed above the CESL 512. An ESL 516 is disposed above the gate structure 508, the gate spacer 510, and the ILD layer 514. An IMD layer 518 is disposed above the ESL 516. The source contact 522S extends through the IMD layer 518, the ESL 516, the ILD layer 514, and the CESL 512 to connect to the source feature 506S. The gate contact via 520 extends through the IMD layer 518 and the ESL 516 to connect to the gate structure 508. The drain contact 522D extends through the IMD layer 518, the ESL 516, the ILD layer 514, and the CESL 512 to connect to the drain feature 506D. The ESL 530 is disposed over the IMD layer 518, the source contact 522S, the gate contact via 520, and the drain contact 522D. The IMD layer 532 is disposed over the ESL 530. The first contact via 540, the second contact via 542, and the third contact via 544 extend through the IMD layer 532 and the ESL 530 to be connected to the gate contact via 520, the source contact 522S, and the drain contact 522D, respectively. The ESL 550 is disposed over the IMD layer 532, the first contact via 540, the second contact via 542, and the third contact via 544. The IMD layer 552 is disposed over the ESL 550. The fourth contact via 560, the fifth contact via 562, and the sixth contact via 564 extend through the IMD layer 552 and the ESL 550 to be connected to the first contact via 540, the second contact via 542, and the third contact via 544, respectively.

[0042] In some embodiments, the substrate 502 and the fin structure 504 may include silicon (Si). The source component 506S and the drain component 506D may be n-type or p-type. When it is n-type, it includes silicon (Si) and n-type dopants such as phosphorus (P) or arsenic (as). When it is p-type, it includes silicon germanium (SiGe) and p-type dopants such as boron (B). The gate structure 508 includes an interface layer intersecting the fin structure 504, a gate dielectric layer above the interface layer, and a gate electrode above the gate dielectric layer. The interface layer may include silicon oxide. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. The gate electrode may include titanium nitride, titanium aluminum, titanium aluminum nitride, titanium, tantalum, or tungsten. The gate spacer 510 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, or silicon oxycarbon. The CESL 512 may include silicon nitride or silicon oxynitride. ILD layer 514, IMD layer 518, IMD layer 532, and IMD layer 552 may include porous organic silicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbon nitride (SiOCN), spin-on silicon-based polymer dielectrics, or combinations thereof. Source contact 522S and drain contact 522D may include cobalt (Co), nickel (Ni), or titanium nitride (TiN). Gate contact via 520 may include cobalt (Co), nickel (Ni), tungsten (W), or ruthenium (Ru).

[0043] The first contact via 540 , the second contact via 542 , and the third contact via 544 include tungsten (W).

[0044] The fourth contact via 560 , the fifth contact via 562 , and the sixth contact via 564 include copper (Cu).

[0045] In some embodiments, ESL 516 and ESL 530 may be implemented with first ESL stack 2002, second ESL stack 2004, or third ESL stack 2006 because the underlying contact components are not made of refractory metal. In addition, first ESL stack 2002, second ESL stack 2004, or third ESL stack 2006 provides better etching control because the etching process may produce compounds or polymers that prevent over-etching. In some embodiments, ESL 550 may be implemented with fifth ESL stack 2010 or gradient ESL 2180 because the metal oxide in fifth ESL stack 2010 or gradient ESL 2180 may adhere well to first contact via 540, second contact via 542, and third contact via 544 formed of tungsten (W), and is less affected by electromigration when in contact with the metal oxide. As described above, the fourth ESL stack 2008 may be more suitable for use in a metallization layer located above the FinFET 500 and including a metal line pitch greater than 90 nm.

[0046] Fig. 27The implementation of an ESL to full-circuit galvanometer (GAA) transistor 600 is shown. The GAA transistor 600 includes a vertical stack of channel components 6080 disposed above a substrate 602. The channel component 6080 may also be referred to as a nanostructure. Depending on its cross-sectional shape, it may be referred to as a nanosheet or a nanowire. The channel component 6080 extends between a source component 606S and a drain component 606D along the X direction. A gate structure 610 surrounds each vertical stack of the channel component 6080. The gate structure 610 is laterally spaced apart from the source component 606S or the drain component 606D by a plurality of internal spacer components 612. Above the channel component 6080, the gate structure 610 is sandwiched between two top gate spacers 614. A contact etch stop layer (CESL) 618 is disposed above the source component 606S and the drain component 606D. An interlayer dielectric (ILD) layer 620 is disposed above the CESL 618. The ESL 622 is disposed over the gate structure 610, the top gate spacer 614, and the ILD layer 620. The IMD layer 624 is disposed over the ESL 622. A source contact 632S extends through the IMD layer 624, the ESL 622, the ILD layer 620, and the CESL 618 to connect to the source feature 606S. The gate contact via 630 extends through the IMD layer 624 and the ESL 622 to connect to the gate structure 610. A drain contact 632D extends through the IMD layer 624, the ESL 622, the ILD layer 620, and the CESL 618 to connect to the drain feature 606D. The ESL 636 is disposed over the IMD layer 624, the source contact 632S, the gate contact via 630, and the drain contact 632D. The IMD layer 638 is disposed over the ESL 636. The seventh contact via 640, the eighth contact via 642, and the ninth contact via 644 extend through the IMD layer 638 and the ESL 636 to be connected to the gate contact via 630, the source contact 632S, and the drain contact 632D, respectively. The ESL 650 is disposed over the IMD layer 638, the seventh contact via 640, the eighth contact via 642, and the ninth contact via 644. The IMD layer 652 is disposed over the ESL 650. The tenth contact via 660, the eleventh contact via 662, and the twelfth contact via 664 extend through the IMD layer 652 and the ESL 650 to be connected to the seventh contact via 640, the eighth contact via 642, and the ninth contact via 644, respectively.

[0047] In some embodiments, the substrate 602 and the channel member 6080 may include silicon (Si). The source component 606S and the drain component 606D may be n-type or p-type. When it is n-type, it includes silicon (Si) and n-type dopants such as phosphorus (P) or arsenic (as). When it is p-type, it includes silicon germanium (SiGe) and p-type dopants such as boron (B). The gate structure 610 includes an interface layer intersecting the channel member 6080, a gate dielectric layer above the interface layer, and a gate electrode above the gate dielectric layer. The interface layer may include silicon oxide. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. The gate electrode may include titanium nitride, titanium aluminum, titanium aluminum nitride, titanium, tantalum, or tungsten. The top gate spacer 614 and the inner spacer component 612 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, or silicon oxycarbon. The CESL 618 may include silicon nitride or silicon oxynitride. The ILD layer 620, the IMD layer 624, the IMD layer 638, and the IMD layer 652 may include a porous organic silicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, oxycarbon nitride silicon (SiOCN), spin-on silicon-based polymer dielectrics, or a combination thereof. The source contact 632S and the drain contact 632D may include cobalt (Co), nickel (Ni), or titanium nitride (TiN). The gate contact via 630 may include cobalt (Co), nickel (Ni), tungsten (W), or ruthenium (Ru). The seventh contact via 640, the eighth contact via 642, and the ninth contact via 644 include tungsten (W). The tenth contact via 660, the eleventh contact via 662, and the twelfth contact via 664 include copper (Cu).

[0048] In some embodiments, ESL 622 and ESL 636 may be implemented with first ESL stack 2002, second ESL stack 2004, or third ESL stack 2006 because the underlying contact components are not made of refractory metal. In addition, first ESL stack 2002, second ESL stack 2004, or third ESL stack 2006 provides better etching control because the etching process may produce compounds or polymers that prevent over-etching. In some embodiments, ESL 650 may be implemented with fifth ESL stack 2010 or gradient ESL 2180 because the metal oxide in fifth ESL stack 2010 or gradient ESL 2180 may adhere well to seventh contact via 640, eighth contact via 642, and ninth contact via 644 formed of tungsten (W), and is less affected by electromigration when in contact with the metal oxide. As described above, the fourth ESL stack 2008 may be more suitable for use in a metallization layer located above the GAA transistor 600 and including a metal line pitch greater than 90 nm.

[0049] Therefore, one embodiment of the present disclosure provides a method for forming a contact structure. The method includes: receiving a workpiece including a conductive component embedded in a first dielectric layer; treating the workpiece with a nitrogen-containing plasma; after the treatment, depositing a first etch stop layer (ESL) over the workpiece; depositing a second ESL over the first ESL; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, and the first ESL to expose the conductive component; and forming a contact via in the opening. The first ESL includes aluminum nitride or silicon carbonitride, and the second ESL includes aluminum oxide or silicon oxycarbide.

[0050] In some embodiments, the conductive component includes copper (Cu). In some embodiments, the nitrogen-containing plasma includes ammonia plasma and nitrogen plasma. In some embodiments, the method also includes depositing an intermediate ESL above the first ESL before the deposition of the second ESL. In some cases, the composition of the intermediate ESL is different from the composition of the first ESL or the second ESL. In some embodiments, the intermediate ESL includes oxygen-doped silicon carbide. In some embodiments, the deposition of the intermediate ESL includes using tetramethylsilane, silane, trimethylsilane, carbon dioxide, xenon, oxygen, or a combination thereof. In some embodiments, the first ESL includes a bottom surface closer to the conductive component, and a top surface away from the conductive component, and the nitrogen content at the bottom surface is greater than the nitrogen content at the top surface.

[0051] In another embodiment, a contact structure is provided. The contact structure includes: a conductive component embedded in a first dielectric layer; a first etch stop layer (ESL) located above the conductive component and the first dielectric layer; a second ESL located above the first ESL; a second dielectric layer located above the second ESL; and a contact via extending through the second dielectric layer, the second ESL, and the first ESL to connect to the conductive component. The first ESL includes aluminum nitride or silicon carbonitride, and the second ESL includes aluminum oxide or silicon oxycarbide.

[0052] In some embodiments, the conductive component includes copper. In some embodiments, the contact structure further includes: an intermediate ESL sandwiched between the first ESL and the second ESL. In some embodiments, the intermediate ESL includes silicon oxycarbide. In some embodiments, the conductive component and the top surface of the first dielectric layer are coplanar. In some cases, the first ESL includes a bottom surface closer to the conductive component and a top surface farther from the conductive component, and the nitrogen content at the bottom surface is greater than the nitrogen content at the top surface.

[0053] In another embodiment, a method is provided. The method includes: receiving a workpiece including a conductive component embedded in a first dielectric layer; depositing a first etch stop layer (ESL) over the workpiece such that the first ESL is in direct contact with the conductive component and a top surface of the first dielectric layer; depositing a second ESL over the first ESL; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, and the first ESL to expose the conductive component; and forming a contact via in the opening. The first ESL includes a metal oxide.

[0054] In some embodiments, the conductive component includes tungsten (W). In some embodiments, the first ESL includes aluminum oxide. In some embodiments, the second ESL includes a metal nitride or a metal oxide. In some cases, when the second ESL includes a metal oxide, the oxygen content in the second ESL is greater than the oxygen content in the first ESL. In some embodiments, the second ESL includes aluminum nitride.

[0055] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a contact structure, comprising: receiving a workpiece including a conductive component embedded in a first dielectric layer; treating the workpiece with a nitrogen-containing plasma; After said processing, depositing a first etch stop layer over said workpiece; depositing a second etch stop layer over the first etch stop layer; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, and the first etch stop layer to expose the conductive feature; as well as forming a contact via in the opening, Wherein, the first etching stop layer comprises aluminum nitride or silicon carbonitride, Wherein, the second etching stop layer includes aluminum oxide or silicon oxycarbide.

2. The method according to claim 1, wherein: The nitrogen-containing plasma includes ammonia plasma and nitrogen plasma.

3. The method according to claim 1, further comprising: Prior to said depositing of said second etch stop layer, an intermediate etch stop layer is deposited over said first etch stop layer.

4. The method according to claim 3, wherein: The composition of the intermediate etch stop layer is different from the composition of the first etch stop layer or the second etch stop layer.

5. The method according to claim 3, wherein: The depositing of the intermediate etch stop layer includes using tetramethylsilane, silane, trimethylsilane, carbon dioxide, xenon, oxygen, or a combination thereof.

6. The method according to claim 1, in, The first etch stop layer includes a bottom surface closer to the conductive component and a top surface farther from the conductive component, Wherein, the nitrogen content at the bottom surface is greater than the nitrogen content at the top surface.

7. A contact structure comprising: a conductive component embedded in the first dielectric layer; a first etch stop layer located above the conductive component and the first dielectric layer; a second etch stop layer, located above the first etch stop layer; a second dielectric layer located above the second etch stop layer; as well as a contact via extending through the second dielectric layer, the second etch stop layer, and the first etch stop layer to connect to the conductive feature, Wherein, the first etching stop layer comprises aluminum nitride or silicon carbonitride, Wherein, the second etching stop layer includes aluminum oxide or silicon oxycarbide.

8. The contact structure according to claim 7, further comprising: The middle etch stop layer is sandwiched between the first etch stop layer and the second etch stop layer.

9. The contact structure according to claim 7, wherein: The first etch stop layer includes a bottom surface closer to the conductive component and a top surface farther from the conductive component, Wherein, the nitrogen content at the bottom surface is greater than the nitrogen content at the top surface.

10. A method of forming a contact structure, comprising: receiving a workpiece including a conductive component embedded in a first dielectric layer; depositing a first etch stop layer over the workpiece such that the first etch stop layer is in direct contact with top surfaces of the conductive feature and the first dielectric layer; depositing a second etch stop layer over the first etch stop layer; depositing a second dielectric layer over the second etch stop layer; forming an opening through the second dielectric layer, the second etch stop layer, and the first etch stop layer to expose the conductive feature; as well as forming a contact via in the opening, Wherein, the first etching stop layer comprises metal oxide.

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