Stress mitigation architecture for glass core substrates

Abstract

The present disclosure relates to stress mitigation architectures for glass core substrates. Embodiments disclosed herein include a package substrate having a glass core. In an embodiment, an apparatus includes a core having a first width, and the core includes a glass layer. In an embodiment, a via is disposed through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is disposed over the core, where the first layer includes a second width that is less than the first width. In an embodiment, a second layer is disposed under the core, where the second layer includes a third width that is less than the first width.

Description

Background Art

[0001] As semiconductor packaging architectures continue to evolve toward more complex and compact systems, new material solutions can be used to achieve such architectures. A promising candidate for packaging substrates is a glass core layer. In this substrate, a glass core is sandwiched between an upper buildup layer and a lower buildup layer. Conductive vias are provided through the glass core to provide electrical coupling between the upper buildup layer and the lower buildup layer. Glass cores are beneficial because they can provide high-density vias. Glass is also a high modulus material that provides the desired stiffness for the entire packaging substrate. Glass cores can also improve planarity issues at the panel level.

[0002] However, glass cores are not without their problems. For example, compressive stress vectors applied to the glass core by the upper buildup layers can lead to catastrophic defects, especially at the panel level. One major defect mechanism is sometimes referred to as the seware defect mechanism. When a seware defect occurs, the forces applied to the panel cause the glass core to split horizontally. That is, the panel is divided into a top side (including the top buildup layer and the upper half of the glass core) and a bottom side (including the bottom buildup layer and the lower half of the glass core). The top and bottom sides warp in directions relative to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A is a plan view of a panel having a plurality of package substrate units distributed throughout the panel according to an embodiment.

[0004] Figure 1B is a plan view of a panel having a plurality of package substrate units according to an embodiment, wherein a trench passes through a build-up layer around a quarter panel area.

[0005] Figure 1C is a plan view of a panel having a plurality of package substrate units according to an embodiment, wherein a groove and a firewall are provided around a quarter panel area.

[0006] Figure 2A is a cross-sectional view of a portion of a panel showing grooves through a buildup layer along a saw street according to an embodiment.

[0007] Figure 2B is a cross-sectional view of a portion of a package substrate after singulation according to an embodiment, showing that edges of the buildup layers are offset relative to edges of the glass core.

[0008] Figure 2C is a cross-sectional view of a portion of a panel according to an embodiment, showing a first groove along a saw street and a second groove inside the first groove.

[0009] Figure 2D is a cross-sectional view of a portion of a package substrate after singulation according to an embodiment, showing that the edge of the buildup layer is set back relative to the edges of the glass core and the second trench.

[0010] Figure 2E is a cross-sectional view of a portion of a panel showing grooves with sloped sidewalls along a saw street according to an embodiment.

[0011] Figure 2F is a cross-sectional view of a portion of a package substrate after singulation according to an embodiment, showing that the edges of the buildup layers are offset relative to the edges of the glass core.

[0012] Figure 3 is a cross-sectional view of a package substrate having a glass core and a buildup layer having an edge that is set back relative to an edge of the glass core according to an embodiment.

[0013] Figure 4A is a cross-sectional view of a portion of a package substrate having a glass core according to an embodiment, the glass core including a first region having defects at an edge of the glass core and a second region substantially free of defects.

[0014] Figure 4B is a cross-sectional view of a portion of a package substrate having a glass core and a buildup layer having a groove for reducing propagation of defects from an edge of the glass core according to an embodiment.

[0015] Figure 5A is a plan view of a package substrate having a trench penetrating a buildup layer disposed away from an edge of the package substrate according to an embodiment.

[0016] Figure 5B According to the embodiment Figure 5A A cross-sectional view of the package substrate along line 5-5'.

[0017] Figure 5C is a cross-sectional view of a package substrate having a trench with tapered sidewalls according to an embodiment.

[0018] Fig. 6A is a plan view of a package substrate having a trench according to an embodiment, the trench including a liner along an outer sidewall of the trench.

[0019] Figure 6B According to the embodiment Fig. 6A A cross-sectional view of the package substrate along line 6-6'.

[0020] Figure 6C is a cross-sectional view of an edge of a package substrate according to an embodiment, illustrating the compressive force applied to the edge of a glass core by a trench having a liner layer.

[0021] Fig. 7A is a cross-sectional view of a portion of a panel having an insert in a glass core through a saw street according to an embodiment.

[0022] Figure 7B is a cross-sectional view of a portion of a package substrate having an interposer at an edge of a glass core according to an embodiment.

[0023] Figure 7C is a cross-sectional view of a portion of a package substrate having a triangular-shaped interposer at an edge of a glass core according to an embodiment.

[0024] Fig.7D is a cross-sectional view of a portion of a package substrate according to an embodiment, wherein the package substrate has an insert into a glass core, the insert being disposed away from an edge of the glass core.

[0025] Figure 8 is a cross-sectional view of a package substrate having a buildup layer including an edge surface having a protrusion according to an embodiment.

[0026] Figures 9A-9G is a cross-sectional view illustrating a process for forming a package substrate having a glass core and a buildup layer having an edge protrusion according to an embodiment.

[0027] Figures 10A-10C is a cross-sectional view illustrating a process for forming a package substrate having a glass core and a recessed buildup layer, the buildup layer having an edge protrusion according to another embodiment.

[0028] Fig.11 is a cross-sectional view of a package substrate having a glass core including an embedded stress reduction layer according to an embodiment.

[0029] Fig.12 is a cross-sectional view of a portion of a package substrate having an interposer penetrating through the thickness of a glass core to provide a compressive force on the glass core in accordance with an embodiment.

[0030] Fig.13A is a plan view of a portion of a panel including a column of inserts adjacent to a saw street through a glass core according to an embodiment.

[0031] Fig. 13B is a plan view of a portion of a panel including a pair of insert columns adjacent to a saw street through a glass core according to an embodiment.

[0032] Fig. 13C is a plan view of a portion of a panel including a ring of inserts around a glass core unit according to an embodiment.

[0033] Figures 14A-14G is a cross-sectional view of a portion of a panel showing the process of forming a compression insert through the thickness of a glass core according to an embodiment.

[0034] Fig.15 is a schematic diagram of a computing device constructed in accordance with an embodiment. DETAILED DESCRIPTION

[0035] Electronic systems are described herein, and more specifically, packaging substrates having a glass core including a stress relief architecture according to various embodiments are described. In the following description, various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of their work to other technicians in the field. However, it is obvious to those skilled in the art that the present disclosure can be practiced using only some of the described aspects. For the purpose of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it is obvious to those skilled in the art that the present disclosure can be practiced without specific details. In other cases, well-known features are omitted or simplified so as not to make the illustrative embodiments difficult to understand.

[0036] Various operations will be described as multiple discrete operations performed in sequence in a manner that is most helpful for understanding the present disclosure, however, the order of description should not be interpreted as implying that these operations must be sequence-dependent. In particular, these operations do not need to be performed in the order presented.

[0037] As described above, panel-level manufacturing of package substrates with glass cores can result in significant defects that can reduce yield to zero. In particular, stress introduced into the glass core from the buildup layers above has been shown to be an important contributor to seware defects at the panel level. The stress is generated at least in part due to the mismatch in the coefficient of thermal expansion (CTE) between the material of the glass core and the material of the buildup layers. Therefore, embodiments disclosed herein provide architectures, processes, and other solutions that allow stress mitigation not only at the panel level, but also at the individual unit level.

[0038] Some embodiments include using grooves that pass through the thickness of the buildup layer. For example, the grooves can be set at the saw street locations between individual units. The singulation process can then pass only through the glass core. In this case, the resulting package substrate unit can have a buildup layer having an edge surface that is set back relative to the edge surface of the glass core. The grooves can also be used as a "firewall" type structure. The firewall groove is set further away from the edge of the glass core than the first groove along the saw street. The firewall groove reduces the propagation of cracks and other defects from the edge of the glass core further toward the center of the glass core.

[0039] Other embodiments may include stress relief grooves disposed away from the edge of the buildup layer. The stress relief grooves may also include a liner along the outer sidewall. Due to the CTE mismatch between the liner and the buildup material, controlled warping may occur. This controlled warping may induce compressive forces on the glass core to mitigate defect propagation.

[0040] In yet another embodiment, an insert may be provided along the edge of the glass core. The insert may have a CTE similar to that of the glass, while also having a higher modulus than the glass. This allows the insert to preferentially absorb stress, which may prevent or minimize damage to the glass core.

[0041] In yet another embodiment, a compression pin may be provided that passes through the thickness of the glass core. The pin may have a top pad and a bottom pad. As the pin solidifies, the top pad is pulled toward the bottom pad to induce a compressive force on the glass core. Such pins may be arranged in a ring (or multiple rings) around the perimeter of the glass core in each package substrate.

[0042] In embodiments disclosed herein, grooves through the buildup layers can be provided by one or more different processing operations. In one process, laser ablation is used to remove the buildup layer material and expose the glass core below. In another process, a dummy structure (e.g., dummy copper) can be manufactured along with the manufacture of the buildup layer. The dummy structure can then be removed by an etching process to expose the glass core below. In such embodiments, the outer edge of the buildup layer can have a unique profile, including a profile with a protrusion.

[0043] Reference now Figure 1A , a plan view of a panel 110 according to an embodiment is shown. The panel 110 may include a plurality of package substrate units 100 distributed throughout the panel 110. The individual units 100 may be provided in a grid array. For example, the unit 100 may be provided in an array forming four quarter panels, and each quarter panel has twelve individual units 100. However, the number and layout of the units 100 within the panel 110 may vary depending on the size of the panel 110 and the size of the unit 100 and other factors. The use of panel-level processing allows for increased throughput. That is, a plurality of units 100 may be manufactured and assembled substantially in parallel with each other. After the panel 110 is completed, the individual units 100 may be singulated using any suitable process. For example, a saw or other mechanical tool may cut along the saw road between the individual units 100, as will be described in more detail below.

[0044] In the illustrated embodiment, the cells 100 are shown with dashed lines. Dashed lines are used because at the panel 110 level, the individual cells 100 may not have any distinguishable boundaries with each other. For example, the top layer (e.g., the buildup layer 140) may be a substantially uniform top surface. In some cases, blank areas (e.g., areas without electrical wiring) of the panel 110 may be provided along the saw streets between the cells 100.

[0045] Panel 110 may include a glass core (not shown). Buildup layers 140 may be provided above and / or below the glass core. As described above, interaction between buildup layers 140 and the glass core may result in significant warping or other damage (e.g., seware defects). Therefore, a plurality of layers may be used, such as Figure 1B and Figure 1C The disadvantages can be alleviated by embodiments such as those shown in .

[0046] Reference now Figure 1B , shows a plan view of a panel 110 according to another embodiment. In an embodiment, the panel 110 may include a groove 130 passing through the buildup layer 140. The groove 130 may expose the surface of the glass core 120 below. In an embodiment, the groove 130 may be formed using a laser ablation process. For example, a laser source may be used to selectively remove the dielectric material of the buildup layer 140. However, other material removal processes may also be used.

[0047] The groove 130 can be disposed around the perimeter of the unit 100. For example, the groove 130 can be a ring that is offset relative to the edge of the panel 110. However, in other embodiments, the groove 130 can also extend all the way to the edge of the panel 110. The groove 130 can have a width of about 10 μm or more or up to about 250 μm. However, in some embodiments, the groove 130 can have a smaller or larger width.

[0048] In an embodiment, the groove 130 may also include a portion along the saw street between the quarter panel areas of the panel 110. For example, Figure 1B The groove 130 in the panel 110 has a cross shape defining four quadrants of the panel 110. Although not shown, some embodiments may further include a groove 130 surrounding each of the individual cells 100.

[0049] Reference now Figure 1C , shows a plan view of a panel 110 according to yet another embodiment. Figure 1CIn the illustrated embodiment, a plurality of grooves 130, 131, and 132 are provided. The plurality of grooves 130, 131, and 132 can further reduce the stress induced on the glass core 120. In some embodiments, the groove 130 can be a ring disposed near the periphery of the panel 110. The second groove 131 can be a ring around a quarter panel. The groove 131 can also have a cross along the saw street between the quarter panel areas. In an embodiment, the third groove 132 can be a ring within the second groove 131 and around the unit 100 in the quarter panel.

[0050] In an embodiment, the second groove 131 can be along the saw road of the panel 110. However, the third groove 132 can be within the saw road that defines each quarter panel. That is, the entire third groove 132 can remain after the singulation process. In some embodiments, the third groove 132 can be referred to as a firewall groove 132. The third groove 132 can help reduce the further diffusion or propagation of defects from the outer edge of the glass core 120 to the center of the glass core 120. In this way, electrical wiring features (e.g., vias, etc.) can be protected and the possibility of seware damage is reduced. In some embodiments, the firewall type groove 132 can also be set at the unit 100 level.

[0051] Reference now Figures 2A-2F , shows a cross-sectional view of a panel 210 and respective package substrates 200 according to various embodiments. In the illustrated embodiment, a glass core 220 is provided below a buildup layer 240. It should be understood that a similar buildup layer 240 structure may also be provided on the bottom surface of the glass core 220.

[0052] In an embodiment, the glass core 220 may be substantially all glass. The glass core 220 may be a solid substance including a glass material having an amorphous crystal structure, wherein the solid glass core may also include various structures filled with one or more other materials (e.g., metals, metal alloys, dielectric materials, etc.), such as vias, cavities, channels, or other features. Therefore, the glass core 220 may be distinguished from, for example, a "prepreg" or "RF4" core of a printed circuit board (PCB) substrate, which typically includes glass fibers embedded in a resin organic material (e.g., epoxy resin). More specifically, the glass core 220 may be any suitable glass formulation having the necessary mechanical robustness and compatibility with semiconductor package manufacturing and assembly processes. For example, the glass core 220 may include aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silicon dioxide, fused silica, and the like. In some embodiments, the glass core 220 may include one or more additives, such as, but not limited to, Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. More generally, the glass core 220 may include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In an embodiment, the glass core 220 may include at least 23% silicon (by weight) and at least 26% oxygen (by weight). In some embodiments, the glass core 220 may also include at least 5% aluminum (by weight).

[0053] In an embodiment, the thickness of the glass core 220 (between the top and bottom surfaces) can be about 50 μm to about 2,000 μm. However, a thinner or thicker glass core 220 can be used in other embodiments. The glass core 220 can have a substantially rectangular shape (when viewed from above in a plan view). However, other shapes can also be used for the glass core 220.

[0054] In an embodiment, buildup layer 240 may include an organic buildup film or any other dielectric material suitable for electrical packaging. Buildup layer 240 may include one or more laminate layers to form a structure with a desired thickness. In an embodiment, buildup layer 240 may include conductive features (e.g., pads, traces, vias, etc.) fabricated together with the formation of buildup layer 240.

[0055] Embodiments disclosed herein may refer to two or more separate surfaces as being substantially coplanar with each other. As used herein, "substantially coplanar" may refer to two or more surfaces being coplanar within any manufacturing tolerance of the tool used to produce the surface. For example, in a singulation process, a saw may be used to cut through multiple layers of material. Since a single saw with a single sawing path is used to cut through multiple layers, the exposed edges of these layers will be substantially coplanar. Substantially coplanar may also refer to two surfaces being parallel to each other but on a plane spaced about 3 μm or less from each other. Substantially coplanar may also refer to two surfaces being in contact with each other and being coplanar with each other within about 3°. As used herein, "about" may refer to a range of values ​​within ten percent of the value. For example, about 100 μm may refer to a range between 90 μm and 110 μm.

[0056] Reference now Figure 2A , shows a cross-sectional view of a portion of a panel 210 according to an embodiment. In an embodiment, a buildup layer 240 above a glass core 220 includes a groove 230. The groove 230 may coincide with a saw street 205 passing through the panel 210. The saw street 205 may be a saw street 205 used to singulate a quarter panel area of ​​the board 210. In other embodiments, the saw street 205 may be disposed between adjacent cells. The groove 230 may be a ring around the entire panel 210, a quarter panel area, or a single cell.

[0057] In an embodiment, trench 230 may have substantially vertical sidewalls. However, embodiments may have trench 230 with any sidewall profile. Trench 230 may have a width between about 10 μm and about 250 μm. However, narrower or wider trenches 230 may also be used in some embodiments.

[0058] Reference now Figure 2B , shows a cross-sectional view of a package substrate unit 200 according to an embodiment. In an embodiment, Figure 2B The unit 200 shown in FIG. 1 is obtained after singulation along saw street 205. Figure 2A In the illustrated embodiment, only a single edge of the unit 200 is shown for simplicity. It should be understood that all edges of the unit 200 may be similar in shape and layout. Figure 2B The left edge shown in .

[0059] As shown, edge 241 of buildup layer 240 is set back relative to edge 226 of glass core 220. For example, the distance between edge 241 and edge 226 can be between about 10 μm and about 250 μm. However, larger or smaller setback distances can also be used. Due to the setback of edge 241, a portion of the top surface of glass core 220 is exposed. Pulling back a portion of buildup layer 240 from the edge of glass core 220 also reduces the amount of stress introduced into glass core 220. Therefore, defects at edge 226 of glass core 220 are less likely to propagate to the center of glass core 220.

[0060] Reference now Figure 2C , shows a cross-sectional view of a portion of a panel 210 according to an embodiment. In an embodiment, the panel 210 may include a buildup layer 240 disposed over the glass core 220. In an embodiment, the panel 210 may include a first groove 230 disposed along a saw street 205. The saw street 205 may be disposed around the perimeter of the panel 210, between quarter panel areas of the panel 210, or between individual cells 200 of the panel 210.

[0061] In an embodiment, the second groove 231 may be disposed inside the first groove 230. The first groove 230 and the second groove 231 may be rings concentric with each other. In some embodiments, the spacing between the first groove 230 and the second groove 231 may be between about 5 μm and about 200 μm. The grooves 230 and 231 may have similar widths. However, in other embodiments, the widths of the grooves 230 and 231 may be different. The second groove 231 may be referred to as a firewall groove because it may be used to mitigate the propagation of defects to the center of the glass core 220.

[0062] Reference now Figure 2D , shows a cross-sectional view of a package substrate unit 200 according to an embodiment. In an embodiment, the unit 200 is Figure 2C 2. As shown in the figure, the first groove 230 sets back the edge 241 of the buildup layer 240 relative to the edge 226 of the glass core 220. The second groove 231 allows the island of the buildup layer 240 to be set close to the edge of the unit 200. The island of the buildup layer 240 can be a ring set from the edge 226 of the glass core 220.

[0063] Reference now Figure 2E, shows a cross-sectional view of a panel 210 according to yet another embodiment. The panel 210 may include a buildup layer 240 disposed above a glass core 220. In an embodiment, a groove 230 through the buildup layer 240 exposes a top surface of the glass core 220. The groove 230 may be located along a saw street 205 of the panel 210. The saw street 205 may be around the perimeter of the panel 210, along a quarter panel area of ​​the panel 210, or around a cell 200 of the panel 210.

[0064] In an embodiment, the groove 230 may have a sidewall 241. The sidewall 241 may have an inclined or otherwise tapered profile. For example, the top surface of the buildup layer 240 may be narrower than the bottom surface of the buildup layer 240. In other words, the top of the groove 230 may be wider than the bottom of the groove 230. The slope of the sidewall 241 may depend on various processing conditions, such as but not limited to laser power parameters, scanning speed, etc.

[0065] Reference now Figure 2F , a cross-sectional view of a package substrate unit 200 according to an embodiment is shown. Figure 2F The unit 200 may be along the Figure 2E As shown, the edge 241 of the buildup layer 240 is offset relative to the edge 226 of the glass core 220. Therefore, a portion of the top surface of the glass core 220 is exposed outside the buildup layer 240.

[0066] Reference now Figure 3 , a cross-sectional view of a package substrate unit 300 according to an embodiment is shown. In an embodiment, the unit 300 may include a glass core 320. The glass core 320 may be similar to any glass core described in more detail herein. In an embodiment, the glass core 320 may include a sidewall (or edge) 326 coupling the top surface 323 to the bottom surface 324. The edge 326 may be substantially vertical. That is, in some cases, the edge 326 may be substantially orthogonal to the top surface 323. However, depending on the method of singulation, the edge 326 may have a non-vertical profile.

[0067] Glass core 320 may also include conductive vias 321 that pass through the thickness of glass core 320. In some embodiments, vias 321 may be lined with a liner (not shown). Depending on the manufacturing method, vias 321 may have a cross-section of any shape. For example, Figure 3 The via 321 in the embodiment has an hourglass-shaped cross-section, which is a typical feature of the double-sided laser-assisted etching process. The via 321 may include copper, aluminum, silver, an alloy of metal materials, etc. In some embodiments, the via 321 may include a seed layer, a barrier layer, etc.

[0068] In an embodiment, the cell 300 may also include a buildup layer 340 disposed above and / or below the glass core 320. The buildup layer 340 may include an organic dielectric material, such as a laminated buildup film layer. Conductive features 344 (e.g., pads, traces, vias, etc.) may also be embedded within the buildup layer 340. In an embodiment, the buildup layer 340 may have a sidewall (or edge) 341. The edge 341 may be vertical (e.g., substantially orthogonal to the top surface 323 of the glass core 320). In other embodiments, the edge 341 may be inclined, similar to the embodiments described in more detail above.

[0069] The buildup layer 340 of the unit 300 may have a first width, and the glass core 320 may have a second width greater than the first width. Thus, the sidewall 341 of the buildup layer 340 is set back relative to the edge 326 of the glass core 320. This exposes portions of the top surface 323 and the bottom surface 324. In an embodiment, the exposure of the top surface 323 and the bottom surface 324 helps to reduce the stress introduced into the glass core 320.

[0070] Reference now Figure 4A , a cross-sectional view of a portion of a package substrate unit 400 according to an embodiment is shown. The unit 400 may include a glass core 420 with a buildup layer 440 above and / or below the glass core 420. As shown, the glass core 420 may extend outward beyond the edge of the buildup layer 440. The exposed end region of the glass core 420 allows for reduced defect propagation. For example, the glass core 420 may have a first region 429 around the outer edge of the unit 400 and a second region 428 at the center of the unit 400.

[0071] The first region 429 may have a relatively high defect density. The defects may include cracks, microcracks, etc. The defects may be caused by the singulation process used to cut through the glass core 420. However, since the buildup layer 440 is retracted, the stress on the first region 429 is reduced. This limits how far the defects propagate into the glass core 420. In some cases, the second region 428 may have a low defect density compared to the first region 429. For example, the defect density of the first region 429 may be about twice (or more) the defect density of the second region 428. In some cases, the second region 428 may have up to 10% of the defects of the first region 429, up to 5% of the defects of the first region 429, or up to 1% of the defects of the first region 429. In an embodiment, the width of the first region 429 may be up to about 10 μm, up to about 50 μm, up to about 100 μm, or up to about 250 μm.

[0072] Reference now Figure 4B , shows a cross-sectional view of a package substrate unit 400 according to an additional embodiment. In the embodiment, in addition to Figure 4B Outside the groove 431 in the unit 400, Figure 4B The unit 400 in may be similar to Figure 4A In an embodiment, the groove 431 can further reduce the propagation of defects toward the center of the glass core 420. In some embodiments, the first region 429 can extend all the way to the groove 431. For example, the inner edge of the first region 429 can be outside the inner sidewall of the groove 431. However, in some cases, the first region 429 can extend beyond the groove 431.

[0073] Reference now Figure 5A , shows a plan view of a package substrate unit 500 according to an embodiment. In an embodiment, the unit 500 may include a stacked body including a glass core 520 with a buildup layer 540 above and / or below the glass core 520. In an embodiment, the buildup layer 540 extends to the edge of the glass core 520. Figure 5A As shown, groove 531 is disposed near the edge of unit 500. Groove 531 can be a ring, such as a rectangular ring. Groove 531 can be used as a stress relief feature to prevent or limit stress transfer from buildup layer 540 to glass core 520. Groove 531 passes through the entire thickness of buildup layer 540 to expose the surface of glass core 520.

[0074] Reference now Figure 5B , showing the Figure 5A 5 ' is a cross-sectional view of the package substrate unit 500 in FIG. 5 . In an embodiment, the glass core 520 may include a conductive via 521 passing through the thickness of the glass core 520. The via 521 may have any shape (e.g., tapered sidewalls, vertical sidewalls, etc.). In some cases, a liner (not shown) may be provided between the via 521 and the glass core 520.

[0075] Build-up layers 540 may be disposed above and below glass core 520. Build-up layers 540 may extend to the edge of glass core 520. That is, instead of having a setback, edge 541 of build-up layers 540 may be substantially coplanar with edge 526 of glass core 520. For example, a singulation process for forming unit 500 may include passing a saw blade through build-up layers 540 and glass core 520. Build-up layers 540 may include conductive features 544 (e.g., pads, traces, vias, etc.). Conductive features 544 may be fabricated using conventional package assembly processes during assembly of build-up layers 540.

[0076] In an embodiment, the groove 531 passes through the buildup layer 540 to expose portions of the top and bottom surfaces of the glass core 520. In an embodiment, the groove 531 may be disposed away from the edge 526 of the glass core 520. For example, the outer wall of the groove 531 may be up to 250 μm away from the edge 526 of the glass core 520. In some cases, the outer wall of the groove 531 may be 10 μm to 100 μm away from the edge 526 of the glass core 520. In some embodiments, the wall of the groove 531 may be substantially vertical. That is, the wall of the groove 531 may be substantially orthogonal to the top surface of the glass core 520. In an embodiment, the area of ​​the buildup layer 540 outside the groove 531 may be a blank area. That is, there may be no conductive feature 544 outside the groove 531.

[0077] Reference now Figure 5C , shows a cross-sectional view of a package substrate unit 500 according to an additional embodiment. In the embodiment, in addition to the structure of the groove 531, Figure 5C Unit 500 in is substantially similar to Figure 5B 5. Instead of having vertical sidewalls, trench 531 may have sloped or tapered sidewalls 543. Sloped sidewalls 543 may be a result of a laser ablation process used to form trench 531. In an embodiment, the top of trench 531 may be wider than the bottom of trench 531.

[0078] Reference now Fig. 6A , shows a plan view of a package substrate unit 600 according to an embodiment. In an embodiment, the unit 600 may include a stacked body including a glass core 620 with a buildup layer 640 above and / or below the glass core 620. In an embodiment, the buildup layer 640 extends to the edge of the glass core 620. Fig. 6A As shown, groove 631 is disposed near the edge of unit 600. Groove 631 can be a ring, such as a rectangular ring. Groove 631 can be used as a stress relief feature to prevent or limit stress transfer from buildup layer 640 to glass core 620. Groove 631 passes through the entire thickness of buildup layer 640 to expose the surface of glass core 620.

[0079] In an embodiment, a liner 637 is provided along the outer surface of the groove 631. The liner 637 may include a material different from that of the buildup layer 640. More specifically, the liner 637 may have a CTE different from that of the buildup layer 640. The difference in CTE may be used to facilitate providing controlled warping of the cell 600. Such controlled warping may be used to apply a compressive force to the glass core 620, as will be described in more detail below.

[0080] Reference now Figure 6B , showing the Fig. 6A6-6' of the package substrate unit 600 in FIG. In an embodiment, the glass core 620 may include a conductive via 621 passing through the thickness of the glass core 620. The via 621 may have any shape (e.g., tapered sidewalls, vertical sidewalls, etc.). In some cases, a liner (not shown) may be provided between the via 621 and the glass core 620.

[0081] Build-up layers 640 may be disposed above and below glass core 620. Build-up layers 640 may extend to the edge of glass core 620. That is, instead of having a setback, edge 641 of build-up layers 640 may be substantially coplanar with edge 626 of glass core 620. For example, a singulation process for forming unit 600 may include passing a saw blade through build-up layers 640 and glass core 620. Build-up layers 640 may include conductive features 644 (e.g., pads, traces, vias, etc.). Conductive features 644 may be fabricated using conventional package assembly processes during assembly of build-up layers 640.

[0082] In an embodiment, the groove 631 passes through the buildup layer 640 to expose portions of the top and bottom surfaces of the glass core 620. In an embodiment, the groove 631 can be set away from the edge 626 of the glass core 620. For example, the outer wall of the groove 631 can be up to 250 μm away from the edge 626 of the glass core 620. In some cases, the outer wall of the groove 631 can be between 10 μm and 100 μm away from the edge 626 of the glass core 620. In some embodiments, the wall of the groove 631 can be substantially vertical. That is, the wall of the groove 631 can be substantially orthogonal to the top surface of the glass core 620.

[0083] In an embodiment, a liner 637 is provided along the outer sidewall of the trench 631. The liner 637 may include a material different from the buildup layer 640. For example, the liner 637 may include a metal material such as copper. In some embodiments, the liner 637 may cover the entire sidewall of the trench 631. The liner 637 may have a thickness of up to about 20% of the thickness of the trench 631. For example, in some embodiments, the liner 637 may have a thickness of up to about 25 μm.

[0084] Reference now Figure 6C, an enlarged cross-sectional view of a portion of a unit 600 according to an embodiment is shown. As shown, the region of the stacking layer 640 outside the groove 631 can have a controlled warp. For example, the edge 641 of the stacking layer 640 can be curved or otherwise nonlinear. Similarly, the surface 638 of the liner 637 can be curved away from the rest of the stacking layer 640 on the opposite side of the groove 631. The curvature can be the result of a CTE mismatch between the liner 637 and the stacking layer 640. In an embodiment, the warping can result in a compressive force (arrowed) being applied to the glass core 620. The compressive force can help reduce or eliminate the propagation of defects to the center of the glass core 620.

[0085] Reference now Fig. 7A , shows a cross-sectional view of a portion of a panel 710 according to an embodiment. In an embodiment, the panel 710 may include a glass core 720 and a buildup layer 740 above and / or below the glass core 720. The conductive features 744 may be embedded in the buildup layer 740.

[0086] In an embodiment, the insert 750 may be at least partially embedded in the glass core 720. For example, a pair of inserts 750 are disposed in the glass core 720, with one insert at the top surface of the glass core 720 and a second insert at the bottom of the glass core 720. In an embodiment, the insert 750 may extend through the saw streets 705 defining the individual cells.

[0087] The insert 750 may be a different material than the glass core 720. More specifically, the insert 750 may be a material having a similar CTE to the glass core 720 while also having a higher modulus than the glass core 720. For example, the CTE of the insert 750 may be within about 20% of the CTE of the glass core 720. The increased modulus of the insert 750 allows excess stress introduced into the glass core 720 to be absorbed by the insert 750. This prevents or minimizes the propagation of defects into the glass core 720.

[0088] Reference now Figure 7B , a cross-sectional view of a portion of a package substrate unit 700 according to an embodiment is shown. Figure 7B The unit 700 may be along the Fig. 7A Result of the singulation process of panel 710 in saw street 705.

[0089] As shown, the insert 750 can have an outer edge 751 that is substantially coplanar with the edge 726 of the glass core 720. The top surface 754 of the insert 750 can be substantially coplanar with the top surface 723 of the glass core 720. The bottom surface 753 of the insert 750 can be substantially parallel to the top surface 723 of the glass core 720. In an embodiment, the inner edge 752 of the insert 750 can be inclined. The inclined profile of the inner edge 752 can further reduce the stress transmitted to the glass core 720. The insert 750 can extend into the glass core 720 at any suitable distance. For example, the length of the insert 750 can be up to about 250 μm. In other embodiments, the length of the insert 750 can be between about 10 μm and about 100 μm.

[0090] Reference now Figure 7C , shows a cross-sectional view of a package substrate unit 700 according to an additional embodiment. In an embodiment, in addition to the shape of the insert 750, Figure 7C Unit 700 in is similar to Figure 7B Unit 700 in. Figure 7C In the embodiment of the present invention, the insert 750 may have a triangular shape. The triangular insert 750 may have an edge 751 that is substantially coplanar with the edge 726 of the glass core 720. Figure 7B and Figure 7C Certain shapes of insert 750 are shown in FIG. 7 , but it should be understood that insert 750 may take any suitable shape.

[0091] Reference now Fig.7D , a cross-sectional view of a package substrate unit 700 according to an additional embodiment is shown. Fig.7D , cell 700 includes a buffer layer 708 disposed between a buildup layer 740 and a glass core 720. Buffer layer 708 may be a dielectric material, such as an organic dielectric. Buffer layer 708 may be a different material than buildup layer 740. However, in other embodiments, buffer layer 708 and buildup layer 740 may include similar or identical materials.

[0092] In an embodiment, a groove 753 can be provided in the top surface and / or the bottom surface of the glass core 720. The groove 753 can be provided in the glass core 720 away from the edge 726. In an embodiment, the groove 753 can be filled by an insert 750 that is part of the buffer layer 708. The groove 753 can have any suitable shape. In the illustrated embodiment, the groove 753 is a semi-circular groove entering the surface of the glass core 720. However, other shapes (e.g., rectangular, trapezoidal, triangular, etc.) can also be used in some embodiments. Fig.7DIn the embodiment shown, the corners 755 at the edges of the grooves 753 are angled. However, stress can be further reduced by rounding the corners 755 so that there are no sharp points that concentrate stress.

[0093] Reference now Figure 8 , shows a cross-sectional view of a package substrate unit 800 according to an embodiment. In an embodiment, the unit 800 may include a glass core 820 with a buildup layer 840 above and / or below the glass core 820. Vias 821 may be provided through the thickness of the glass core 820, and conductive features 844 may be embedded in the buildup layer 840.

[0094] In an embodiment, edge 841 of buildup layer 840 may be set back relative to edge 826 of glass core 820. However, instead of having a planar edge 841, edge 841 includes multiple sub-surfaces. Figure 8 In the embodiment of the present invention, three sub-surfaces 861, 862 and 863 are provided. The first sub-surface 861 and the third sub-surface 863 can be substantially vertical (e.g., substantially orthogonal to the top surface of the glass core 820). In some embodiments, the first sub-surface 861 and the third sub-surface 863 can be arranged on the same plane. In other embodiments, the first sub-surface 861 and the third sub-surface 863 can be on different planes. The second sub-surface 862 can be a portion of the protrusion extending beyond the first sub-surface 861 and the third sub-surface 863. In some embodiments, the second sub-surface 862 can have an inclined profile.

[0095] The unique profile of the edge 841 of the buildup layer 840 is the result of a process for clearing the saw streets at the panel level. Instead of using a laser ablation process, a dummy structure is fabricated and then etched away. The dummy structure may include vias and pads arranged in a vertical stack through the thickness of the buildup layer 840. Removal with an etching process (e.g., a wet etching process) may allow for reduced damage to the surface of the glass core 820 compared to a conventional laser ablation process.

[0096] Reference now Figures 9A-9G , a series of cross-sectional views are shown illustrating a process for forming a package substrate unit having a recessed buildup layer edge using a dummy structure process according to an embodiment.

[0097] Reference now Fig.9A , shows a cross-sectional view of a portion of a panel 910 according to an embodiment. In an embodiment, the panel 910 may include a glass core 920.

[0098] Reference now Fig. 9B, shows a cross-sectional view of a portion of panel 910 after forming a first pad 965 according to an embodiment. In an embodiment, the first pad 965 can be formed with other conductive features 944 above the glass core 920. Although referred to as a "pad," it should be understood that the pad 965 can be an elongated feature. For example, the first pad 965 can extend along the entire saw street of the panel 910. The first pad 965 can be formed using any plating and patterning process typical of electronic packaging solutions.

[0099] Reference now Fig. 9C , shows a cross-sectional view of a portion of panel 910 after forming a buildup layer 940 and additional metal layers 966 and 967 according to an embodiment. Metal layer 966 may be a via 966 connecting a second pad 967 to a first pad 965. In some embodiments, via 966 may have a tapered sidewall. The first pad 965 and the second pad 967 may have similar widths and thicknesses. Alternatively, the widths and / or thicknesses of the first pad 965 and the second pad 967 may be different. In some embodiments, the first pad 965 and the second pad 967 may be aligned with each other. For example, the centerline of the first pad 965 may substantially coincide with the centerline of the second pad 967. Similar to the first pad 965, the via 966 and the second pad 967 may be elongated structures extending along the length of the saw street of the panel 910.

[0100] Reference now Fig.9D , shows a cross-sectional view of a portion of panel 910 after an additional portion of buildup layer 940 is disposed over second pad 967 in accordance with an embodiment. The additional buildup material may be applied using a lamination process or the like.

[0101] Reference now Fig.9E , illustrates a cross-sectional view of a portion of a panel 910 after forming an opening 968 to expose a second pad 967 according to an embodiment. The opening 968 may be formed using an etching process or the like. Fig.9E The opening 968 in the embodiment has the same width as the second pad 967. However, in some embodiments, the opening 968 may be narrower or wider than the second pad 967.

[0102] Reference now Fig.9F , shows a cross-sectional view of a portion of panel 910 after removing a first pad 965, a via 966, and a second pad 967 according to an embodiment. Features 965, 966, and 967 may be removed using an etching process, such as a wet etching process. In an embodiment, the removal of features 965, 966, and 967 results in an opening 968 extending down to the surface of glass core 920. In an embodiment, a saw street 905 may be provided along opening 968.

[0103] exist Figures 9A-9F In the embodiment shown in FIG. 1 , it should be understood that a single buildup layer 940 is disposed over the top and bottom of the glass core 920. However, in some embodiments, the process may be repeated any number of times to form multiple buildup layers 940. In this case, features 965, 966, and 967 may be repeated for each buildup layer 940, and after all buildup layers are formed, all metals may be etched simultaneously.

[0104] Reference now Figure 9G , a cross-sectional view of a portion of a package substrate unit 900 after singulation according to an embodiment is shown. As shown, the edge of the buildup layer 940 is set back relative to the edge 926 of the glass core 920. In addition, the edge of the buildup layer 940 may include a plurality of sub-surfaces. For example, a first sub-surface 961, a second sub-surface 962, and a third sub-surface 963 may be provided. The second sub-surface 962 may be a portion of a protrusion that extends beyond the first sub-surface 961 and the third sub-surface 963. That is, the protrusion may be between the top surface and the bottom surface of the buildup layer 940. In an embodiment, the second sub-surface 962 may include an inclined profile.

[0105] Reference now Figures 10A-10C , shows a series of cross-sectional views illustrating a process for forming a package substrate unit according to further embodiments.

[0106] Reference now Fig. 10A , shows a cross-sectional view of a portion of a panel 1010 according to an embodiment. The panel 1010 may include a glass core 1020 with a buildup layer 1040 above and / or below the glass core 1020. In an embodiment, a conductive feature 1044 may be disposed in the buildup layer 1040. Additionally, a dummy feature may be disposed through the thickness of the buildup layer 1040. For example, the dummy feature may include copper or other metal structures, such as a first pad 1065, a via 1066, and a second pad 1067.

[0107] Reference now Fig. 10B , shows a cross-sectional view of a portion of panel 1010 after applying a resist layer 1069 over buildup layer 1040 according to an embodiment. In an embodiment, resist layer 1069 can include an opening 1068 that exposes a dummy feature. In particular, opening 1068 can be aligned with second pad 1067.

[0108] Reference now Fig. 10C, a cross-sectional view of a portion of panel 1010 after removing dummy features 1065, 1066, and 1067 according to an embodiment is shown. Dummy features 1065, 1066, and 1067 may be removed using an etching process, such as a wet etching process. Etching results in an opening 1068 extending downward to glass core 1020. Opening 1068 results in the formation of a multi-surface edge of buildup layer 1040. For example, a first sub-surface 1061 and a second sub-surface 1062 are provided. Second sub-surface 1062 may have an inclined profile. In addition, second sub-surface 1062 may be a portion of a protrusion at the top of buildup layer 1040.

[0109] exist Figures 10A-10C In the embodiment of the present invention, it should be understood that a single build-up layer 1040 is provided on the top and bottom of the glass core 1020. However, in some embodiments, the process can be repeated any number of times to form multiple build-up layers 1040. In this case, the dummy features 1065, 1066, and 1067 can be repeated for each build-up layer 1040, and after all build-up layers are formed, all metals can be etched simultaneously.

[0110] Reference now Fig.11 , a cross-sectional view of a package substrate unit 1100 according to an embodiment is shown. In an embodiment, the unit 1100 may include a composite core. For example, the first glass layer 1120a and the second glass layer 1120b may be separated from each other by an interface layer 1114. The interface layer 1114 may be a dielectric material, such as an organic dielectric, etc. The interface layer 1114 may absorb stress applied to the glass layers 1120a and 1120b, which is caused by the CTE mismatch between the stacking layer 1140 and the glass layers 1120a and 1120b.

[0111] Reference now Fig.12 , a cross-sectional view of a portion of a package substrate unit 1200 according to an embodiment is shown. In an embodiment, the unit 1200 includes a glass core 1220. In an embodiment, a pin 1280 is set through the thickness of the glass core 1220. The pin 1280 may include a via 1281, which connects a pad 1282 on the opposite surface of the glass core 1220. In an embodiment, the pin 1280 is cured, and the curing process causes the material of the pin 1280 to shrink. Therefore, as shown by the arrow in the via 1281, the pad 1282 is pulled together. This causes a compressive force on the glass core 1220, and the compressive force can limit or prevent the propagation of defects within the glass core 1220. In an embodiment, the material of the pin 1280 can be a high CTE organic material. In a specific embodiment, the pin 1280 can be a stacked film material with (or without) inorganic filler particles.

[0112] In other embodiments, the compressive force may be due to one or both of contraction of the material of the pins 1280 during curing (or during deposition and / or processing of any other layers), and residual stress of the material. For example, the residual stress may be caused by thermal expansion / contraction of the material of the pins 1280. If the CTE of the pins 1280 is higher than the CTE of the glass core, and the package substrate unit 1200 is processed at an elevated temperature (e.g., room temperature or an operating temperature ranging, for example, between about -55°C to about 125°C), the residual stress in the glass core 1220 will be compressive.

[0113] Reference now Figures 13A-13C , shows a series of plan views of a portion of a panel 1310 having a compression pin array according to various embodiments.

[0114] Reference now Fig.13A , shows a plan view of a portion of a panel 1310 according to an embodiment. In an embodiment, the panel 1310 includes a saw street 1305. The saw street 1305 can separate the individual units within the panel 1310. In an embodiment, a column of pins 1380 can be set along each side of the saw street 1305. The pins 1380 can be similar to those described above with respect to Fig.12 1305 . The pins 1380 are described in more detail. In the illustrated embodiment, the pins 1380 have a circular shape. However, in some embodiments, a square shape, a rectangular shape, or any other shape may also be used for the pins 1380. The pins 1380 may be up to about 250 μm from the edge of the saw street 1305 (or from the edge of a single unit of the glass core 1320). The pins 1380 may have a diameter between about 1 μm and about 90 μm.

[0115] Reference now Fig. 13B , shows a plan view of a portion of a panel 1310 according to another embodiment. In addition to having more than one column of pins 1380 on each side of the saw street 1305, the panel 1310 can be similar to Fig.13A For example, a first column of pins 1380A and a second column of pins 1380B may be disposed through the glass core 1320. The first column of pins 1380A may be offset relative to the second column of pins 1380B. In other embodiments, the pins 1380A may be aligned with the pins 1380B.

[0116] Reference now Fig. 13C , shows a plan view of a portion of a panel 1310 according to another embodiment. Fig. 13CThe glass core 1320 in FIG. 1 is shown as being surrounded by saw streets 1305 on all four sides to define a single unit within the panel 1310. As shown, the pins 1380 can be arranged in a ring around the perimeter of the unit. Although a single ring is shown, two or more rings of pins 1380 can be used in other embodiments.

[0117] Reference now Figures 14A-14G , a series of cross-sectional views are shown that illustrate a process for forming pins 1480 through glass core 1420 according to an embodiment. As shown, the openings for pins 1480 can be formed simultaneously with the openings for conductive vias. In some cases, the shapes and sizes of the pin openings and via openings can also be similar to each other.

[0118] Reference now Fig.14A , shows a cross-sectional view of a portion of a panel 1410 according to an embodiment. In an embodiment, the panel 1410 can include a glass core 1420, which is similar to any of the glass cores described in more detail herein.

[0119] Reference now Fig. 14B , shows a cross-sectional view of a portion of panel 1410 after forming openings 1411 and 1412 according to an embodiment. Opening 1411 can be a via opening that passes through the thickness of glass core 1420. Similarly, pin opening 1412 can pass through the thickness of glass core 1420. Openings 1411 and 1412 can be formed using any suitable process. For example, a laser-assisted etching process can be used to form openings 1411 and 1412. In such an embodiment, the sidewalls of openings 1411 and 1412 can be tapered. For example, openings 1411 and 1412 have an hourglass-shaped cross-section. In other embodiments, openings 1411 and 1412 can have substantially vertical sidewalls. As Fig. 14B As shown, the size and shape of openings 1411 and 1412 can be similar or identical to each other. However, in other embodiments, opening 1411 can be different from opening 1412.

[0120] Reference now Fig. 14C , shows a cross-sectional view of a portion of a panel 1410 after forming a via 1421 in a via opening 1411 according to an embodiment. The via 1421 may be formed using an electroplating process or the like. During the plating process, a resist layer 1415 may be used to cover the pin opening 1412. In some embodiments, the resist layer 1415 may have an opening wider than the via 1421 so as to define a pad 1422 above and below the via 1421.

[0121] Reference now Fig.14D, shows a cross-sectional view of a portion of a panel 1410 after patterning a second resist layer 1415 to expose a pin opening 1412 according to an embodiment. In an embodiment, the resist layer 1415 may have an opening 1416 that exposes the pin opening 1412. The opening 1416 may have a width wider than the pin opening 1412 to allow pads to be formed above and below the pins.

[0122] Reference now Fig.14E , shows a cross-sectional view of a portion of panel 1410 after pins 1480 are formed through glass core 1420 according to an embodiment. In an embodiment, pin 1480 may include via 1481 with pads 1482 above and below via 1481. The material of pin 1480 is different from the material of via 1421. For example, pin 1480 may include an organic dielectric material, such as a laminate film, epoxy resin, molding material, etc. Pin 1480 may include filler particles, such as inorganic filler particles. In an embodiment, pin 1480 may be in Fig.14E In an embodiment, the pins 1480 may be deposited using any suitable process, such as but not limited to slit coating, inkjet, etc.

[0123] Reference now Fig.14F , shows a cross-sectional view of a portion of panel 1410 after a polishing operation according to an embodiment. In an embodiment, resist layer 1415 is removed and a polishing process is performed. For example, a chemical mechanical polishing (CMP) process or other planarization process may be used to provide a substantially coplanar relationship between the top surface of pad 1422 and the top surface of pad 1482.

[0124] Reference now Figure 14G , shows a cross-sectional view of a portion of panel 1410 after a curing process according to an embodiment. The curing process causes pin 1480' to shrink. The shrinkage of the entire pin 1480' can cause pads 1482 above and below via 1481 to be pulled toward each other. This force exerts a compressive force on glass core 1420. This can achieve a reduction or elimination of defect propagation through glass core 1420.

[0125] In some embodiments described herein, reference is made to panel-level products or unit-level products. It should be understood that unit-level products can be manufactured from panel-level products (e.g., through a singulation process). However, unit-level products can also be formed independently rather than initially formed in a panel structure.

[0126] In addition, the embodiments disclosed herein are not limited to package substrate units. The package substrate unit can be part of a larger system. In such an embodiment, a board (e.g., a printed circuit board (PCB)) can be mounted to one side of the unit. For example, a second level interconnect (SLI) (such as a solder ball or a pin) can mechanically and electrically couple the package substrate unit to the board. In addition, the first level interconnect (FLI) on the opposite side of the package substrate unit can mechanically and electrically couple the unit to one or more tube cores. The tube core can include a computing tube core, such as a central processing unit (CPU), a graphics processing unit (GPU), an XPU, a communication tube core, a memory tube core, etc. In some cases, two or more tube cores can be coupled together by a bridge tube core embedded in a stacking layer or arranged above a stacking layer. In some cases, an interposer can also be set between any components in the board, the package substrate unit, and the tube core.

[0127] Fig.15 A computing device 1500 is shown according to one embodiment of the present disclosure. The computing device 1500 houses a board 1502. The board 1502 may include a number of components, including, but not limited to, a processor 1504 and at least one communication chip 1506. The processor 1504 is physically and electrically coupled to the board 1502. In some embodiments, the at least one communication chip 1506 is also physically and electrically coupled to the board 1502. In further embodiments, the communication chip 1506 is part of the processor 1504.

[0128] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0129] The communication chip 1506 implements wireless communication for transmitting data to and from the computing device 1500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data by using modulated electromagnetic radiation passing through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not contain any wires. The communication chip 1506 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G and higher generations. The computing device 1500 may include multiple communication chips 1506. For example, the first communication chip 1506 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1506 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0130] The processor 1504 of the computing device 1500 includes an integrated circuit die packaged within the processor 1504. In some implementations of the present disclosure, the integrated circuit die of the processor may be part of an electronic package that includes a packaging substrate having a glass core according to embodiments described herein, the glass core including one or more stress reduction features to relieve stress caused by a CTE mismatch between the glass core and an overlying buildup layer. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that may be stored in registers and / or memory.

[0131] The communication chip 1506 also includes an integrated circuit die packaged within the communication chip 1506. According to another embodiment of the present disclosure, the integrated circuit die of the communication chip can be part of an electronic package that includes a packaging substrate having a glass core according to embodiments described herein, the glass core including one or more stress reduction features to relieve stress caused by a CTE mismatch between the glass core and an overlying buildup layer.

[0132] In an embodiment, computing device 1500 may be part of any apparatus. For example, computing device may be part of a personal computer, a server, a mobile device, a tablet computer, an automobile, etc. That is, computing device 1500 is not limited to use in any particular type of system, and computing device 1500 may be included in any apparatus that may benefit from computing functionality.

[0133] The above description of the illustrated embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications within the scope of the present disclosure are possible as will be appreciated by those skilled in the relevant art.

[0134] These modifications may be made to the present disclosure in light of the above specific embodiments. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific embodiments disclosed in the specification and claims. On the contrary, the scope of the present disclosure will be determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

[0135] Example 1: A device comprising: a core having a first width, wherein the core comprises a glass layer; a via, the via extending through the thickness of the core, wherein the via is conductive; a first layer above the core, wherein the first layer comprises a second width less than the first width; and a second layer below the core, wherein the second layer comprises a third width less than the first width.

[0136] Example 2: The device according to Example 1, wherein the edge surface of the first layer is set back from the edge surface of the core by a maximum of about 250 μm.

[0137] Example 3: The device of Example 1 or Example 2, wherein an edge surface of the first layer is along a first plane and an edge surface of the core is along a second plane, wherein the first plane intersects the second plane.

[0138] Example 4: The device of Example 3, wherein a top surface of the first layer is narrower than a bottom surface of the first layer.

[0139] Example 5: The device of Examples 1-4, further comprising: a groove passing through a thickness of the first layer, wherein the islands of the first layer are disposed between an edge surface of the first layer and the groove.

[0140] Example 6: The device according to Example 5, wherein the width of the islands of the first layer is up to about 200 μm.

[0141] Example 7: The device of Examples 1-6, wherein the outer edge surface of the first layer includes a protrusion between the top surface and the bottom surface of the first layer.

[0142] Example 8: The device of Examples 1-7, wherein the core has an outer region and an inner region, wherein the outer region has a first defect density and the inner region has a second defect density lower than the first defect density.

[0143] Example 9: The device of Example 8, wherein the outer region has a width of up to about 200 μm from the edge of the core to the outer edge surface of the inner region.

[0144] Example 10: The device of Examples 1-9, wherein the first layer and the second layer comprise organic buildup layers.

[0145] Example 11: A device comprising: a core, wherein the core comprises glass; and a layer over the core, wherein the layer comprises an organic buildup film; and a groove through the thickness of the layer, wherein the groove is a ring disposed at a distance from an outer edge surface of the layer.

[0146] Example 12: The device according to Example 11 also includes: a lining along the outer side wall of the groove.

[0147] Example 13: The device of Example 12, wherein the liner comprises copper.

[0148] Example 14: The device of Examples 11-13, wherein the outer edge surface of the layer is substantially coplanar with the outer edge surface of the core.

[0149] Example 15: The device of Examples 11-14, wherein the groove has sidewalls having a sloped profile.

[0150] Example 16: A device comprising: a core, wherein the core comprises a glass layer; a layer above the core; and an insert at least partially embedded in the core, wherein the insert comprises a different material than the glass layer.

[0151] Example 17: The device of Example 16, wherein the insert has a coefficient of thermal expansion (CTE) that is within 20% of the CTE of the core, and wherein the modulus of the insert is greater than the modulus of the core.

[0152] Example 18: The device of Example 16 or Example 17, wherein the insert is an organic dielectric material that fills a groove into the surface of the core.

[0153] Example 19: The apparatus of Examples 16-18, wherein the insert passes through the thickness of the core, and wherein the first pad is above the insert and the second pad is below the insert.

[0154] Example 20: The device according to Example 19, comprising a cured deposited film.

[0155] Example 21: A device comprising: a core, wherein the core comprises a glass layer; a layer above the core, wherein the layer comprises an organic buildup film; and a groove through the thickness of the layer, wherein the groove defines an outer portion of the layer and an inner portion of the layer, and wherein the inner portion comprises one or more wiring features that are conductive and the outer portion has no wiring features.

[0156] Example 22: The device of Example 21, wherein the trench has sidewalls that are substantially orthogonal to the top surface of the layer.

[0157] Example 23: The device of Example 21 or Example 22, wherein the groove has a sidewall having an inclined profile.

[0158] Example 24: The device of Examples 21-23, wherein the groove is a ring surrounding the entire inner portion.

[0159] Example 25: The device of Examples 21-24, wherein the width of the groove is up to about 250 μm.

[0160] Example 26: The device of Examples 21-25 further includes: a lining along the outer sidewall of the groove.

[0161] Example 27: The device of Example 26, wherein the liner comprises copper.

[0162] Example 28: The device of Example 26 or Example 27, wherein the liner and the outer portion are curved away from the inner portion.

[0163] Example 29: The device of Examples 21-28, wherein the outer portion has a width of up to about 250 μm.

[0164] Example 30: The device of Examples 21-29, wherein the core has a thickness of up to 2,000 μm.

[0165] Example 31: A device comprising: a core, wherein the core comprises a glass layer; a layer above the core, wherein the layer is an organic build-up film; and an insert extending into a surface of the core, wherein a material composition of the insert is different from a material composition of the core.

[0166] Example 32: A device according to Example 31, wherein the insert has a first coefficient of thermal expansion (CTE) and a first modulus, and wherein the core has a second CTE and a second modulus, wherein the first CTE is within 20% of the second CTE, and wherein the first modulus is higher than the second modulus.

[0167] Example 33: The device of Example 31 or Example 32, wherein the insert has a top surface that is substantially coplanar with the top surface of the core and a second surface that is offset relative to the top surface of the core.

[0168] Example 34: The device of Example 33, wherein the first sidewall of the insert is substantially coplanar with the sidewall of the core, and wherein the second sidewall of the insert is inclined.

[0169] Example 35: The device of Examples 31-34, wherein the insert is triangular-shaped and the sidewalls of the insert are substantially coplanar with the sidewalls of the core.

[0170] Example 36: The device of Examples 31-35, wherein the insert fills a groove into the top surface of the core.

[0171] Example 37: The device of Example 36, wherein the groove has a circular bottom surface.

[0172] Example 38: The device of Example 37, wherein the corner between the groove and the top surface of the core is rounded.

[0173] Example 39: The device of Examples 31-38, wherein the insert comprises a built-up film material having inorganic filler particles.

[0174] Example 40: The apparatus of Examples 31-39, further comprising: a second insert on a surface of the core opposite the insert.

[0175] Example 41: A device comprising: a core, wherein the core comprises a glass layer; and a layer over the core, wherein the layer comprises an organic buildup film, and wherein the protrusions extend outwardly from a sidewall of the layer.

[0176] Example 42: A device according to Example 41, wherein the protrusion has a sloped edge profile.

[0177] Example 43: A device according to Example 42, wherein the length of the top surface of the protrusion is less than the length of the bottom surface of the protrusion.

[0178] Example 44: The device of Examples 41-43, wherein the protrusion is located between the top surface of the layer and the bottom surface of the layer.

[0179] Example 45: A device according to Examples 41-44, wherein the protrusion is located on the top of the layer.

[0180] Example 46: The device of Examples 41-45, wherein the edge of the protrusion is set back relative to the edge of the core.

[0181] Example 47: The device of Examples 41-46, wherein at least a portion of the top surface of the core is not covered by the layer.

[0182] Example 48: The device of Example 47, wherein the portion of the top surface of the core is a ring around the periphery of the core.

[0183] Example 49: The device of Examples 41-48, wherein a first sidewall of the layer below the protrusion is substantially coplanar with a second sidewall of the layer above the protrusion.

[0184] Example 50: The device of Example 49, wherein the first sidewall of the layer is shorter than the second sidewall of the layer.

[0185] Example 51: A device comprising: a core, wherein the core includes a glass layer; a pin extending through the thickness of the core; a first solder pad above the pin; and a second solder pad below the pin, wherein the first solder pad and the second solder pad are wider than the pin.

[0186] Example 52: The device of Example 51, wherein the pins are arranged within about 250 μm of the edge of the core.

[0187] Example 53: The device of Example 51 or Example 52, wherein the pins are circular when viewed in plan from above the core.

[0188] Example 54: The device of Examples 51-53, wherein the pin has an hourglass-shaped cross-section.

[0189] Example 55: The apparatus of Example 54, further comprising: a via extending through the thickness of the core, wherein the via is conductive, and wherein a shape of the via is substantially similar to a shape of the pin.

[0190] Example 56: The apparatus of Examples 51-55, further comprising: a plurality of pins extending through the thickness of the core, wherein the plurality of pins are arranged in a ring proximate an outer edge of the core.

[0191] Example 57: The apparatus of Examples 51-56, further comprising: a plurality of pins extending through a thickness of the core, wherein the plurality of pins are arranged in a first column and a second column proximate an outer edge of the core.

[0192] Example 58: The apparatus of Examples 51-57, wherein the pin, the first pad, and the second pad are a monolithic structure.

[0193] Example 59: The apparatus of Examples 51-58, wherein the pin, the first pad, and the second pad comprise a cured build-up film.

[0194] Example 60: The apparatus of Example 59, wherein the pin, the first pad, and the second pad apply a compressive force on the core.

Claims

1. A device comprising: a core having a first width, wherein the core comprises a glass layer; a via extending through a thickness of the core, wherein the via is electrically conductive; a first layer over the core, wherein the first layer comprises a second width less than the first width; and A second layer is below the core, wherein the second layer comprises a third width that is less than the first width.

2. The device according to claim 1, wherein: The edge surface of the first layer is set back by a maximum of about 250 μm relative to the edge surface of the core.

3. The device according to claim 1 or 2, wherein: An edge surface of the first layer is along a first plane and an edge surface of the core is along a second plane, wherein the first plane intersects the second plane.

4. The device according to claim 3, wherein: A top surface of the first layer is narrower than a bottom surface of the first layer.

5. The device according to claim 1 or 2, further comprising: A groove is formed through a thickness of the first layer, wherein the islands of the first layer are disposed between an edge surface of the first layer and the groove.

6. The device according to claim 5, wherein: The width of the islands of the first layer is up to about 200 μm.

7. The device according to claim 1 or 2, wherein: An outer edge surface of the first layer includes a protrusion between a top surface and a bottom surface of the first layer.

8. The device according to claim 1 or 2, wherein: The core has an outer region and an inner region, wherein the outer region has a first defect density and the inner region has a second defect density lower than the first defect density.

9. The device according to claim 8, wherein: The outer region has a width of up to about 200 μm from the edge of the core to the outer edge surface of the inner region.

10. The device according to claim 1 or 2, wherein: The first layer and the second layer include organic buildup layers.

11. An apparatus comprising: a core, wherein the core comprises glass; and a layer over the core, wherein the layer comprises an organic buildup film; and A groove passes through the thickness of the layer, wherein the groove is a ring disposed at a distance from an outer edge surface of the layer.

12. The apparatus according to claim 11, further comprising: A lining layer is disposed along an outer sidewall of the groove.

13. The device according to claim 12, wherein: The liner includes copper.

14. The device according to claim 11, 12 or 13, wherein: The outer edge surface of the layer is substantially coplanar with the outer edge surface of the core.

15. The device according to claim 11, 12 or 13, wherein: The trench has a sidewall having an inclined profile.

16. An apparatus comprising: a core, wherein the core comprises a glass layer; a layer over the core; and An insert is at least partially embedded in the core, wherein the insert comprises a different material than the glass layer.

17. The device according to claim 16, wherein: The insert has a coefficient of thermal expansion (CTE) that is within 20% of the CTE of the core, and wherein the modulus of the insert is greater than the modulus of the core.

18. The device according to claim 16 or 17, wherein: The insert is an organic dielectric material that fills the grooves into the surface of the core.

19. The device according to claim 16 or 17, wherein: The insert passes through a thickness of the core, and wherein a first pad is above the insert and a second pad is below the insert.

20. The device of claim 19, comprising a cured deposited film.

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