Finger-shaped crossed through hole and lead wire of assembly

Abstract

The invention relates to a component finger-crossing via and a lead. Aspects of the present disclosure relate to systems and methods for reducing inductance on an integrated circuit package of a memory subsystem. The memory subsystem is also hereinafter referred to as a "memory device". An example of a memory subsystem is a memory system, such as an SSD, and may be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA) and a ball grid array (EGA).

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with application date of February 19, 2020, application number 202080023558.5, and invention name “Component finger-shaped cross-type through holes and leads”.

[0003] Priority application

[0004] This application claims the benefit of priority to U.S. application Serial No. 16 / 280,570, filed on February 20, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0005] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to systems and methods for reducing inductance on integrated circuits. Background Art

[0006] The memory subsystem may be a storage system such as a solid state drive (SSD) and may include one or more memory components that store data. The memory components may be non-volatile memory components and volatile memory components, such as in the form of integrated circuit packages including pin grid arrays (PGAs). In general, a device or host system may utilize the memory subsystem to store data at and retrieve data from the memory components. Summary of the invention

[0007] According to one embodiment of the present disclosure, a storage system is provided. The storage system includes: a substrate material and a plurality of memory components positioned on the substrate material. Each of the plurality of memory components includes: a package that supports the arrangement of a plurality of electrical contacts; the plurality of electrical contacts include a power lead group and a ground lead group, the power lead group interdigitates among the ground lead group; and the arrangement of the plurality of electrical contacts includes paired groups of electrical contacts, the paired groups of electrical contacts at least include a first paired group and a second paired group and a third paired group adjacent to the first paired group, each paired group includes a power lead and a ground lead at a first distance from each other, wherein the first paired group is at a second distance from the second paired group and the first paired group is at a third distance from the third paired group and wherein the first distance, the second distance and the third distance are all different values, and each of the second distance and the third distance is greater than the first distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0010] Figure 2 is a flow chart of an example method of reducing inductance on an integrated circuit package according to some embodiments of the present disclosure.

[0011] Figure 3A and 3B is a diagram depicting an interdigitated pin arrangement according to some embodiments of the present disclosure.

[0012] Figure 4 is a diagram depicting a substrate layout according to some embodiments of the present disclosure.

[0013] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to systems and methods for reducing inductance on integrated circuit packages by interdigitating pin arrangements. Although the present disclosure may relate to any integrated circuit, it is described herein by way of example with reference to a memory subsystem. The memory subsystem is also referred to below as a "memory device." An example of a memory subsystem is a storage system, such as an SSD, and may be embodied as an integrated circuit package, including, but not limited to, a pin grid array (PGA), a single in-line package (SIP), a standard or non-standard dual in-line package (DIP), a ceramic dual in-line package (CDIP), a quad in-line package (QIP), a narrow dual in-line package (SDIP), a zigzag in-line package (ZIP), a ceramic column grid array (CCGA), a column grid array (CGA), a leadless lead frame package (LLP), a land grid array (LGA), a low temperature co-fired ceramic (LTCC), a multi-chip module (MCM), a micro surface mount device extended technology (MICRO SMDXT), a quad flat package (QFP), a small outline package (SOP), a ball grid array (BGA), and a chip scale package (CSP). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the storage subsystem and may request data to be retrieved from the storage subsystem.

[0015] Memory subsystems in the form of integrated circuits have become common components in computer systems ranging from mobile phones to mission-critical server systems. As reliance on these memory subsystems has increased, so has the need for performance improvements in the components of the memory subsystems. As a result, the demands on the components have led to an increase in the area of ​​the integrated circuits, while design constraints continue to shrink the physical size of the same components. As a result, inductive effects within the components have become a factor whose impact on performance must be managed by designers of such components, often resulting in a compromise in the overall performance of the component.

[0016] For example, components such as NAND gates (NAND), dynamic random access memory (DRAM), and SSD controllers transition from a low power sleep state to a high power, high performance state. Current travels through the power delivery network as it is delivered to the components. In a conventional layout, during a fast transition, the current traveling through the delivery network creates an inductance that momentarily reduces the voltage at the components themselves. The reduced voltage can cause device resets or data corruption. Existing techniques to mitigate the voltage reduction at the components require higher voltages (and therefore higher power).

[0017] The most common technique to address these inductive effects is to add shields or buffers between signal lines to reduce noise. While such techniques are effective in reducing inductive effects in some cases, such solutions are not effective in reducing inductive effects without significant compromises in other areas, such as increased latency, component cost, and size.

[0018] Aspects of the present disclosure address the above and other deficiencies by providing systems and methods that reduce the negative effects of inductance on components, and more specifically in components in a memory subsystem. Such components are externally attached on the top and bottom of a substrate of a device (described herein by way of example in the form of a printed circuit board). In particular, vias are used to transition from external components to the internal conductive layers of the printed circuit board. Voltage regulators and capacitors can be connected to components mounted to the printed circuit board, such as NAND, DRAM, and SSD controllers, in order to improve power delivery and reduce noise.

[0019] This connection between the voltage regulator, capacitor, and components has an inherent geometry-dependent inductance, where the inductance presents an impedance to high-speed switching that is proportional to both the speed and the inductance value. The impedance increases the voltage dropped across the connection and thus reduces the voltage at the component requiring power. Therefore, reducing the inductance reduces the voltage drop and increases the voltage at the component.

[0020] Example embodiments described herein use interdigitation to address the problem of negative effects of inductance on components. Interdigitation includes interlocking or linking of components or elements, similar to the interlinking of the fingers of two hands locked together. For example, in the context of vias and leads, interdigitation of power vias and ground vias can be represented as an alternating arrangement of power vias and ground vias. Thus, the power vias are positioned adjacent to one or more ground vias. Aspects of the present disclosure apply the same or similar methods to memory subsystems and components, including but not limited to NAND, DRAM, and SSD controllers.

[0021] Such components are typically embodied in an integrated circuit package having a standard lead configuration (e.g., the Joint Electron Device Engineering Consultants (JEDEC) standard pin configuration), wherein the through-holes of the printed circuit board are configured to accept the leads of the integrated circuit package, such that the location of the through-holes corresponds to the location of the leads on the integrated circuit package. Thus, a signal can travel through the through-holes and into its corresponding lead on the integrated circuit package, and vice versa. The integrated circuit package includes leads, such as pillars, pads, or pins, each of which requires a corresponding through-hole transition. Due to the package lead density and through-hole size, the placement of through-holes on the substrate is limited to locations near the corresponding leads of the component. However, there is some flexibility for some other leads, allowing the through-holes to be arranged in a cross-finger type manner. When viewed in a two-dimensional top view, the through-holes appear in a checkerboard pattern, with the different colored blocks of the checkerboard corresponding to power through-holes (e.g., red squares) and ground through-holes (black squares), respectively.

[0022] The basic mutual inductance principle is that currents flowing in opposite directions reduce mutual inductance, while currents flowing in the same direction increase mutual inductance. The interdigitated pattern applies this principle to reduce mutual inductance across vias of an integrated circuit package. Thus, according to some example embodiments, power vias are placed adjacent to ground vias in an alternating power-to-ground "checkerboard" pattern.

[0023] According to some example embodiments, a memory component of a memory subsystem may be configured such that a plurality of electrical contacts (including both power and ground component pins) protruding from a package of the memory component are arranged such that the power leads are interdigitated among the ground leads. Similarly, a substrate is configured to receive the memory component by applying the same principles to power and ground vias distributed along a surface of the substrate. For example, the power and ground vias may be arranged such that the power vias are interdigitated among the ground vias.

[0024] In some embodiments, the vias (and therefore the corresponding leads) are arranged in an alternating interdigitated pattern such that the power vias are immediately adjacent to and in front of the ground vias, and likewise, the power leads are immediately adjacent to and in front of the ground leads. In further example embodiments, the vias are grouped together in pairs such that a pair includes a ground via and a power via, and wherein the vias of the pair are a first threshold distance from each other, and any two pairs are a second threshold distance from each other. The leads of the memory component may be similarly arranged such that pairs of leads may be grouped into power and ground pairs, wherein the leads of the pairs are a threshold distance from each other.

[0025] Thus, interdigitation of vias in a layout as discussed above can result in a 22% reduction in effective inductance in the power delivery network, which translates into a 22% increase in performance (bandwidth). For example, in a non-interdigitated layout, the effective inductance can be calculated as:

[0026]

[0027] The modified layout implementing the above interleaving technique can be calculated as:

[0028]

[0029] As seen above, within the power delivery network utilizing interdigitated component pins, the effective inductance is reduced by 22%.

[0030]

[0031] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is illustrated. The memory subsystem 110 may include media, such as memory components 112-1 to 112-N. The memory components 112-1 to 112-N may be volatile memory components, non-volatile memory components, or a combination of the like. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0032] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110 so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection, whether wired or wireless, or a direct communication connection (e.g., without an intermediary component), including connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112-1 to 112-N when the memory subsystem 110 is coupled to the host system 120 through a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0033] The memory components 112-1 to 112-N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include non-AND (NAND) type flash memory. Each of the memory components 112-1 to 112-N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC) or four-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND type flash memory are described, the memory components 112-1 to 112-N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112-1 to 112-N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), non-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory may perform bit storage with a stackable cross-grid data access array based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without previously erasing the non-volatile memory cells. Furthermore, as described above, the memory cells of the memory components 112-1 to 112-N may be grouped into data blocks, which may refer to cells of a memory component used to store data. In some embodiments, the memory components 112-1 to 112-N may be embodied in an integrated circuit package, including but not limited to a pin grid array (PGA), a single in-line package (SIP), a standard or non-standard dual in-line package (DIP), a ceramic dual in-line package (CDIP), a quad in-line package (QIP), a narrow dual in-line package (SDIP), a zigzag in-line package (ZIP), a ceramic column grid array (CCGA), a column grid array (CGA), a leadless lead frame package (LLP), a land grid array (LGA), a low temperature co-fired ceramic (LTCC), a multi-chip module (MCM), micro surface mount device extended technology (MICRO SMDXT), a quad flat package (QFP), a small outline package (SOP), a ball grid array (BGA), and a chip scale package (CSP).Thus, memory components 112-1 through 112-N may be inserted or otherwise attached to a substrate associated with memory subsystem 110, wherein the substrate includes an arrangement of a plurality of vias.

[0034] The memory subsystem controller 115 (hereinafter referred to as "controller") can communicate with the memory components 112-1 to 112-N to perform operations such as reading data, writing data, or erasing data at the memory components 112-1 to 112-N, as well as other such operations. The controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] In general, the controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112-1 to 112-N. The controller 115 may be responsible for other operations, such as wear leveling operations, obsolete item collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 112-1 to 112-N. The controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory components 112-1 to 112-N, and convert responses associated with the memory components 112-1 to 112-N into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112-1 to 112-N.

[0037] Figure 2 2 is a flow chart of an example method 200 of reducing inductance on an integrated circuit package according to some embodiments of the present disclosure. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0038] At operation 205, the integrated circuit package of the memory components 112-1 to 112-N is configured to support a plurality of electrical contacts, such as pins or leads. For example, the integrated circuit package includes a BGA or PGA, where the plurality of electrical contacts includes a set of power leads and ground leads.

[0039] Thereafter, at operation 210, a plurality of electrical contacts are arranged on the integrated circuit package such that the set of power leads are interdigitated among the set of ground leads. As an illustrative example, consider a checkerboard, where black and white squares are arranged in an alternating pattern such that a black square is always in front of and behind a white square, and vice versa. Similarly, interdigitating the power leads among the ground leads may include arranging the power leads and the ground leads in a checkerboard pattern such that a power lead is always in front of and behind a ground lead, and vice versa.

[0040] In some embodiments, the leads may be grouped into power and ground pairs such that the pairs of leads are a first threshold distance from each other and wherein each pair of leads is a second threshold distance from an adjacent pair of leads. The first threshold distance may be shorter than the second threshold distance.

[0041] As depicted in operation 215 of method 200, a plurality of vias of the substrate are configured to receive memory components 112-1 to 112-N by arranging the vias in a matching interdigitated pattern. For example, the plurality of vias include power vias and ground vias. Thus, the plurality of vias are arranged along the substrate such that the power vias are interdigitated among the ground vias.

[0042] Figure 3A300A is a diagram depicting an interdigitated arrangement of leads 302 (hereinafter referred to as "leads 302") of a memory component (e.g., memory component 112) according to some embodiments of the present disclosure. As seen in FIG. 300A, leads 302 include a set of power leads (e.g., power lead 304, power lead 310, power lead 312, power lead 314) and ground leads (e.g., ground lead 306, ground lead 316, ground lead 318, and ground lead 320). Leads 302 include electrical contacts distributed on an integrated circuit package (e.g., a BGA or PGA).

[0043] According to certain example embodiments, and as seen in FIG. 300A, the leads 302 may be arranged into interdigitated pairs of power and ground leads (e.g., pair 308) such that the power lead 304 is separated from the ground lead 306 by a first threshold distance 322, and pair 308 is separated from other pairs of leads (e.g., pair 328 and pair 330) by second and third thresholds 324 and 326, wherein the first, second and third thresholds 322, 324 and 326 are all distinct values.

[0044] For example, a first threshold distance 322 defining a gap between power lead 304 and ground lead 306 of pair 308 may be configured to be as small as possible so as to minimize inductance between pair 308, while second and third threshold distances 324 and 326 are spaced to optimize so as to reduce crosstalk between any two lead pairs (e.g., pair 328 and pair 330) including adjacent lead pairs.

[0045] Figure 3B FIG. 300B is a diagram depicting an interdigitated arrangement of vias 332 according to some embodiments of the present disclosure. As seen in FIG. 300B , vias 332 include a set of power vias (e.g., power vias 334, power vias 336, power vias 338, power vias 340, and power vias 356) and ground vias (e.g., ground vias 342, ground vias 344, ground vias 346, ground vias 348, ground vias 350, and ground vias 352). Vias 332 may be arranged in an alternating, interdigitated pattern (e.g., a checkerboard pattern) along the substrate and correspond to a plurality of leads (e.g., leads 302).

[0046] According to certain example embodiments, vias 332 may be arranged on the substrate to maximize the size of webbing 354 between power vias on the substrate. In such embodiments, webbing 354 provides protection from short circuits between power vias, such as power via 340 and power via 356.

[0047] Figure 44 is a diagram 400 depicting a substrate layout 405 according to some embodiments of the present disclosure. As seen in diagram 400, substrate layout 405 includes an interdigitated arrangement of vias 410 configured to accept and reduce inductance on an integrated circuit package (e.g., a PGA or BGA). The interdigitated arrangement of vias 410 of diagram 400 includes an illustration of pin routing between vias, depicted as connectors between each point (via) in the interdigitated arrangement of vias 410.

[0048] As seen in diagram 400, the interdigitated arrangement of vias 410 may be similar to Figure 3B 332, wherein the arrangement of vias 410 includes alternating and interdigitated distribution of power and ground vias and is configured to receive a set of interdigitated leads, such as Figure 3A Lead 302 is depicted in FIG.

[0049] As seen in diagram 400, a plurality of ground vias 415 may be arranged on substrate layout 405 such that a plurality of power vias 420 are interdigitated among the plurality of power vias 420 such that a power via is always in front of and behind a ground via.

[0050] Figure 5 An example machine illustrating a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0051] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0052] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 518, which communicate with each other via a bus 530.

[0053] The processing device 502 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 502 may also be one or more special purpose processing devices, such as an ASIC, an FPGA, a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0054] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 526 by the computer system 500, the instructions 526 may also reside, in whole or in part, within the main memory 504 and / or within the processing device 502, which also constitute machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0055] Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be taken to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0056] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0057] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into similarly represented physical quantities within a computer system's memories or registers or other such information storage systems.

[0058] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specifically constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0059] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0060] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, and the like.

[0061] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader scope of embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

[0062] Examples

[0063] Example 1 is a system comprising: a substrate material; and a plurality of memory components positioned on the substrate material, each of the plurality of memory components comprising: a package supporting an arrangement of a plurality of electrical contacts; the plurality of electrical contacts comprising a set of power pins and a set of ground pins; and the arrangement of the plurality of electrical contacts comprising the set of power pins interdigitated among the set of ground pins.

[0064] In Example 2, according to the subject matter of Example 1, wherein the substrate material includes a plurality of vias corresponding to each of the plurality of electrical contacts of the package, the plurality of vias including a set of power vias and a set of ground vias.

[0065] In Example 3, according to the subject matter described in Examples 1 and 2, the arrangement of the plurality of electrical contacts is a first arrangement, the substrate material includes a second arrangement of the plurality of through holes, and the second arrangement of the plurality of through holes includes the group of power through holes interdigitated among the group of ground through holes.

[0066] In Example 4, according to the subject matter described in Examples 1, 2, and 3, the arrangement of the plurality of electrical contacts is a first arrangement, the substrate material includes a second arrangement of the plurality of through holes, and the second arrangement of the plurality of through holes includes pairs of power through holes and ground through holes located at a first distance from each other, wherein each pair is a second distance from another pair.

[0067] In Example 5, according to the subject matter of Example 1, wherein the arrangement of the plurality of electrical contacts further comprises an alternating pattern including power pins from among the set of power pins and ground pins from among the set of ground pins.

[0068] In Example 6, according to the subject matter of Example 1, wherein the package includes a pin grid array.

[0069] In Example 7, according to the subject matter of Example 1, the arrangement of the plurality of electrical contacts includes a gap of minimum thickness between each contact among the plurality of electrical contacts.

[0070] Example 8 is a method for reducing inductance on an integrated circuit package, comprising: configuring the integrated circuit package to support multiple electrical contacts including a group of power pins and a group of ground pins; and arranging the multiple electrical contacts on the integrated circuit package so that the group of power pins are interdigitated among the group of ground pins.

[0071] In Example 9, according to the subject matter described in Example 8, the method further includes: preparing a substrate to receive the integrated circuit package, the preparing the substrate including: orienting a plurality of through holes corresponding to each of the plurality of electrical contacts of the integrated circuit package on the substrate, the plurality of through holes including a group of power through holes and a group of ground through holes.

[0072] In Example 10, according to the subject matter of Examples 8 and 9, the set of power vias are interdigitated among the set of ground vias along the substrate.

[0073] In Example 11, according to the subject matter of Examples 8, 9, and 10, wherein the orienting the plurality of vias further includes: arranging one or more pairs of power and ground vias at locations along the substrate, the locations of the one or more pairs of power and ground vias are located at a threshold distance from each other.

[0074] In Example 12, according to the subject matter of Example 8, the arrangement of the plurality of electrical contacts further comprises: an alternating pattern of power pins and ground pins.

[0075] In Example 13, according to the subject matter of Example 8, the integrated circuit package includes a pin grid array.

[0076] In Example 14, according to the subject matter of Example 8, the arrangement of the plurality of electrical contacts includes one or more gaps between each of the plurality of electrical contacts, the one or more gaps comprising a minimum distance.

[0077] Example 15 is a non-transitory computer-readable storage medium comprising: a plurality of memory components, each of the plurality of memory components comprising: a package supporting an arrangement of a plurality of electrical contacts; the plurality of electrical contacts comprising a set of power pins and a set of ground pins; and the arrangement of the plurality of electrical contacts comprising the set of power leads interdigitated among the set of ground leads.

[0078] In Example 16, the subject matter of Example 15 further includes a substrate material including a plurality of vias corresponding to the plurality of electrical contacts, the plurality of vias including a set of power vias and a set of ground vias.

[0079] In Example 17, according to the subject matter described in Examples 15 and 16, the arrangement of the plurality of electrical contacts is a first arrangement, the substrate material includes a second arrangement of the plurality of through holes, and the second arrangement of the plurality of through holes includes the group of power through holes interdigitated among the group of ground through holes.

[0080] In Example 18, according to the subject matter of Example 15, the arrangement of the plurality of electrical contacts further comprises: an alternating pattern including power pins from among the set of power pins and ground pins from among the set of ground pins.

[0081] In Example 19, the subject matter of Example 15 wherein the package comprises a pin grid array.

[0082] In Example 20, according to the subject matter of Example 15, the arrangement of the plurality of electrical contacts includes a gap of minimum thickness between each contact among the plurality of electrical contacts.

Claims

1. A storage system, comprising: Substrate material; and a plurality of memory components positioned on the substrate material, each of the plurality of memory components comprising: a package that supports the arrangement of a plurality of electrical contacts; The plurality of electrical contacts include a power lead set and a ground lead set, wherein the power lead set is interdigitated among the ground lead set; and The arrangement of the plurality of electrical contacts comprises paired groups of electrical contacts, the paired groups of electrical contacts comprising at least a first paired group and a second paired group and a third paired group adjacent to the first paired group, each paired group comprising a power lead and a ground lead at a first distance from each other, wherein the first paired group is at a second distance from the second paired group and the first paired group is at a third distance from the third paired group and wherein the first distance, the second distance and the third distance are all different values, each of the second distance and the third distance being greater than the first distance.

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