Electronic device

Abstract

The invention provides an electronic device. The electronic device has a central region and a peripheral region surrounding the central region. The electronic device comprises a substrate, a through hole, a buffer layer, a first circuit structure, an electronic component and a first connecting pad. The substrate has a first surface and a second surface opposite to the first surface. The through hole penetrates through the substrate and is provided with a first through hole and a second through hole. The buffer layer covers the first surface, the second surface, the inner wall of the first through hole and the inner wall of the second through hole. The first circuit structure is disposed on the first surface. The electronic component is disposed on the first circuit structure and corresponds to the central region. The first connecting pad is arranged on the second surface. The first connecting pad is electrically connected with the electronic component through the through hole and the first circuit structure. The first through hole corresponds to the central area, the second through hole corresponds to the peripheral area, and the width of the second through hole is larger than that of the first through hole. The electronic device disclosed by the invention can improve the problem of warping.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device capable of improving the warping problem. Background Art

[0002] Electronic devices or spliced ​​electronic devices including semiconductor components have been widely used in different fields such as communication, display, automobile or aviation. With the rapid development of electronic devices, electronic devices are developing towards being lighter and thinner, so the reliability or quality requirements of electronic devices are higher. Summary of the invention

[0003] The present disclosure provides an electronic device which can improve the warping problem.

[0004] According to an embodiment of the present disclosure, an electronic device has a central area and a peripheral area surrounding the central area. The electronic device includes a substrate, a through hole, a buffer layer, a first circuit structure, an electronic component and a first pad. The substrate has a first surface and a second surface opposite to the first surface. The through hole passes through the substrate and has a first through hole and a second through hole. The buffer layer covers the first surface, the second surface, the inner wall of the first through hole and the inner wall of the second through hole. The first circuit structure is arranged on the first surface. The electronic component is arranged on the first circuit structure and corresponds to the central area. The first pad is arranged on the second surface. The first pad is electrically connected to the electronic component with the first circuit structure through the through hole. The first through hole corresponds to the central area, the second through hole corresponds to the peripheral area, and the width of the second through hole is greater than the width of the first through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0006] Figure 1A A schematic top view of an electronic device according to a first embodiment of the present disclosure;

[0007] Figure 1B for Figure 1A A schematic cross-sectional view of an electronic device along a section line II';

[0008] Figure 2 A cross-sectional schematic diagram of an electronic device according to a second embodiment of the present disclosure;

[0009] Figure 3 A cross-sectional schematic diagram of an electronic device according to a third embodiment of the present disclosure;

[0010] Figure 4 A cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present disclosure;

[0011] Figure 5is a cross-sectional schematic diagram of an electronic device according to a fifth embodiment of the present disclosure;

[0012] Figure 6 It is a cross-sectional schematic diagram of an electronic device according to a sixth embodiment of the present disclosure.

[0013] Description of Figure Numbers

[0014] 10, 100, 100a, 100b, 100c, 100d, 100e: electronic devices;

[0015] 101: Central District;

[0016] 102: peripheral area;

[0017] 110: substrate;

[0018] 111: groove;

[0019] 111a: bottom surface;

[0020] 111b, 1211, 1221: inner wall;

[0021] 110a: first side;

[0022] 110b: second side;

[0023] 110c, 140a, 160c, 177a1: side surface;

[0024] 120: through hole;

[0025] 121: first through hole;

[0026] 122: second through hole;

[0027] 123: third through hole;

[0028] 124: fourth through hole;

[0029] 130: buffer layer;

[0030] 140, 140d, 140e: first circuit structure;

[0031] 141, 144, 147, 171, 174, 177, 1711, 1712, 177a, 191: conductive layer; 142, 1421, 145, 172, 1721, 175, 192: dielectric layer;

[0032] 143, 1431, 146, 173, 1731, 176, 193: through holes;

[0033] 1471, 1771: concave;

[0034] 148, 178: anti-warping layer;

[0035] 150: conductive parts;

[0036] 160, 200, 300: electronic components;

[0037] 160a: active surface;

[0038] 160b: back;

[0039] 161, 210, 310: pads;

[0040] 170, 170e: second circuit structure;

[0041] 1712a: First floor;

[0042] 1712b: Second floor;

[0043] 177a2: surface;

[0044] 180: first pad;

[0045] 190: component integration layer;

[0046] 194: Components;

[0047] 250: optical fiber;

[0048] 300a: side;

[0049] 350: adhesive layer;

[0050] 360: Base glue;

[0051] AM: counterpoint mark;

[0052] CM: conductive material;

[0053] CL1, CL2: Conductor layer

[0054] D1, D2, D3: width;

[0055] IL1: first insulation layer;

[0056] IL2: second insulation layer;

[0057] HS: heat sink;

[0058] L: depth;

[0059] L1, L2: spacing;

[0060] L3, L4: distance;

[0061] PCB: circuit board;

[0062] SL1, SL2: Seed layer

[0063] SR1, SR2: solder mask;

[0064] T1, T2, T3, T4, T5: thickness;

[0065] X, Y, Z: direction;

[0066] θ: angle. DETAILED DESCRIPTION

[0067] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not intended to limit the scope of the present disclosure.

[0068] In the following description and claims, the words “including” and “comprising” are open-ended words, and thus should be interpreted as meaning “including but not limited to…”.

[0069] It should be understood that when a component or film layer is referred to as being "on" or "connected to" another component or film layer, it may be directly on or directly connected to the other component or layer, or there may be an intervening component or film layer between the two (indirect case). Conversely, when a component is referred to as being "directly on" or "directly connected to" another component or film layer, there may be no intervening components or film layers between the two.

[0070] Although the terms "first", "second", "third" ... can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by first, second, third ... according to the order of components declared in the claims. Therefore, in the following description, the first component may be the second component in the claims.

[0071] In the text, the terms "about", "approximately", "substantially", and "roughly" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The numbers given here are approximate numbers, that is, in the absence of specific descriptions of "about", "approximately", "substantially", and "roughly", the meanings of "about", "approximately", "substantially", and "roughly" can still be implied.

[0072] In some embodiments of the present disclosure, terms such as "connection" and "interconnection" may refer to two structures being in direct contact, or two structures not being in direct contact, with other structures disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed. In addition, the term "coupling" includes any direct and indirect electrical connection means.

[0073] In some embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the area, width, thickness, or height of each component, or the distance or spacing between components. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including a component to be measured, and the area, width, thickness, or height of each component, or the distance or spacing between components may be measured.

[0074] In the present disclosure, the definition of roughness judgment can be observed by SEM. On the concave-convex surface, it can be seen that the peaks and valleys of the surface undulations have a distance difference of 0.15 micrometers (μm) to 1 μm. The measurement of roughness judgment can include using SEM, transmission electron microscope (TEM), etc., to observe the surface undulations at the same appropriate magnification, and by taking a sample of unit length (for example, 10 μm) to compare the undulations, which is its roughness range. Here, "appropriate magnification" means that at least one surface can see at least 10 undulating peaks in the field of view of this magnification. Roughness (Rz) or average roughness (Ra).

[0075] The electronic device disclosed herein may include a display device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include a liquid crystal light emitting diode; the light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED or a quantum dot light emitting diode (QD, which may be, for example, QLED, QDLED), fluorescence, phosphorescence or other suitable materials, and the materials may be arranged and combined in any manner, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. The electronic device may include an electronic unit, wherein the electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. It should be noted that the electronic device disclosed herein may be various combinations of the above-mentioned devices, but is not limited thereto. The electronic device disclosed herein may be applied to, for example, a power module, a semiconductor packaging device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may include a system on a chip (SoC), a system in a package (SiP), an antenna in package (AiP) or various combinations of the above-mentioned devices, but is not limited thereto. It should be noted that the electronic device may be any combination of the aforementioned arrangements, but is not limited thereto. The following will illustrate the contents of the present disclosure using an electronic device, but the present disclosure is not limited thereto.

[0076] It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0077] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0078] Figure 1A It is a top view schematic diagram of an electronic device according to a first embodiment of the present disclosure. Figure 1B for Figure 1AA schematic cross-sectional view of an electronic device along section line II'. For the sake of clarity and convenience of description, Figure 1A Some components in the electronic device are omitted (eg, the buffer layer 130 , the first circuit structure 140 , the conductive element 150 , the second circuit structure 170 , the first pad 180 , the first insulating layer IL1 , and the second insulating layer IL2 , but not limited thereto).

[0079] Please also refer to Figure 1A and Figure 1B The electronic device 10 of this embodiment has a plurality of electronic devices 100 ( Figure 1A 9 electronic devices 100 are schematically shown, but not limited to this) and multiple alignment marks AM. Each electronic device 100 has a central area 101 and a peripheral area 102 surrounding the central area 101, and each electronic device 100 may include a substrate 110, a through hole 120, a buffer layer 130, a first circuit structure 140, a conductive member 150, an electronic component 160, a second circuit structure 170, a first pad 180, a first insulating layer IL1 and a second insulating layer IL2. In some embodiments, the central area 101 can be regarded as an active area of ​​the electronic device 100, but not limited to this. During the manufacturing process of the electronic device 10, multiple alignment marks AM can be used to pick and place the electronic component 160 or align other components, but not limited to this. According to some embodiments, multiple alignment marks AM can be set on the surface of the substrate 110. According to some embodiments, a plurality of alignment marks AM may be disposed in the substrate 110 , that is, along the normal direction (direction Z) of the substrate 110 , there is a distance between the alignment marks AM and the surface of the substrate 110 .

[0080] In this embodiment, the electronic device 100 may be applied to a power module, a semiconductor packaging device, a display device, a light emitting device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto.

[0081] Specifically, the substrate 110 has a first surface 110a, a second surface 110b opposite to the first surface 110a, and a side surface 110c connecting the first surface 110a and the second surface 110b. The substrate 110 may include a hard substrate, a soft substrate, or a combination thereof. For example, the material of the substrate 110 may include glass, quartz, sapphire, ceramic, wafer, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination thereof, but is not limited thereto.

[0082] The through hole 120 passes through the substrate 110. The through hole 120 is filled with a conductive material CM, and the through hole 120 can electrically connect the first circuit structure 140 and the second circuit structure 170. The through hole 120 has a first through hole 121 and a second through hole 122. The first through hole 121 corresponds to the central area 101, and the first through hole 121 can overlap the electronic component 160 in the direction Z. The second through hole 122 corresponds to the peripheral area 102, and the second through hole 122 does not overlap the electronic component 160 in the direction Z. The first through hole 121 has a width D1 and a depth L, and the second through hole 122 has a width D2 and a depth L. Among them, the width D1 is, for example, the maximum width of the first through hole 121 measured along the direction X, the width D2 is, for example, the maximum width of the second through hole 122 measured along the direction X, and the depth L is, for example, the maximum depth of the first through hole 121 (or the second through hole 122) measured along the direction Z. In this embodiment, the width D2 of the second through hole 122 may be greater than the width D1 of the first through hole 121. Specifically, the ratio of the width D2 of the second through hole 122 to the width D1 of the first through hole 121 may be 1.2 to 3 (i.e., 1.2≤D2 / D1≤3), so as to release stress or improve the warpage problem by increasing the copper ratio of the through hole 120 in the peripheral area 102, but not limited thereto. According to some embodiments, the width D2 of the second through hole 122 may be greater than the width D1 of the first through hole 121, so as to improve the lateral heat dissipation capability of the electronic device, but not limited thereto. In the present embodiment, the ratio of the width to the depth of the through hole 120 (i.e., the ratio of the width D1 to the depth L of the first through hole 121, or the ratio of the width D2 to the depth L of the second through hole 122) may be 0.01 to 0.5 (i.e., 0.01≤D1 / L≤0.5 or 0.01≤D2 / L≤0.5), but is not limited thereto. According to some embodiments, the conductive material CM in the through hole 120 is substantially coplanar with the first surface 110a and the second surface 110b of the substrate 110, and further, along the direction Z, the spacing between the first surface 110a of the substrate 110 and the surface of the conductive material CM or the spacing between the second surface 110b of the substrate 110 and the surface of the conductive material CM is less than or equal to 10 microns.

[0083] In the present embodiment, direction X, direction Y, and direction Z are different directions. For example, direction X is, for example, the extension direction of section line II', and direction Z is, for example, the normal direction of substrate 110 or the normal direction of electronic device 100. Direction X is substantially perpendicular to direction Z, and direction X and direction Z are respectively substantially perpendicular to direction Y, but not limited thereto.

[0084] The buffer layer 130 may at least cover the first surface 110a of the substrate 110, the second surface 110b of the substrate 110, a portion of the inner wall 1211 of the first through hole 121, and a portion of the inner wall 1221 of the second through hole 122. The buffer layer 130 has a buffering property, and thus can protect the substrate 110 to reduce damage to the substrate 110 (for example, reducing cracks in the glass substrate) caused by stress generated by subsequent processes (for example, forming the conductive material CM in the through hole 120, forming the first circuit structure 140, and forming the second circuit structure 170). The material of the buffer layer 130 may include polyimide, parylene, benzocyclobutene (BCB), epoxy, polycarbonate, polyethylene terephthalate, polyethylene naphthalate (PEN), polymer, other suitable buffer materials, inorganic materials, or a combination thereof, but is not limited thereto.

[0085] In this embodiment, the toughness of the buffer layer 130 may be 0.1 kJ / m 2 Up to 100kJ / m 2 , but not limited thereto. Toughness is measured, for example, by the standard test method for tensile properties of plastics (ASTM D638). Specifically, the component to be subjected to the tensile test is first separated from the electronic device 100; then, two marks are pre-marked on the component, where the distance between the two marks is called the gage length; then, the component is stretched using a tensile machine (such as a universal testing machine) so that the gage length is gradually extended during the tensile test. Toughness can be obtained by calculating the area under the stress-strain curve (using integration).

[0086] The buffer layer 130 has a thickness T1. The thickness T1 is, for example, the maximum thickness of the buffer layer 130 covering the first surface 110a and the second surface 110b of the substrate 110 measured along the direction Z, or the thickness T1 is, for example, the maximum thickness of the buffer layer 130 covering the inner wall 1211 of the first through hole 121 and the inner wall 1221 of the second through hole 122 measured along the direction X. In the present embodiment, the thickness T1 of the buffer layer 130 may be 0.01 micrometers (μm) to 10 micrometers, but is not limited thereto. In the present embodiment, the ratio of the thickness T1 of the buffer layer 130 to the width D1 of the first through hole 121 (or the width D2 of the second through hole 122) may be 0.02 to 0.2 (i.e., T1 / D1=0.02-0.2 or T1 / D2=0.02-0.2). Through the above design, the substrate 110 can be provided with a certain degree of protection to prevent the substrate 110 from breaking, but is not limited thereto.

[0087] The first circuit structure 140 is disposed on the first surface 110a of the substrate 110, and the first circuit structure 140 may expose a portion of the buffer layer 130 disposed on the first surface 110a. The first circuit structure 140 may be electrically connected to the first through hole 121 or the second through hole 122. The first circuit structure 140 may be electrically connected to the second circuit structure 170 in the direction Z through the through hole 120, thereby shortening the signal transmission path between the two, thereby reducing signal loss. The first circuit structure 140 includes a conductive layer 141, a dielectric layer 142, a through hole 143, a conductive layer 144, a dielectric layer 145, a through hole 146, and a conductive layer 147. The conductive layer 141 is disposed on the first surface 110a of the substrate 110 and on the buffer layer 130. A portion of the conductive layer 141 may contact and electrically connect to the first through hole 121, and another portion of the conductive layer 141 may contact and electrically connect to the second through hole 122. The dielectric layer 142, the conductive layer 144, the dielectric layer 145 and the conductive layer 147 are stacked alternately on the conductive layer 141 in sequence along the direction Z. The through hole 143 and the through hole 146 are filled with a conductive material CM. The through hole 143 penetrates the dielectric layer 142 and electrically connects the conductive layer 144 and the conductive layer 141, and the through hole 146 penetrates the dielectric layer 145 and electrically connects the conductive layer 147 and the conductive layer 144. In this embodiment, the conductive layer and the dielectric layer may be a single layer or a multi-layer stack, wherein the material of the conductive layer may include copper, titanium, molybdenum, aluminum or other suitable conductive materials, and the material of the dielectric layer may include polyimide, photosensitive polyimide (PSPI), polybenzoxazole (PBO), epoxy resin, polymer, ajinomoto build-up layer (ABF), silicon oxide (SiOx), silicon nitride (SiNx) or other suitable dielectric materials, but are not limited thereto.

[0088] In the present disclosure, the conductive material CM in the through hole 120, the conductive layer (141, 144, 147) of the first circuit structure 140, or the through hole (143, 146) may include a single layer or a multi-layer stacked structure. For example, when the conductive material CM in the through hole 120 and the conductive layer 141 of the first circuit structure 140 include a multi-layer stacked structure, it may include multiple sub-layers, one of which may be a seed layer (SL1, SL2), and one sub-layer may be a conductor layer (CL1, CL2), the seed layer SL1 may be disposed on the inner wall (1211, 1221) of the through hole 120, and the seed layer SL2 may be disposed on the first surface 110a and the second surface 110b of the substrate 110. After forming the seed layer (SL1, SL2), a conductor layer (CL1, CL2) may be formed on the seed layer (SL1, SL2), and the thickness of the conductor layer (CL1, CL2) is thicker than the seed layer (SL1, SL2). By providing the seed layer (SL1, SL2), the bonding force between the substrate 110 and the conductive material CM or the conductive layer 141 or the electrical characteristics of the electronic device 100 may be improved, but the invention is not limited thereto. The materials of the seed layer (SL1, SL2) and the conductor layer (CL1, CL2) may include copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), nitride, carbide or other conductive materials or any combination thereof, but the invention is not limited thereto. According to some embodiments, the conductive material CM and the conductive layer 141 can be made separately, that is, the seed layer SL2 can be disposed between the conductive material CM and the conductor layer CL2, and in the direction Z, the conductive material CM does not overlap with the first surface 110a of the substrate 110, or the conductive material CM does not overlap with the second surface 110b of the substrate 110. Through the above design, the stress at the corner of the substrate 110 can be reduced, and the risk of cracking can be reduced, but the present invention is not limited thereto.

[0089] There is a spacing L1 between two adjacent conductive layers 147. The spacing L1 is, for example, the minimum distance between two adjacent conductive layers 147 measured along the direction X, and the conductive layer 147 may be the conductive layer farthest from the substrate 110 (or the conductive layer closest to the electronic component 160) in the first circuit structure 140.

[0090] The dielectric layer 142 and the dielectric layer 145 have a thickness T2. The thickness T2 is, for example, the maximum thickness of the dielectric layer 142 (or the dielectric layer 145) measured along the direction Z. In the present embodiment, the thickness T2 of the dielectric layer 142 and the dielectric layer 145 may be 5 mm to 15 mm, but is not limited thereto. In the present embodiment, the thickness T2 of the dielectric layer 142 or the dielectric layer 145 may be greater than the thickness T1 of the buffer layer 130 (i.e., T2>T1), but is not limited thereto.

[0091] In this embodiment, the first circuit structure 140 and the second circuit structure 170 may be redistribution layers (RDL) and include at least one conductive layer and at least one dielectric layer ( Figure 1B Schematically showing 3 conductive layers and 2 dielectric layers, but not limited to this). The redistribution layer can enable line redistribution and / or further increase the line fan-out area. The redistribution layer can be used to electrically connect different electronic components. The redistribution layer can expand the connection to a wider spacing or redistribute the connection to another connection with a different spacing, and / or the redistribution layer can be used as a substrate for wiring the electrical interface between one connection and another connection. For example, the pitch of two adjacent contact pads at one end of the redistribution structure contacting the electronic component can be less than or equal to the pitch of two adjacent contact pads at one end of the redistribution structure away from the electronic component. Therefore, the redistribution structure can adjust the line fan-out condition or electrically connect a circuit structure / electronic component with a first pitch to a circuit structure / electronic component with a second pitch, but not limited to this. Among them, the step of forming the redistribution layer may include providing a stack of at least one conductive layer and at least one dielectric layer, and the method of forming the redistribution layer may include processes such as yellow light, etching, surface treatment, laser, and electroplating. The surface treatment may include roughening or activating the surface of the dielectric layer or the conductive layer to improve the bonding ability of the dielectric layer or the conductive layer. For example, the bonding force between the dielectric layer and the subsequent film layer may be improved by increasing the surface roughness.

[0092] The conductive member 150 is disposed on the conductive layer 147 of the first circuit structure 140 and in the recess 1471 of the conductive layer 147. The conductive member 150 corresponds to the central area 101. The conductive member 150 can contact and electrically connect the conductive layer 147 of the first circuit structure 140. The material of the conductive member 150 may include tin, copper, nickel, gold, silver, gallium, a combination of the above, the above alloy or other suitable materials, but is not limited thereto. For example, the conductive member 150 may be, for example, a solder ball, a tin ball or a copper pillar (Cu pillar), but is not limited thereto.

[0093] The electronic component 160 is disposed on the first circuit structure 140 and corresponds to the central area 101. The electronic component 160 is disposed on the conductive member 150. The electronic component 160 has an active surface 160a, a back surface 160b, and a side surface 160c. The active surface 160a faces the first circuit structure 140, the active surface 160a and the back surface 160b are opposite to each other, and the side surface 160c connects the active surface 160a and the back surface 160b. The electronic component 160 includes a pad 161 disposed on the active surface 160a. The pad 161 of the electronic component 160 is electrically connected to the conductive layer 147 of the first circuit structure 140 through the conductive member 150. The electronic component 160 may include a passive component or an active component, such as a chip, a known good chip (KGD), a semiconductor structure, a diode, a transistor, a capacitor, a resistor, an inductor, etc., but is not limited thereto.

[0094] The second circuit structure 170 is disposed on the second surface 110b of the substrate 110, and the second circuit structure 170 is located between the substrate 110 and the first pad 180. The second circuit structure 170 can be electrically connected to the first through hole 121 or the second through hole 122. The second circuit structure 170 includes a conductive layer 171, a dielectric layer 172, a through hole 173, a conductive layer 174, a dielectric layer 175, a through hole 176, and a conductive layer 177. The conductive layer 171 is disposed under the second surface 110b of the substrate 110 and under the buffer layer 130. A portion of the conductive layer 171 can contact and electrically connect to the first through hole 121, and another portion of the conductive layer 171 can contact and electrically connect to the second through hole 122. The dielectric layer 172, the conductive layer 174, the dielectric layer 175, and the conductive layer 177 are stacked alternately along the direction Z in sequence under the conductive layer 171. The through hole 173 and the through hole 176 are filled with a conductive material CM, the through hole 173 penetrates the dielectric layer 172 and electrically connects the conductive layer 174 and the conductive layer 171, and the through hole 176 penetrates the dielectric layer 175 and electrically connects the conductive layer 177 and the conductive layer 174. In this embodiment, the conductive layer and the dielectric layer can be a single layer or a multi-layer stack, and the materials of the conductive layer and the dielectric layer can be the same or similar to the conductive layer and the dielectric layer in the first circuit structure 140, so they are not repeated. In some embodiments, the coefficient of thermal expansion (CTE) of the material of the dielectric layer in the second circuit structure 170 can be the same as or different from the coefficient of thermal expansion of the dielectric layer in the first circuit structure 140 to improve the warping problem. According to some embodiments, the material and warping tendency (e.g., downward warping) of the dielectric layer in the second circuit structure 170 may be different from the material and warping tendency (e.g., upward warping) of the dielectric layer in the first circuit structure 140 to improve the warping problem; for example, along the Z direction, when the dielectric layer in the second circuit structure 170 has a warping tendency in which the left and right sides bend downward, the warping problem can be improved by setting the dielectric layer in the first circuit structure 140 to have a warping tendency in which the left and right sides bend upward.

[0095] There is a spacing L2 between two adjacent conductive layers 177. The spacing L2 is, for example, the minimum distance between two adjacent conductive layers 177 measured along the direction X, and the conductive layer 177 may be the conductive layer farthest from the substrate 110 (or the conductive layer closest to the first pad 180) in the second circuit structure 170. In this embodiment, the spacing L1 between two adjacent conductive layers 147 in the first circuit structure 140 is smaller than the spacing L2 between two adjacent conductive layers 177 in the second circuit structure 170, but is not limited thereto.

[0096] The dielectric layer 172 and the dielectric layer 175 have a thickness T3. The thickness T3 is, for example, the maximum thickness of the dielectric layer 172 (or the dielectric layer 175) measured along the direction Z. In the present embodiment, the thickness T3 of the dielectric layer 172 and the dielectric layer 175 may be 5 mm to 15 mm, but is not limited thereto. In the present embodiment, the thickness T3 of the dielectric layer 172 or the dielectric layer 175 may be greater than the thickness T1 of the buffer layer 130 (i.e., T3>T1), but is not limited thereto.

[0097] The conductive layer 171 may include a conductive layer 1711 disposed corresponding to the central area 101 and a conductive layer 1712 disposed corresponding to the peripheral area 102. The conductive layer 1711 has a thickness T4, and the conductive layer 1712 has a thickness T5. The thickness T4 is, for example, the maximum thickness of the conductive layer 1711 measured along the direction Z, and the thickness T5 is, for example, the maximum thickness of the conductive layer 1711 measured along the direction Z. In the present embodiment, the thickness T5 of the conductive layer 1712 may be greater than or equal to 1.5 times the thickness T4 of the conductive layer 1711 (i.e., T5 ≥ 1.5×T4) for shielding EMI or grounding, but is not limited thereto.

[0098] In the present embodiment, the conductive layer 1712 may be a double-layer stack formed by electroplating and / or copper foil. The conductive layer 1712 may include a first layer 1712a and a second layer 1712b, wherein the first layer 1712a contacts the first through hole 121, the second layer 1712b is disposed under the first layer 1712a, and the second layer 1712b surrounds the side surface of the first layer 1712a. For example, after the first layer 1712a is formed by electroplating, the copper foil as the second layer 1712b may be attached under the first layer 1712a; or after the first layer 1712a is formed by electroplating, the surface of the first layer 1712a may be roughened first, and then the copper foil as the second layer 1712b may be attached under the roughened first layer 1712a to enhance the bonding strength. In some embodiments, the copper foil as the second layer 1712b may be used for shielding electromagnetic interference or grounding, but is not limited thereto.

[0099] The first pad 180 is disposed on the second surface 110b of the substrate 110. The first pad 180 can be electrically connected to the electronic component 160 through the through hole 120 and the first circuit structure 140. The first pad 180 can be a solder ball or a tin ball, but is not limited thereto. In addition, in the present embodiment, the first pad 180 can be disposed under the conductive layer 177 of the second circuit structure 170 and in the recess 1771 of the conductive layer 177, and the first pad 180 can be electrically connected to the through hole 120 through the second circuit structure 170, but is not limited thereto. In some embodiments, the second circuit structure may not be provided depending on demand or design requirements, so that the first pad can contact or be electrically connected to the through hole through other components.

[0100] The first insulating layer IL1 is disposed between the electronic component 160 and the first circuit structure 140. The first insulating layer IL1 may surround the conductive member 150 and the conductive layer 147. In the cross-sectional view of the electronic device 100, the first insulating layer IL1 may at least contact the side surface of the conductive member 150 and the side surface of the conductive layer 147. In the present embodiment, the first insulating layer IL1 may include an organic material or an inorganic material. The organic material may be an underfill or other suitable polymer material for fixing the electronic component 160, but is not limited thereto. The inorganic material may include silicon oxide, silicon nitride or other suitable materials for fixing the electronic component 160 or adjusting the warpage of the electronic device, but is not limited thereto.

[0101] The second insulating layer IL2 is disposed on the first surface 110a of the substrate 110, and the second insulating layer IL2 surrounds the electronic component 160 and the first circuit structure 140. In the cross-sectional view of the electronic device 100, the second insulating layer IL2 may at least contact the side surface 160c of the electronic component 160 and the side surface 140a of the first circuit structure 140. The second insulating layer IL2 may contact the buffer layer 130. In the present embodiment, the second insulating layer IL2 may include an organic material or an inorganic material. The organic material may be a molding layer. The inorganic material may include silicon oxide, silicon nitride or other suitable materials for protecting the electronic component 160 or isolating moisture, but is not limited thereto.

[0102] In the present embodiment, the manufacturing method of the electronic device 100 may include but is not limited to the following steps and the order of the steps: providing a substrate 110, wherein the substrate 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a; drilling the substrate 110 by means of, for example, laser modification or etching, to form a through hole 120, wherein the through hole 120 passes through the substrate 110, the through hole 120 has a first through hole 121 and a second through hole 122, and the width D2 of the second through hole 122 is greater than the width D1 of the first through hole 121; forming a buffer layer 130 so that the buffer layer 130 covers the first surface 110a, the second surface 110b, the inner wall 1211 of the first through hole 121, and the inner wall 1221 of the second through hole 122; depositing a seed layer (not shown) on the inner wall (1211, 1221) of the through hole 120; , forming a conductive material CM in the through hole 120 by means such as electroplating or chemical plating; forming a first circuit structure 140 and a second circuit structure 170 on the first surface 110a and under the second surface 110b respectively by processes such as yellow light, etching, surface treatment, laser, electroplating, etc.; bonding the electronic component 160 to the first circuit structure 140 through the conductive member 150; forming a first pad 180 under the second circuit structure 170 so that the first pad 180 is electrically connected to the electronic component 160 through the second circuit structure 170, the through hole 120, the first circuit structure 140 and the conductive member 150; forming a first insulating layer IL1 between the electronic component 160 and the first circuit structure 140; and forming a second insulating layer IL2 so that the second insulating layer IL2 surrounds the electronic component 160 and the first circuit structure 140.

[0103] In this embodiment, the manufacturing method of the electronic device 100 can be applied to a wafer-level package (WLP) process or a panel-level package (PLP) process, and can be a chip-first or chip-last redistribution layer first (RDL first) manufacturing method.

[0104] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiments, and the following embodiments will not be repeated.

[0105] Figure 2 This is a cross-sectional diagram of an electronic device according to a second embodiment of the present disclosure. Figure 2 and Figure 1BThe electronic device 100a of this embodiment and Figure 1B The electronic device 100a of the present embodiment is similar to the electronic device 100 of the present embodiment, but the difference between the two is that: in the electronic device 100a of the present embodiment, the conductive layer 177a of the second circuit structure 170 is buried in the dielectric layer 175. In addition, the buffer layer 130 may at least cover the side surface 110c of the substrate 110. In this way, by covering at least a portion of the side surface 110c of the substrate 110 with the buffer layer 130, the risk of the substrate 110 breaking during the singulation or cutting process can be reduced.

[0106] Specifically, please refer to Figure 2 In the cross-sectional view of the electronic device 100a, the dielectric layer 175 may surround the conductive layer 177a, the dielectric layer 175 may at least contact the side surface 177a1 of the conductive layer 177a, and the surface 177a2 of the conductive layer 177a facing away from the substrate 110 is exposed outside the dielectric layer 175.

[0107] Figure 3 This is a cross-sectional diagram of an electronic device according to a third embodiment of the present disclosure. Figure 3 and Figure 1B The electronic device 100b of this embodiment and Figure 1B The electronic device 100b of the present embodiment is similar to the electronic device 100 of the present embodiment, but the difference between the two is that the electronic device 100b of the present embodiment further includes a heat sink HS, and the through hole 120 further includes a third through hole 123 and a fourth through hole 124.

[0108] Specifically, please refer to Figure 3 , the third through hole 123 and the fourth through hole 124 correspond to the central area 101. There is a distance L3 between the third through hole 123 and the closest second through hole 122, and there is a distance L4 between the fourth through hole 124 and the closest second through hole 122. Wherein, the distance L3 is, for example, the minimum distance measured along the direction X between the third through hole 123 and the closest second through hole 122, and the distance L4 is, for example, the minimum distance measured along the direction X between the fourth through hole 124 and the closest second through hole 122. In this embodiment, the ratio of the distance L3 to the distance L4 can be greater than or equal to 0.8 and less than or equal to 1.2 (that is, 0.8≤L3 / L4≤1.2), so that the third through hole 123 and the fourth through hole 124 adjacent to each other in the direction X can be substantially symmetrically arranged, and the stress on the left and right sides of the substrate 110 can be balanced to reduce the problem of warping, but it is not limited thereto.

[0109] The third through hole 123 and the fourth through hole 124 have a width D3 and a depth L. The width D3 is, for example, the maximum width of the third through hole 123 (or the fourth through hole 124) measured along the direction X, and the depth L is, for example, the maximum depth of the third through hole 123 (or the fourth through hole 124) measured along the direction Z. In the present embodiment, the width D3 of the third through hole 123 (or the fourth through hole 124) may be greater than the width D1 of the first through hole 121 for heat dissipation or for transmitting a larger voltage signal, but is not limited thereto. In the present embodiment, the ratio of the width D3 of the third through hole 123 (or the fourth through hole 124) to the depth L may be 0.01 to 0.5 (i.e., D3 / L=0.01-0.5), but is not limited thereto.

[0110] The heat sink HS is disposed on the back side 160b of the electronic component 160 to conduct heat generated by the electronic component 160 to the outside. According to some embodiments, the side of the heat sink HS away from the electronic component 160 may have a fin or groove design to improve the heat dissipation effect, but is not limited thereto.

[0111] Figure 4 This is a cross-sectional diagram of an electronic device according to a fourth embodiment of the present disclosure. Figure 4 and Figure 1B The electronic device 100c of this embodiment and Figure 1B The electronic device 100c of the present embodiment is similar to the electronic device 100 of the present embodiment, but the difference between the two is that the electronic device 100c of the present embodiment further includes a circuit board PCB, the first circuit structure 140 further includes an anti-warping layer 148, and the second circuit structure 170 further includes an anti-warping layer 178.

[0112] Specifically, please refer to Figure 4 In the first circuit structure 140, the anti-warping layer 148 is disposed on the dielectric layer 142, and the anti-warping layer 148 is disposed at the junction between the dielectric layer 145 and the dielectric layer 142. Part of the anti-warping layer 148 may also be disposed between two adjacent conductive layers 144. In this embodiment, the material and the warping tendency (e.g., downward warping) of the anti-warping layer 148 may be different from the material and the warping tendency (e.g., upward warping) of the dielectric layer in the first circuit structure 140 to improve the warping problem.

[0113] In the second circuit structure 170, the anti-warping layer 178 is disposed under the dielectric layer 172, and the anti-warping layer 178 is disposed at the junction between the dielectric layer 175 and the dielectric layer 172. Part of the anti-warping layer 178 may also be disposed between two adjacent conductive layers 174. In this embodiment, the material and the warping tendency (e.g., upward warping) of the anti-warping layer 178 may be different from the material and the warping tendency (e.g., downward warping) of the dielectric layer in the second circuit structure 170 to improve the warping problem.

[0114] In the present embodiment, the material of the anti-warping layer 148 may be the same as or different from the material of the anti-warping layer 178 , but is not limited thereto.

[0115] The PCB is disposed under the first pad 180 and can be electrically connected to the first pad 180. In this embodiment, the electronic component 160 can be electrically connected to the PCB through the conductive element 150, the first circuit structure 140, the through hole 120, the second circuit structure 170 and the first pad 180.

[0116] Figure 5 This is a cross-sectional diagram of an electronic device according to a fifth embodiment of the present disclosure. Figure 5 and Figure 1B The electronic device 100d of this embodiment and Figure 1B The electronic device 100d of the present embodiment is similar to the electronic device 100 of the present embodiment, but the difference between the two is that the electronic device 100d of the present embodiment further includes a component integration layer 190, and the buffer layer 130 can completely cover the inner wall 1211 of the first through hole 121 and the inner wall 1221 of the second through hole 122.

[0117] Specifically, please refer to Figure 5 The first circuit structure 140d is disposed on the component integration layer 190, and the first circuit structure 140d includes a conductive layer 144, a dielectric layer 145, a through hole 146, and a conductive layer 147. The conductive layer 144 is disposed on the component integration layer 190, the dielectric layer 145 is disposed on the conductive layer 144, the conductive layer 147 is disposed on the dielectric layer 145, and the through hole 146 penetrates the dielectric layer 145 and electrically connects the conductive layer 147 and the conductive layer 144.

[0118] The component integration layer 190 is disposed between the first circuit structure 140d and the substrate 110, and the component integration layer 190 includes a conductive layer 191, a dielectric layer 192, a through hole 193, and a component 194. The conductive layer 191 is disposed on the buffer layer 130, the dielectric layer 192 is disposed on the conductive layer 191, the through hole 193 penetrates the dielectric layer 192 and electrically connects the conductive layer 144 and the conductive layer 191, and the component 194 is disposed in the dielectric layer 145. The component 194 can overlap with the electronic component 160 in the direction Z, thereby shortening the signal transmission path between the two, thereby reducing signal loss or achieving energy saving effects.

[0119] In this embodiment, the dissipation factor (Df) of the dielectric layer 192 in the component integration layer 190 may be different from the dissipation factor of the dielectric layer 145 in the first circuit structure 140d, and the dissipation factor of the dielectric layer 192 may be smaller than the dissipation factor of the dielectric layer 145 to form a better capacitance, but is not limited thereto.

[0120] In this embodiment, the component 194 may be an active component, a passive component or other suitable component. In some embodiments, the passive component may also be a capacitor, a resistor or an inductor. In some embodiments, the active component may also be a transistor or a thin film transistor.

[0121] Figure 6 This is a cross-sectional diagram of an electronic device according to a sixth embodiment of the present disclosure. Figure 6 and Figure 1B The electronic device 100e of this embodiment and Figure 1B The electronic device 100e of the present embodiment is similar to the electronic device 100, but the difference between the two is that the electronic device 100e of the present embodiment further includes an electronic component 200, an optical fiber 250, an electronic component 300, a solder resist layer SR1 and a solder resist layer SR2, and the substrate 110 includes a groove 111 recessed in the first surface 110a.

[0122] Specifically, please refer to Figure 6 The first circuit structure 140e further includes a dielectric layer 1421 and a through hole 1431. The dielectric layer 1421 is disposed between the dielectric layer 142 and the first surface 110a of the substrate 110. The through hole 1431 is filled with a conductive material CM, and the through hole 1431 penetrates the dielectric layer 1421 and electrically connects the conductive layer 141 and the first through hole 121.

[0123] The second circuit structure 170e further includes a dielectric layer 1721 and a through hole 1731. The dielectric layer 1721 is disposed between the second surface 110b of the substrate 110 and the dielectric layer 172. The through hole 1731 is filled with a conductive material CM and penetrates the dielectric layer 1721 to electrically connect the first through hole 121 and the conductive layer 171.

[0124] The solder resist layer SR1 and the solder resist layer SR2 can cover and surround the first circuit structure 140e and the second circuit structure 170e, respectively. The solder resist layer SR1 and the solder resist layer SR2 can be used to protect the first circuit structure 140e and the second circuit structure 170e, respectively, to block external water and oxygen, or to avoid affecting the first circuit structure 140e and the second circuit structure 170e when manufacturing the conductive member 150.

[0125] The electronic component 200 is disposed on the first circuit structure 140e and the conductive member 150, and the electronic component 200 corresponds to the central area 101. The pad 210 of the electronic component 200 can be electrically connected to the conductive layer 147 of the first circuit structure 140e through the conductive member 150. In addition, the electronic component 200 can also be electrically connected to the optical fiber 250. In this embodiment, the electronic component 200 can be a silicon photonic chip (photonic IC, PIC), but is not limited thereto.

[0126] The groove 111 corresponds to the central area 101, and the groove 111 has a bottom surface 111a and an inner wall 111b. The buffer layer 130 can cover a portion of the inner wall 111b of the groove 111. The adhesive layer 350 is disposed on the bottom surface 111a of the groove 111. The bottom glue 360 ​​is filled in the groove 111. According to some embodiments, the angle θ between the inner wall 111b of the groove 111 and the direction Z can be between 20 degrees and 60 degrees, thereby making it easier to place the electronic component 300, but it is not limited thereto.

[0127] The electronic component 300 is embedded and fixed in the groove 111 through the adhesive layer 350, and the electronic component 300 is arranged corresponding to the central area 101. The pad 310 of the electronic component 300 can be electrically connected to the through hole 1431 of the first circuit structure 140e. In this embodiment, the electronic component 300 can be a connector for processing signals between the electronic component 160 and the electronic component 200, but is not limited thereto. According to some embodiments, the adhesive layer 350 can contact the side 300a of the electronic component 300 to fix the electronic component 300, but is not limited thereto.

[0128] In summary, in the electronic device of the disclosed embodiment, since the width of the second through hole corresponding to the peripheral area can be greater than the width of the first through hole corresponding to the central area, the copper ratio of the through hole in the peripheral area can be increased to release stress or improve the warping problem. Since the buffer layer with buffering properties covers the first surface of the substrate, the second surface of the substrate, the inner wall of the first through hole and the inner wall of the second through hole, the substrate can be protected to reduce damage to the substrate caused by stress generated by subsequent processes. Since the warping trend of the second circuit structure can be different from the warping trend of the first circuit structure, the warping problem can be improved. Since the warping trend of the anti-warping layer in the circuit structure can be different from the warping trend of the dielectric layer in the circuit structure, the warping problem can be improved. Since the components in the component integration layer can overlap with the electronic components, the signal transmission path between the two can be shortened, thereby reducing signal loss or achieving energy saving effects.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that: It has a central area and a peripheral area surrounding the central area, and includes: A substrate having a first surface and a second surface opposite to the first surface; A through hole, which passes through the substrate and has a first through hole and a second through hole; a buffer layer, covering the first surface, the second surface, an inner wall of the first through hole, and an inner wall of the second through hole; A first circuit structure is disposed on the first surface; an electronic component, disposed on the first circuit structure and corresponding to the central area; and a first pad, disposed on the second surface and electrically connected to the electronic component through the through hole and the first circuit structure; The first through hole corresponds to the central area, the second through hole corresponds to the peripheral area, and the width of the second through hole is greater than that of the first through hole.

2. The electronic device according to claim 1, characterized in that: A ratio of a width of the second through hole to a width of the first through hole is 1.2 to 3.

3. The electronic device according to claim 1, characterized in that: Also includes: The second circuit structure is disposed on the second surface and located between the substrate and the first pad.

4. The electronic device according to claim 3, characterized in that: A distance between two adjacent conductive layers in the first circuit structure is smaller than a distance between two adjacent conductive layers in the second circuit structure.

5. The electronic device according to claim 3, characterized in that: The first circuit structure is electrically connected to the second circuit structure through the through hole.

6. The electronic device according to claim 1, characterized in that: Also includes: The first insulating layer is disposed between the electronic component and the first circuit structure.

7. The electronic device according to claim 1, characterized in that: Also includes: The second insulating layer surrounds the electronic component and the first circuit structure.

8. The electronic device according to claim 7, characterized in that: The second insulating layer contacts the buffer layer.

9. The electronic device according to claim 1, characterized in that: The first circuit structure includes an anti-warping layer and a dielectric layer, and a warping tendency of the anti-warping layer is different from a warping tendency of the dielectric layer.

10. The electronic device according to claim 1, characterized in that: Also includes: A component integration layer is disposed between the first circuit structure and the substrate, The component integration layer includes components, and the components overlap the electronic components.

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