Semiconductor device, chip, electronic equipment and preparation method of semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a chip, electronic equipment and a preparation method of the semiconductor device, relates to the technical field of semiconductor bonding, and is used for improving the electric connection effect between two semiconductor devices. The semiconductor device includes a semiconductor structure and an interconnect layer. The interconnection layer is located on one side of the semiconductor structure and comprises a plurality of bonding parts arranged at intervals, each bonding part comprises a bonding pad and a metal glass layer, the bonding pads are connected to the semiconductor structure, and the metal glass layers cover the sides, away from the semiconductor structure, of the bonding pads. The semiconductor device is used for a chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor bonding technology, and in particular to a semiconductor device, a chip, an electronic device, and a method for preparing a semiconductor device. Background Art

[0002] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, and the size of the pads set therein is getting smaller and smaller. In the related art, a hybrid bonding technology can be used to connect the pads of two semiconductor devices, so that the two semiconductor devices are electrically connected. However, in the related art, the bonding effect between the pads is not good, resulting in a poor electrical connection effect between the two semiconductor devices. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a semiconductor device, a chip, an electronic device and a method for manufacturing a semiconductor device, so as to improve the electrical connection effect between two semiconductor devices.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] In one aspect, a semiconductor device is provided. The semiconductor device includes: a semiconductor structure and an interconnection layer. The interconnection layer is located on one side of the semiconductor structure, and the interconnection layer includes a plurality of bonding portions arranged at intervals, and the bonding portions include a bonding pad and a metallic glass layer, wherein the bonding pad is connected to the semiconductor structure, and the metallic glass layer covers a side of the bonding pad away from the semiconductor structure.

[0006] In the above semiconductor device, the metallic glass layer can be electrically connected to the bonding pad, and the metallic glass layer can be electrically connected to the semiconductor structure through the bonding pad. The metallic glass layer of the semiconductor device can be hybrid bonded with the metallic glass layer of another semiconductor device, and the metallic glass layers of the two semiconductor devices can form a bonding connection portion, and the bonding connection portion can be electrically connected to the semiconductor structure through the bonding pad. At this time, the semiconductor structures of the two semiconductor devices can be electrically connected through the bonding pad and the bonding connection portion. In the bonding process of the metallic glass layer of the bonding portion in the two semiconductor devices, the metallic glass layers of the bonding portion in the two semiconductor devices are aligned with high precision, hybrid bonded, and then annealed. During the annealing process, when the temperature reaches the supercooled liquid phase region, the metallic glass layers of the two semiconductor devices can soften and form a liquid-like state, thereby producing an effect similar to liquid flow, thereby reducing the gap at the contact interface of the metallic glass layers of the two semiconductor devices, and then improving the contact effect of the metallic glass layers of the two semiconductor devices, thereby improving the bonding effect of the two semiconductor devices, and then improving the electrical connection quality of the two semiconductor devices, thereby improving the subsequent electrical testing and reliability testing of the chip. In addition, before the metal glass layers of the two semiconductor devices are bonded, an oxide layer may exist on the surface of the metal glass layer. The metal glass layer is an amorphous structure (i.e., no crystalline structure) at the microscopic level. Among them, the metal atoms in the metal glass layer do not occupy the lowest energy site, so the metal atoms are in a higher energy state in structure. In this case, the metal glass layer can activate the movement of its local metal atomic clusters through ultrasonic vibration at room temperature, and the movement of the atomic clusters can make the atomic clusters break through the oxide layer of the bonding interface of the metal glass layer. At this time, the metal glass layers in the two semiconductor devices can break through the surface oxide layer for bonding. Therefore, the bonding effect of the metal glass layers in the two semiconductor devices is better. In addition, because, at room temperature, the movement of the atomic clusters in the metal glass layer can break through the surface oxide layer, therefore, the metal glass layers in the two semiconductor devices can be bonded under room temperature conditions. In addition, after the metal glass layers of the two semiconductor devices are mixed and bonded, the movement of the metal atomic clusters will be more intense during the annealing process, which will be more conducive to the metal atomic clusters breaking through the oxide layer of the bonding interface of the metal glass layer, thereby improving the bonding effect of the metal glass layers in the two semiconductor devices.

[0007] In some embodiments, the interconnection layer also includes: a dielectric layer, the bonding portion is embedded in the dielectric layer, the dielectric layer exposes a first surface of the metallic glass layer, the first surface is a surface of the metallic glass layer facing away from the semiconductor structure; the dielectric layer includes a second surface facing away from the semiconductor structure; wherein the first surface is closer to the semiconductor structure than the second surface.

[0008] Among them, the first surface of the metallic glass layer can enclose an expansion space with the dielectric layer. During the bonding process of the metallic glass layer in the bonding part of the two semiconductor devices, the metallic glass layer of the two semiconductor devices can expand, and at this time, the volume of the metallic glass layer can increase. By making the first surface of the metallic glass layer and the dielectric layer enclose an expansion space, the metallic glass layer can expand into the expansion space, so as to avoid that after the expansion of the metallic glass layer, the portion protruding too much from the second surface of the dielectric layer causes a gap between the metallic glass layers of the two semiconductor devices after bonding. In an embodiment of the present application, by making the first surface closer to the semiconductor structure than the second surface, the phenomenon of the existence of a gap after the bonding of the two semiconductor devices due to the expansion of the metallic glass layer can be reduced.

[0009] In some embodiments, the distance between the first surface and the second surface in the first direction is greater than or equal to and less than or equal to The first direction is perpendicular to the first surface.

[0010] Wherein, by making the distance between the first surface and the second surface in the first direction greater than or equal to The metallic glass layer can have sufficient expansion space to avoid the metallic glass layer from protruding too much from the second surface after expansion due to lack of expansion space, resulting in a gap between the two semiconductor devices after the metallic glass layer is bonded, thereby affecting the bonding effect of the metallic glass layer in the two semiconductor devices. The phenomenon that a gap exists between two semiconductor devices after the metal glass layer is bonded can be reduced.

[0011] By making the distance between the first surface and the second surface in the first direction less than or equal to It can be avoided that the expansion space of the metallic glass layer is too large, resulting in the metallic glass layer being unable to fill the expansion space after expansion. If the expansion space is too large, a gap will exist between the metallic glass layers of the two semiconductor devices after expansion, thereby affecting the contact effect of the metallic glass layers of the two semiconductor devices. Therefore, by making the distance between the first surface and the second surface in the first direction less than or equal to The influence of the excessive expansion space on the bonding effect of the metallic glass layers of the two semiconductor devices can be reduced.

[0012] In some embodiments, the dielectric layer includes a first isolation layer, an intermediate layer, and a second isolation layer sequentially stacked on the semiconductor structure; the bonding pad is embedded in the first isolation layer, the intermediate layer, and the second isolation layer, and the metallic glass layer is embedded in the second isolation layer.

[0013] The second surface of the dielectric layer is the surface of the second isolation layer away from the semiconductor structure. In this way, the first surface of the metallic glass layer can be lower than or flush with the second surface of the dielectric layer.

[0014] In some embodiments, a ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is greater than or equal to 10.55 and less than or equal to 158.9.

[0015] Among them, the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is greater than or equal to 10.55, so that the thickness of the metallic glass layer can be avoided from being too large. If the thickness of the metallic glass layer is too large, it may cause the metallic glass layer to protrude too much from the second surface after expansion. At this time, after the metallic glass layers of the two semiconductor devices are bonded, there may be a gap between the two semiconductor devices. Therefore, by making the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer greater than or equal to 10.55, the phenomenon of the gap between the two semiconductor devices caused by the excessive thickness of the metallic glass layer can be reduced. In addition, the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is less than or equal to 158.9, so that the thickness of the metallic glass layer can be avoided from being too small. If the thickness of the metallic glass layer is too small, it may cause the metallic glass layers of the two semiconductor devices to have a gap between them after expansion, so that the bonding of the metallic glass layers of the two semiconductor devices is not sufficient. Therefore, by making the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer less than or equal to 158.9, the phenomenon of insufficient bonding of the metallic glass layers of two semiconductor devices due to too small thickness of the metallic glass layer can be reduced.

[0016] In some embodiments, the bonding pad includes a first portion and a second portion, one end of the first portion is connected to the semiconductor structure, the second portion is connected to the other end of the first portion, a cross-sectional area of ​​the first portion on a first reference plane is smaller than a cross-sectional area of ​​the second portion on a second reference plane, wherein the first reference plane and the second reference plane are both parallel to a surface of the metallic glass layer facing away from the semiconductor structure; wherein a ratio of a thickness of the first portion to a thickness of the metallic glass layer is greater than or equal to 5.55 and less than or equal to 75. A ratio of a thickness of the second portion to a thickness of the metallic glass layer is greater than or equal to 5 and less than or equal to 83.9.

[0017] Wherein, the ratio of the thickness of the first part to the thickness of the metal glass layer is greater than or equal to 5.55, so that the thickness of the metal glass layer can be avoided to be too large. If the thickness of the metal glass layer is too large, it may cause the metal glass layer to protrude too much from the second surface after expansion. At this time, after the metal glass layers of the two semiconductor devices are bonded, there is a gap between the two semiconductor devices. Therefore, by making the ratio of the thickness of the first part to the thickness of the metal glass layer greater than or equal to 5.55, the phenomenon of the gap between the two semiconductor devices caused by the excessive thickness of the metal glass layer can be reduced. In addition, the ratio of the thickness of the second part to the thickness of the metal glass layer is less than or equal to 75, so that the thickness of the metal glass layer can be avoided to be too small. If the thickness of the metal glass layer is too small, it may cause the metal glass layers of the two semiconductor devices to have a gap after expansion, thereby causing the metal glass layers of the two semiconductor devices to be insufficiently bonded. Therefore, by making the ratio of the thickness of the second part to the thickness of the metal glass layer less than or equal to 75, the phenomenon of the insufficient bonding of the metal glass layers of the two semiconductor devices caused by the excessively small thickness of the metal glass layer can be reduced.

[0018] In some embodiments, the thickness of the metallic glass layer is greater than or equal to and less than or equal to

[0019] The thickness of the metallic glass layer is greater than or equal to This can prevent the thickness of the metallic glass layer from being too small. If the thickness of the metallic glass layer is too small, a gap may exist between the metallic glass layers of the two semiconductor devices after the metallic glass layers of the two semiconductor devices expand, thereby causing the metallic glass layers of the two semiconductor devices to be insufficiently bonded. Therefore, by making the thickness of the metallic glass layer greater than or equal to The phenomenon that the metal glass layer of two semiconductor devices is not sufficiently bonded due to the metal glass layer being too thin can be reduced. In addition, the thickness of the metal glass layer is less than or equal to This can prevent the thickness of the metallic glass layer from being too large. If the thickness of the metallic glass layer is too large, the metallic glass layer may bulge out too much from the second surface after expansion, and in this case, a gap will exist between the two semiconductor devices after the metallic glass layers of the two semiconductor devices are bonded. Therefore, by making the thickness of the metallic glass layer less than or equal to The phenomenon of a gap between two semiconductor devices caused by the excessive thickness of the metallic glass layer can be reduced.

[0020] In some embodiments, the thickness of the bonding pad is greater than or equal to and less than or equal to

[0021] Wherein, the thickness of the bonding pad is greater than or equal to It can be avoided that the thickness of the bonding pad is too thin, which may cause the metallic glass layer on the surface of the bonding pad to be too thick. If the thickness of the metallic glass layer is too thick, it may cause the metallic glass layer to bulge out too much from the second surface after expansion. In this case, after the metallic glass layers of the two semiconductor devices are bonded, there may be a gap between the two semiconductor devices. Therefore, by making the thickness of the bonding pad greater than or equal to The gap between two semiconductor devices caused by the excessive thickness of the metallic glass layer can be reduced. It is possible to avoid the bonding pad being too thick, which would cause the metallic glass layer on the bonding pad surface to be too thin. If the metallic glass layer is too thin, a gap may exist between the metallic glass layers of the two semiconductor devices after the metallic glass layers of the two semiconductor devices expand, thereby causing the metallic glass layers of the two semiconductor devices to be insufficiently bonded. Therefore, by making the bonding pad thickness less than or equal to The phenomenon that the metal glass layers of two semiconductor devices are not sufficiently bonded due to the metal glass layer being too thin can be reduced.

[0022] In some embodiments, the material of the metallic glass layer includes CuZr.

[0023] Among them, after the bonding process of the metal glass layers of the two semiconductor devices, when the two semiconductor devices are annealed, when the annealing temperature reaches the crystallization temperature of CuZr, the Cu atoms and Zr atoms in CuZr can rearrange the atomic positions, specifically, the Cu atoms can crystallize and precipitate single crystal Cu. At this time, the bonding connection formed after the metal glass layers of the two semiconductor devices are bonded can include CuZr and single crystal Cu. Among them, the resistivity of single crystal Cu is less than the resistivity of CuZr, therefore, the material of the metal glass layer includes CuZr can reduce the resistivity of the bonding connection. In addition, single crystal Cu can also destroy the oxide layer on the bonding surface of the metal glass layer 342 of the two semiconductor devices 300, thereby improving the bonding effect of the metal glass layer 342 in the two semiconductor devices 300.

[0024] In another aspect, a chip is provided, comprising: two semiconductor devices provided in any one of the above embodiments, wherein the metallic glass layers of multiple bonding portions of the two semiconductor devices are bonded to form multiple bonding connection portions.

[0025] Among them, the above-mentioned chip is composed of two semiconductor devices provided in some of the above-mentioned embodiments, and therefore has the same beneficial effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here.

[0026] In some embodiments, in a semiconductor device, a bonding pad of a bonding portion has a recess on a surface facing away from a semiconductor structure of the semiconductor device, and a portion of the bonding connection portion is filled in the recess.

[0027] Among them, the surface of the bonding pad away from the semiconductor structure is a non-smooth surface with a depression thereon. During the bonding process of the metal glass layers of two semiconductor devices, the temperature of the metal glass layer will increase. When the temperature reaches the supercooled liquid phase, the metal glass layer will be in a liquid-like state. Therefore, the metal glass layer can have fluidity, and then the metal glass layer can be filled in the depression on the surface of the bonding pad away from the semiconductor structure, thereby increasing the connection effect between the metal glass layer (that is, the bonding connection part) and the bonding pad.

[0028] In some embodiments, the material of the bonding connection includes CuZr and single crystal Cu.

[0029] After the metal glass layer bonding process of the two semiconductor devices, when the two semiconductor devices are annealed, when the annealing temperature reaches the crystallization temperature of CuZr, the Cu atoms in CuZr can be crystallized to precipitate single crystal Cu. In other words, the bonding connection formed after the metal glass layers of the two semiconductor devices are bonded can include CuZr and single crystal Cu. The resistivity of single crystal Cu is less than that of CuZr, so the resistivity of the bonding connection can be reduced.

[0030] In another aspect, an electronic device is provided, which includes a circuit board and the chip provided by some of the above embodiments, wherein the chip is arranged on the circuit board.

[0031] Among them, the above-mentioned electronic device has the same structure and beneficial technical effects as the chips provided in some of the above-mentioned embodiments, which will not be repeated here.

[0032] In another aspect, a method for preparing a semiconductor device is provided, which comprises: forming a dielectric layer on a surface of a semiconductor structure; forming a plurality of contact holes on the dielectric layer; forming bonding pads in the contact holes; and forming a metallic glass layer in the contact holes, wherein the metallic glass layer overlaps and contacts the bonding pads.

[0033] Among them, the method for preparing the above-mentioned semiconductor device is used to prepare the semiconductor devices provided by some of the above embodiments, and therefore has the same beneficial effects as the semiconductor devices provided by some of the above embodiments, which will not be described in detail here.

[0034] In some embodiments, forming bonding pads in a plurality of contact holes includes: depositing a metal material, the metal material filling the contact holes; removing the metal material at the top of the contact holes to form a first recess, the metal material remaining in the contact holes is the bonding pad; the top of the contact hole is the area of ​​the contact hole away from one end of the semiconductor structure. Forming a metallic glass layer in the contact hole includes: forming a metallic glass layer in the first recess.

[0035] After the metal material at the top of the contact hole is removed, a first recess can be formed, thereby providing a space for accommodating the metallic glass layer. In addition, after the metal material at the top of the contact hole is removed, a bonding pad can be formed. At this time, the bonding pad can have a flat surface on the side away from the semiconductor structure, thereby providing a flat surface for the formation of the metallic glass layer, which is beneficial to improving the thickness uniformity of the metallic glass layer.

[0036] In some embodiments, forming a metallic glass layer in the first recess includes: depositing a metallic glass material, the metallic glass material filling the first recess and covering the dielectric layer; removing the metallic glass material covering the dielectric layer and retaining the metallic glass material in the first recess to form the metallic glass layer.

[0037] The first surface of the metallic glass layer may be flush with the second surface of the dielectric layer.

[0038] In some embodiments, a metallic glass layer is formed in the first recess, including: depositing a metallic glass material, the metallic glass material filling the first recess and covering the dielectric layer; removing the metallic glass material covering the dielectric layer and the metallic glass material located at the top of the first recess, and the metallic glass material retained in the first recess is the metallic glass layer, wherein the top of the first recess is the region of the first recess facing away from one end of the semiconductor structure.

[0039] Among them, the first surface of the metallic glass layer is closer to the semiconductor structure than the second surface of the dielectric layer. At this time, the first surface of the metallic glass layer can enclose an expansion space with the dielectric layer. During the bonding process of the metallic glass layer of the bonding part in the two semiconductor devices, the metallic glass layers of the two semiconductor devices can expand, and at this time, the volume of the metallic glass layer can increase. By making the first surface of the metallic glass layer and the dielectric layer enclose an expansion space, the metallic glass layer can expand into the expansion space, so as to avoid that the metallic glass layer protrudes too much from the second surface of the dielectric layer after expansion, and at this time, after the metallic glass layers of the two semiconductor devices are bonded, there may be a gap between the two semiconductor devices. Therefore, by making the first surface closer to the semiconductor structure than the second surface, the phenomenon of the existence of a gap after the bonding of the two semiconductor devices due to the expansion of the metallic glass layer can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0041] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application;

[0042] Figure 2 It is a structural diagram of a chip in the related art;

[0043] Figure 3 A structural diagram of a chip provided in an embodiment of the present application;

[0044] Figure 4 A structural diagram of a semiconductor device provided in an embodiment of the present application;

[0045] Figure 5 Another structural diagram of a semiconductor device provided in an embodiment of the present application;

[0046] Figure 6 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0047] Figures 7 to 14 A step diagram of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0048] Fig.15 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0049] Fig.16 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0050] Fig.17 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0051] Fig.18 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0052] Figures 19 to 24 This is another step diagram of the method for preparing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "compris ing", are to be interpreted as open, inclusive, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0056] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0057] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0058] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0059] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0060] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application.

[0061] See also Figure 1 , the embodiment of the present application provides an electronic device 1000, which may include any one of CMOS (complementary metal-oxide-semiconductor) image sensors, NAND memory, high bandwidth memory, mobile phones, tablet computers (pads), televisions, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and other electronic products. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device 1000.

[0062] like Figure 1As shown, the electronic device 1000 may include a chip packaging structure 2000 and a circuit board 3000 , and the chip packaging structure 2000 is electrically connected to the circuit board 3000 .

[0063] The chip package structure 2000 may include a chip 100 and a package substrate 200. The chip 100 may be packaged in the package substrate 200. In this case, the chip 100 may be disposed on a circuit board 3000 through the package substrate 200. The chip 100 may be a 3D IC (3-dimension integrated circuits).

[0064] Figure 2 FIG. 1 is a structural diagram of a chip 100 in the related art.

[0065] See also Figure 2 In some examples, the chip 100 may include two semiconductor devices 300. The semiconductor device 300 may include a semiconductor structure 310 and a connection layer 320, and the connection layer 320 is disposed on one side of the semiconductor structure 310. The connection layer 320 may include a plurality of pads 321 and an intermediate layer 322, wherein the plurality of pads 321 may be embedded in the intermediate layer 322, and the plurality of pads 321 may also be electrically connected to the semiconductor structure 310.

[0066] The plurality of pads 321 of one semiconductor device 300 may be fixedly connected and electrically connected to the plurality of pads 321 of another semiconductor device 300 , so that the two semiconductor devices 300 are fixedly connected and electrically connected.

[0067] Among them, the semiconductor structure 310 of the chip 100 may include a plurality of transistors. With the continuous development of semiconductor technology, the size of the transistors is gradually reduced, and the size of the pad 321 is gradually reduced accordingly. Accordingly, in the related art, Cu (copper) is used as the material of the pad 321, and the pads 321 of the two semiconductor devices 300 are hybrid-bonded (hybrid-bonding, HB), so that the two semiconductor devices 300 are electrically interconnected through the pad 321. Among them, the area of ​​the pad 321 required by the hybrid bonding technology is relatively small, so that the connection of the pad 321 of a smaller size can be achieved, thereby improving the interconnection bandwidth between the two semiconductor devices 300.

[0068] In the process of connecting the Cu pads 321, the two semiconductor devices 300 are first aligned with high precision and initially contacted to achieve hybrid bonding. Then annealing is performed. During the annealing process, the Cu pads 321 in the two semiconductor devices 300 expand due to heat and squeeze each other, thereby increasing the contact area of ​​the Cu pads 321 in the two semiconductor devices 300, and even allowing the Cu in the Cu pads 321 in the two semiconductor devices 300 to diffuse mutually, thereby enabling the Cu pads 321 in the two semiconductor devices 300 to achieve good ohmic contact.

[0069] The bonding result of the Cu pad 321 is affected by many factors, thereby affecting the subsequent electrical test and reliability test of the chip 100. For example, the factors affecting the bonding result of the Cu pad 321 include: the surface roughness of the Cu pad, the surface oxide layer, and the proportion of nano-twin copper and small-grain copper in the Cu pad 321.

[0070] In the related art, the following three methods can be used to achieve the bonding effect of the Cu pad 321 .

[0071] Method 1: Before bonding the Cu pads 321, use plasma to pre-treat the Cu pads 321, so that the Cu in the Cu pads 321 is in an "excited state", so that it is easier to combine the Cu pads 321 in the two semiconductor devices 300. In method 1, a high vacuum plasma bombardment device is required, but the high vacuum plasma bombardment device is relatively expensive, so the cost of method 1 is relatively high.

[0072] Method 2: Before the Cu pad 321 is bonded, the bonding surface of the Cu pad 321 is cleaned with an acid solution to remove the oxide layer on the bonding surface of the Cu pad 321 and improve the interface energy of the Cu pad 321. It should be noted that the bonding surface of the Cu pad 321 refers to the surface of the Cu pad 321 that is away from the semiconductor structure 310. However, in method 2, after the bonding surface of the Cu pad 321 is pickled, some gaps will be introduced on the bonding surface of the Cu pad 321, thereby affecting the contact effect of the two Cu pads 321, thereby affecting the bonding effect of the Cu pad 321.

[0073] Method three, adjust the conditions of ECP to increase the proportion of nano-twin copper and small-grain copper. It should be noted that the Cu pad 321 can be formed by an ECP (electro-chemical-deposition) process. The proportion of nano-twin copper crystal orientation is approximately 40%, and the diffusion coefficient of nano-twin copper is relatively high. Therefore, the higher the proportion of nano-twin copper, the better the bonding effect of the two Cu pads 321. However, nano-twin copper usually appears at the edge of the Cu pad 321, and the proportion of nano-twin copper is usually less than 40% of the area of ​​the bonding surface of the Cu pad 321. Therefore, the proportion of nano-twin copper is low, and the bonding effect of the Cu pads 321 of the two semiconductor devices 300 is poor. The challenges faced by adjusting the conditions of ECP to achieve a larger area of ​​nano-twin copper on the bonding surface of a smaller Cu pad 321 are relatively large.

[0074] In summary, when the above-mentioned methods 1, 2 and 3 are applied to the hybrid bonding of the Cu pad 321 , the bonding effect of the Cu pad 321 is poor, thereby resulting in poor results of the electrical test and reliability test of the chip 100 .

[0075] Based on this, an embodiment of the present application provides a chip.

[0076] Figure 3 A structural diagram of a chip 100 provided in an embodiment of the present application.

[0077] See also Figure 3 , the chip 100 may include two semiconductor devices 300. The semiconductor device 300 includes: a semiconductor structure 310 and an interconnection layer 330, wherein the interconnection layer 330 is located on one side of the semiconductor structure 310, and the interconnection layer 330 includes a plurality of bonding portions 340 arranged at intervals, wherein the bonding portion 340 includes a bonding pad 341 and a metallic glass layer 342, wherein the bonding pad 341 is connected to the semiconductor structure 310, and the metallic glass layer 342 covers the side of the bonding pad 341 away from the semiconductor structure 310. The metallic glass layers 342 of the plurality of bonding portions 340 of the two semiconductor devices 300 are bonded to form a plurality of bonding connection portions 400.

[0078] Among them, Figure 3 In the figure, the structure in the dotted frame indicated by the reference numeral 400 is the bonding connection portion 400 , wherein the dotted frame indicated by the reference numeral 400 is only for illustrating the position of the bonding connection portion 400 , and does not represent the actual boundary of the bonding connection portion 400 .

[0079] In a semiconductor device 300, a semiconductor structure 310 and an interconnection layer 330 are stacked along a first direction F1. Figure 3As shown, for the semiconductor device 300 located at the bottom, the direction indicated by the arrow F1 is the first direction F1. The first direction F1 may be perpendicular to the interconnect layer 330. For another semiconductor device 300, that is, the semiconductor device 300 located at the top, the first direction corresponding to it is opposite to the first direction F1 corresponding to the semiconductor device 300 at the bottom.

[0080] In some examples, the semiconductor structure 310 may include a functional structure 311 , a spacer layer 312 , and a routing layer 313 .

[0081] The functional structure 311 may include a functional device, wherein the functional device is used to implement the function of the semiconductor device 300. In the chip 100, the functions of the two semiconductor devices 300 may be different.

[0082] For example, when chip 100 is a NAND memory, the functional device of functional structure 311 in one semiconductor device 300 may be a storage cell string, wherein the storage cell string may implement a storage function, while the functional device of functional structure 311 in another semiconductor device 300 may be a logic circuit or a storage circuit.

[0083] The spacer layer 312 may be made of an insulating material. For example, the material of the spacer layer 312 may include an oxide, such as SiO2 (silicon dioxide). In addition, the material of the spacer layer 312 may also include SiOCN (silicon oxycarbon nitride).

[0084] The material of the wiring layer 313 may include a conductive material, for example, the conductive material may include a metal material. The wiring layer 313 may be electrically connected to the functional device of the functional structure 311. Figure 3 The electrical connection structure between the routing layer 313 and the functional devices is not shown.

[0085] The routing layer 313 may include a plurality of metal routing lines.

[0086] In some examples, the semiconductor structure 310 may further include a substrate (not shown in the figure), wherein the substrate may be disposed on a side of the functional structure 311 facing away from the wiring layer 313 .

[0087] For example, the substrate can be made of silicon or other semiconductor materials. For example, the substrate includes a combination of one or more of the following materials: silicon, silicon carbide, and gallium nitride. Alternatively or additionally, the substrate can include other elemental semiconductor materials such as germanium. In some examples, the substrate is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some examples, the substrate is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0088] The multiple bonding parts 340 of the interconnection layer 330 are arranged at intervals so that the multiple bonding parts 340 are insulated from each other. Among them, the bonding pad 341 of the bonding part 340 can be made of a metal material. For example, the material of the bonding pad 341 can include at least one of gold, silver, copper, aluminum, titanium, molybdenum, tungsten, nickel and chromium. Among them, the material of the bonding pad 341 can be adjusted as required, and in the embodiment of the present application, the material of the bonding pad 341 is not limited.

[0089] For example, the bonding pad 341 may be electrically connected to a metal trace in the trace layer 313 . One metal trace may be electrically connected to at least one bonding pad 341 .

[0090] Figure 4 A structural diagram of a semiconductor device 300 provided in an embodiment of the present application.

[0091] See also Figure 4 , the metallic glass layer 342 has conductivity.

[0092] The metallic glass layer 342 may be located on a side of the bonding pad 341 away from the semiconductor structure 310 , and the metallic glass layer 342 may contact the bonding pad 341 , so that the metallic glass layer 342 may be electrically connected to the bonding pad 341 , and the metallic glass layer 342 may be electrically connected to the semiconductor structure through the bonding pad 341 .

[0093] In the reference Figure 4 At the same time, combined with Figure 3 After the metal glass layers 342 of the two semiconductor devices 300 are bonded, the metal glass layers 342 of the two semiconductor devices 300 can be bonded to form a bonding connection 400. The number of bonding parts 340 included in the two semiconductor devices 300 can be the same. For example, each semiconductor device 300 can include N1 bonding parts 340. The metal glass layers 342 of the N1 bonding parts 340 in one semiconductor device 300 can be bonded one-to-one with the metal glass layers 342 of the N1 bonding parts 340 in another semiconductor device 300, so as to form N1 bonding connections 400. N1 is a positive integer greater than or equal to 1.

[0094] The semiconductor structure 310 in one semiconductor device 300 can be electrically connected to the bonding connection part 400 through the bonding pad 341 of the semiconductor device 300, and the bonding connection part 400 can be electrically connected to the semiconductor structure 310 of another semiconductor device 300 through the bonding pad 341 of another semiconductor device 300, so that the semiconductor structures 310 in the two semiconductor devices 300 can be electrically connected to exchange information.

[0095] The metallic glass layer 342 has liquid-like properties at high temperatures. Specifically, when the metallic glass layer 342 is between the glass transition temperature and the crystallization temperature, the Young's modulus of the metallic glass layer 342 decreases, and the hardness decreases, so that the metallic glass layer 342 softens. At this time, the properties of the metallic glass layer 342 are similar to those of a liquid. The temperature range between the glass transition temperature and the crystallization temperature is called the supercooled liquid phase region, and at this time, the metallic glass layer 342 does not reach the melting point because it is not melted.

[0096] In the bonding process of the metal glass layer 342 of the bonding part 340 of the two semiconductor devices 300, the metal glass layer 342 of the bonding part 340 of the two semiconductor devices 300 is aligned with high precision, hybrid bonding is performed, and then annealing is performed. During the annealing process, when the temperature reaches the supercooled liquid phase region, the metal glass layer 342 of the two semiconductor devices 300 can soften and form a liquid-like state, thereby generating an effect similar to liquid flow, thereby reducing the gap at the contact interface of the metal glass layer 342 of the two semiconductor devices 300, and further improving the contact effect of the metal glass layer 342 of the two semiconductor devices 300, thereby improving the bonding effect of the two semiconductor devices 300, and further improving the electrical connection quality of the two semiconductor devices 300, thereby improving the subsequent electrical test and reliability test of the chip 100.

[0097] In addition, before the metal glass layers 342 of the two semiconductor devices 300 are bonded, an oxide layer may exist on the surface of the metal glass layer 342. The metal glass layer 342 is an amorphous structure (i.e., a non-crystalline structure) at a microscopic level. Among them, the metal atoms in the metal glass layer 342 do not occupy the lowest energy site, so the metal atoms are in a higher energy state in the structure. In this case, the metal glass layer 342 can activate the movement of its local metal atomic clusters through ultrasonic vibration at room temperature, and the movement of the atomic clusters can make the atomic clusters break through the oxide layer of the bonding interface of the metal glass layer 342. At this time, the metal glass layer 342 in the two semiconductor devices 300 can break through the surface oxide layer for bonding, so the bonding effect of the metal glass layer 342 in the two semiconductor devices 300 is better. In addition, because, at room temperature, the movement of the atomic clusters in the metal glass layer 342 can break through the surface oxide layer, therefore, the metal glass layer 342 in the two semiconductor devices 300 can be bonded under room temperature conditions.

[0098] In addition, after the metal glass layers 342 of the two semiconductor devices 300 are mixed and bonded, during the annealing process, the movement of the metal atomic clusters will be more intense, which is more conducive to the metal atomic clusters breaking through the oxide layer of the bonding interface of the metal glass layer 342, thereby improving the bonding effect of the metal glass layer 342 in the two semiconductor devices 300.

[0099] In some examples, the annealing temperature may be greater than or equal to 250° C. and less than or equal to 450° C. In this case, the annealing temperature is relatively low, but the metallic glass layers 342 of the two semiconductor devices 300 may achieve a better bonding effect.

[0100] Illustratively, the annealing temperature may be approximately 300°C.

[0101] Next, a semiconductor device 300 is introduced.

[0102] Please refer to the basic Figure 4 In this embodiment, the interconnection layer 330 further includes a dielectric layer 350 . The bonding portion 340 is embedded in the dielectric layer 350 . At this time, the bonding pad 341 and the metallic glass layer 342 of the bonding portion 340 are both embedded in the dielectric layer 350 .

[0103] The projection of the bonding pad 341 in the second direction F2 covers part of the dielectric layer 350, and the projection of the metallic glass layer 342 in the second direction F2 covers part of the dielectric layer 350. The second direction F2 is parallel to the surface of the dielectric layer 350 away from the semiconductor structure 310. Figure 4 As shown, the direction indicated by arrow F2 is the second direction F2. It should be noted that there are multiple directions parallel to the surface of the dielectric layer 350 away from the semiconductor structure 310, and any direction parallel to the surface of the dielectric layer 350 away from the semiconductor structure 310 is the second direction F2.

[0104] The dielectric layer 350 exposes the first surface 3421 of the metallic glass layer 342 , where the first surface 3421 is the surface of the metallic glass layer 342 facing away from the semiconductor structure 310 . The dielectric layer 350 does not cover the first surface 3421 of the metallic glass layer 342 .

[0105] The dielectric layer 350 includes a second surface 3501 facing away from the semiconductor structure 310 .

[0106] In some examples, first surface 3421 of metallic glass layer 342 may be located on the same surface as second surface 3501 of semiconductor structure 310 .

[0107] Figure 5 Another structural diagram of a semiconductor device 300 provided in an embodiment of the present application.

[0108] See also Figure 5 In some other examples, the first surface 3421 is closer to the semiconductor structure 310 than the second surface 3501 .

[0109] The distance between the first surface 3421 and the semiconductor structure 310 in the first direction F1 is a first distance H1, and the distance between the second surface 3501 and the semiconductor structure 310 in the first direction F1 is a second distance H2. The first distance H1 is smaller than the second distance H2.

[0110] In this example, the metallic glass layer 342 is sunken into the dielectric layer 350, and at this time, the first surface 3421 of the metallic glass layer 342 can enclose an expansion space with the dielectric layer 350. During the bonding process of the metallic glass layer 342 of the bonding portion 340 in the two semiconductor devices 300, the metallic glass layer 342 of the two semiconductor devices 300 can expand, and at this time, the volume of the metallic glass layer 342 can increase. By making the first surface 3421 of the metallic glass layer 342 and the dielectric layer 350 enclose an expansion space, the metallic glass layer 342 can expand into the expansion space, so as to avoid that after the metallic glass layer 342 expands, the portion protruding too much from the second surface 3501 of the dielectric layer 350 causes a gap between the metallic glass layers 342 of the two semiconductor devices 300 after bonding. In the embodiment of the present application, by making the first surface 3421 closer to the semiconductor structure 310 than the second surface 3501, the phenomenon of a gap after the bonding of the two semiconductor devices 300 caused by the expansion of the metallic glass layer 342 can be reduced.

[0111] In some embodiments, the distance between the first surface 3421 and the second surface 3501 in the first direction F1 is greater than or equal to and less than or equal to The first direction F1 is perpendicular to the first surface 3421. In other words, the depth of the expansion space in the first direction F1 is greater than or equal to and less than or equal to

[0112] The greater the distance between the first surface 3421 and the second surface 3501 in the first direction F1, the greater the volume of the expansion space; conversely, the smaller the distance between the first surface 3421 and the second surface 3501 in the first direction F1, the smaller the volume of the expansion space.

[0113] In the embodiment of the present application, the distance between the first surface 3421 and the second surface 3501 in the first direction F1 is greater than or equal to The metallic glass layer 342 can have sufficient expansion space to avoid the metallic glass layer 342 from protruding too much from the second surface 3501 after expansion due to lack of expansion space, resulting in a gap between the two semiconductor devices 300 after the metallic glass layer 342 is bonded, thereby affecting the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300. Therefore, by making the distance between the first surface 3421 and the second surface 3501 in the first direction F1 greater than or equal to The phenomenon that a gap exists between two semiconductor devices 300 after the metallic glass layer 342 is bonded can be reduced.

[0114] By making the distance between the first surface 3421 and the second surface 3501 in the first direction F1 less than or equal to It can be avoided that the expansion space of the metallic glass layer 342 is too large, resulting in the metallic glass layer 342 being unable to fill the expansion space after expansion. If the expansion space is too large, a gap will exist between the metallic glass layers 342 of the two semiconductor devices 300 after expansion, thereby affecting the contact effect of the metallic glass layers 342 of the two semiconductor devices 300. Therefore, by making the distance between the first surface 3421 and the second surface 3501 in the first direction F1 less than or equal to The influence of the excessive expansion space on the bonding effect of the metallic glass layers 342 of the two semiconductor devices 300 can be reduced.

[0115] In some examples, the distance between the first surface 3421 and the second surface 3501 in the first direction F1 is equal to At this time, it is possible to avoid the metal glass layer 342 expanding too much out of the second surface 3501 due to insufficient expansion space, thereby affecting the bonding effect of the metal glass layer 342 in the two semiconductor devices 300; and it is also possible to reduce the impact of insufficient contact between the metal glass layers 342 of the two semiconductor devices 300 due to excessive expansion space, thereby affecting the bonding effect of the metal glass layers 342 of the two semiconductor devices 300.

[0116] Please continue reading Figure 5 In some embodiments, the dielectric layer 350 includes a first isolation layer 351, an intermediate layer 352, and a second isolation layer 353 sequentially stacked on the semiconductor structure 310; wherein the second surface 3501 of the dielectric layer 350 refers to the surface of the second isolation layer 353 facing away from the intermediate layer 352.

[0117] The first isolation layer 351 has an insulating property and may be made of an insulating material. For example, the material of the first isolation layer 351 may include oxide, such as SiO2 (silicon dioxide). In addition, the material of the first isolation layer 351 may also include silicon oxynitride and carbon nitride.

[0118] In some examples, the thickness of the first isolation layer 351 may be greater than or equal to Less than or equal to

[0119] For example, the thickness of the first isolation layer 351 may be equal to

[0120] The material of the interposer 352 may include SiN (silicon nitride).

[0121] In some examples, the thickness of the interposer 352 may be greater than or equal to and less than or equal to

[0122] For example, the thickness of the interposer 352 may be equal to

[0123] The second isolation layer 353 has an insulating property and may be made of an insulating material. For example, the material of the second isolation layer 353 may include oxide, such as SiO2 (silicon dioxide). In addition, the material of the second isolation layer 353 may also include silicon oxynitride and carbon nitride.

[0124] In some examples, the thickness of the second isolation layer 353 may be greater than or equal to Less than or equal to

[0125] For example, the thickness of the second isolation layer 353 may be equal to

[0126] The bonding pad 341 is embedded in the first isolation layer 351 , the intermediate layer 352 and the second isolation layer 353 , and the metallic glass layer 342 is embedded in the second isolation layer 353 .

[0127] The projection of the bonding pad 341 in the second direction F2 covers the first isolation layer 351 , the intermediate layer 352 and part of the second isolation layer 353 , while the projection of the metallic glass layer 342 in the second direction F2 covers part of the second isolation layer 353 . The second direction F2 is parallel to the second surface 3501 .

[0128] Please continue reading Figure 5 In some embodiments, the ratio of the thickness H4 of the bonding pad 341 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 10.55 and less than or equal to 158.9, that is, 10.55≤H4 / H3≤158.9.

[0129] Among them, H4 / H3 is greater than or equal to 10.55, so that the thickness H3 of the metallic glass layer 342 can be prevented from being too large. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may protrude too much from the second surface 3501 after expansion. At this time, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, a gap may exist between the two semiconductor devices 300. Therefore, by making H4 / H3 greater than or equal to 10.55, the phenomenon of the gap between the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can be reduced.

[0130] In addition, H4 / H3 is less than or equal to 158.9, so that the thickness H3 of the metallic glass layer 342 can be prevented from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 expand, thereby causing the metallic glass layers 342 of the two semiconductor devices 300 to be insufficiently bonded. Therefore, by making H4 / H3 less than or equal to 158.9, the phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by the metallic glass layer 342 being too small can be reduced.

[0131] For example, the ratio of the thickness H4 of the bonding pad 341 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 21.67 and less than or equal to 26.

[0132] In some embodiments, the thickness H4 of the bonding pad 341 is greater than or equal to and less than or equal to

[0133] By making the thickness H4 of the bonding pad 341 greater than or equal to It is possible to prevent the thickness H4 of the bonding pad 341 from being too thin, thereby preventing the metallic glass layer 342 on the surface of the bonding pad 341 from being too thick. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may bulge out too much from the second surface 3501 after expansion. In this case, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, a gap may exist between the two semiconductor devices 300. Therefore, by making the thickness H4 of the bonding pad 341 greater than or equal to The phenomenon that a gap exists between two semiconductor devices 300 due to excessive thickness of the metallic glass layer 342 can be reduced.

[0134] By making the thickness H4 of the bonding pad 341 less than or equal to It is possible to avoid that the thickness H4 of the bonding pad 341 is too large, thereby causing the metallic glass layer 342 on the surface of the bonding pad 341 to be too thin. If the thickness of the metallic glass layer 342 is too thin, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after the expansion of the metallic glass layers 342 of the two semiconductor devices 300, thereby causing the metallic glass layers 342 of the two semiconductor devices 300 to be insufficiently bonded. Therefore, by making the thickness H4 of the bonding pad 341 less than or equal to The phenomenon that the metallic glass layers 342 of the two semiconductor devices 300 are not sufficiently bonded due to the metallic glass layer 342 being too thin can be reduced.

[0135] For example, the thickness H4 of the bonding pad 341 is equal to At this time, the gap between the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can be reduced, and the insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can also be reduced.

[0136] Please continue reading Figure 5 In some embodiments, the bonding pad 341 includes a first portion 3411 and a second portion 3412, wherein one end of the first portion 3411 is connected to the semiconductor structure 310. The second portion 3412 is connected to the other end of the first portion 3411. For example, one end of the first portion 3411 may be electrically connected to the wiring layer 313.

[0137] In which, the cross-sectional area of ​​the first portion 3411 on the first reference plane is smaller than the cross-sectional area of ​​the second portion 3412 on the second reference plane, wherein the first reference plane and the second reference plane are both parallel to the surface of the metallic glass layer 342 facing away from the semiconductor structure 310, that is, the first reference plane and the second reference plane are both parallel to the first surface 3421 of the metallic glass layer 342, wherein the first reference plane passes through the first portion 3411, and the second reference plane passes through the second portion 3412.

[0138] The density of the metal wiring in the wiring layer 313 is relatively high. By providing a first portion 3411 with a smaller cross-sectional area in the bonding pad 341 , it is possible to facilitate the connection between the first portion 3411 and the metal wiring.

[0139] The cross-sectional area of ​​the second portion 3412 is relatively large, and the metallic glass layer 342 is disposed on the side of the second portion 3412 away from the first portion 3411. The area of ​​the bearing surface of the second portion 3412 can increase the area of ​​the metallic glass layer 342, thereby increasing the contact area of ​​the metallic glass layer 342 in the two semiconductor devices 300, and thus improving the bonding effect of the metallic glass layer 342 of the two semiconductor devices 300. The bearing surface of the second portion 3412 refers to the surface of the second portion 3412 connected to the metallic glass layer 342.

[0140] The ratio of the thickness H5 of the first portion 3411 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 5.55 and less than or equal to 75, that is, 5.55≤H5 / H3≤75.

[0141] Among them, H5 / H3 is greater than or equal to 5.55, so that the thickness H3 of the metallic glass layer 342 can be prevented from being too large. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may protrude too much from the second surface 3501 after expansion, and at this time, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, a gap exists between the two semiconductor devices 300. Therefore, by making H5 / H3 greater than or equal to 5.55, the phenomenon of the gap between the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can be reduced.

[0142] In addition, H5 / H3 is less than or equal to 75, so that the thickness H3 of the metallic glass layer 342 can be prevented from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 expand, thereby causing the metallic glass layers 342 of the two semiconductor devices 300 to be insufficiently bonded. Therefore, by making H5 / H3 less than or equal to 75, the phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by the metallic glass layer 342 being too small can be reduced.

[0143] In some examples, the thickness H5 of the first portion 3411 is greater than or equal to Less than or equal to

[0144] For example, the thickness H5 of the first portion 3411 is equal to

[0145] The ratio of the thickness H6 of the second portion 3412 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 5 and less than or equal to 83.9, that is, 5≤H6 / H3≤83.9.

[0146] Among them, H6 / H3 is greater than or equal to 5, so that the thickness H3 of the metallic glass layer 342 can be prevented from being too large. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may protrude too much from the second surface 3501 after expansion, and at this time, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, a gap exists between the two semiconductor devices 300. Therefore, by making H6 / H3 greater than or equal to 5, the phenomenon of a gap between the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can be reduced.

[0147] In addition, H6 / H3 is less than or equal to 83.9, so that the thickness H3 of the metallic glass layer 342 can be prevented from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 expand, thereby causing the metallic glass layers 342 of the two semiconductor devices 300 to be insufficiently bonded. Therefore, by making H6 / H3 less than or equal to 83.9, the phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by the metallic glass layer 342 being too small can be reduced.

[0148] In some examples, the thickness H6 of the second portion 3412 is greater than or equal to Less than or equal to

[0149] For example, the thickness H6 of the second portion 3412 is equal to

[0150] In some embodiments, the thickness H3 of the metallic glass layer 342 is greater than or equal to and less than or equal to

[0151] The thickness H3 of the metallic glass layer 342 is greater than or equal to This can prevent the thickness H3 of the metallic glass layer 342 from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after the expansion of the metallic glass layers 342 of the two semiconductor devices 300, thereby causing the metallic glass layers 342 of the two semiconductor devices 300 to be insufficiently bonded. Therefore, by making the thickness H3 of the metallic glass layer 342 greater than or equal to The phenomenon that the metallic glass layers 342 of the two semiconductor devices 300 are insufficiently bonded due to the metallic glass layer 342 being too thin can be reduced.

[0152] In addition, the thickness H3 of the metallic glass layer 342 is less than or equal to This can prevent the thickness H3 of the metallic glass layer 342 from being too large. If the thickness H3 of the metallic glass layer 342 is too large, the metallic glass layer 342 may bulge out too much from the second surface 3501 after expansion, and in this case, a gap may exist between the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 are bonded. Therefore, by making the thickness H3 of the metallic glass layer 342 less than or equal to The phenomenon that a gap exists between two semiconductor devices 300 due to excessive thickness of the metallic glass layer 342 can be reduced.

[0153] In some examples, the thickness H3 of the metallic glass layer 342 is greater than or equal to and less than or equal to At this time, the phenomenon of insufficient bonding of the metal glass layers 342 of the two semiconductor devices 300 due to the metal glass layer 342 being too thin can be reduced, and the phenomenon of a gap between the two semiconductor devices 300 due to the metal glass layer 342 being too thick can also be reduced.

[0154] In some embodiments, the material of the metallic glass layer 342 includes CuZr (Copper Zirconium).

[0155] After the bonding process of the metal glass layers 342 of the two semiconductor devices 300, when the two semiconductor devices 300 are annealed, when the annealing temperature reaches the crystallization temperature of CuZr, the Cu atoms in CuZr can be crystallized to precipitate single crystal Cu. In other words, the bonding connection 400 formed after the metal glass layers 342 of the two semiconductor devices 300 are bonded can include CuZr and single crystal Cu. The resistivity of single crystal Cu is less than that of CuZr, so the material of the metal glass layer 342 includes CuZr, which can reduce the resistivity of the bonding connection 400.

[0156] In some examples, the resistivity of the bond connection 400 is on the order of 10E-7Ωm.

[0157] In some examples, the resistance of metal bond connection 400 is approximately 0.0002Ω.

[0158] In some examples, the material of the metallic glass layer 342 includes Cu X Zr 100-X The ratio of Cu atoms to Zr atoms in the metallic glass layer 342 is X:100-X, where X is greater than or equal to 30 and less than or equal to 90.

[0159] By making X greater than or equal to 30, it is possible to avoid the proportion of Cu atoms in the metallic glass layer 342 being too small, thereby resulting in less single crystal Cu being formed. The smaller the proportion of single crystal Cu is, the greater the resistivity of the bonding connection 400 formed after the metallic glass layers 342 in the two semiconductor devices 300 are bonded. Therefore, by making X greater than or equal to 30, the problem of excessive resistivity of the bonding connection 400 caused by the small proportion of Cu atoms can be reduced.

[0160] In addition, by making X greater than or equal to 90, it is possible to avoid that the proportion of Cu atoms in the metallic glass layer 342 is too large, thereby causing the properties of the metallic glass layer 342 to be close to the bonding pad 341 made of Cu, thereby affecting the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300.

[0161] For example, X=85, in this case, 100-X=15. In this case, the material of the metallic glass layer 342 includes Cu 85 Zr 15 .

[0162] In some of the above embodiments, combined Figure 4 and Figure 5 , the semiconductor device 300 provided in the embodiment of the present application is introduced, and then the chip 100 formed by bonding two semiconductor devices 300 is introduced.

[0163] See you later Figure 3 In some embodiments, in the semiconductor device 300 , a bonding pad 341 of a bonding portion 340 has a recess on a surface of the semiconductor structure 310 facing away from the semiconductor device 300 , and a portion of the bonding connection portion 400 is filled in the recess.

[0164] Among them, the surface of the bonding pad 341 away from the semiconductor structure 310 is a non-smooth surface with a depression thereon. During the bonding process of the metal glass layer 342 of the two semiconductor devices 300, the temperature of the metal glass layer 342 will increase. When the temperature reaches the supercooled liquid phase, the metal glass layer 342 will be in a liquid-like state. Therefore, the metal glass layer 342 can have fluidity, and then the metal glass layer 342 can be filled in the depression on the surface of the bonding pad 341 away from the semiconductor structure 310, thereby increasing the connection effect between the metal glass layer 342 (that is, the bonding connection portion 400) and the bonding pad 341.

[0165] Next, a method for manufacturing the semiconductor device 300 is introduced.

[0166] Figure 6 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0167] See also Figure 6 , the method for preparing a semiconductor device includes: the following steps S1-S4.

[0168] S1. Forming a dielectric layer on the surface of the semiconductor structure.

[0169] The structure of the semiconductor structure 310 has been introduced in some of the above embodiments and will not be described in detail here.

[0170] Figures 7 to 14 A step diagram of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0171] See also Figures 7 to 10 In some examples, the dielectric layer 350 may include: a first isolation layer 351, an intermediate layer 352, and a second isolation layer 353. The materials of the first isolation layer 351, the intermediate layer 352, and the second isolation layer 353 have been introduced in some of the above embodiments and will not be described in detail here.

[0172] When forming the dielectric layer 350 , firstly, a first isolation layer 351 may be formed on the surface of the wiring layer 313 of the semiconductor structure 310 .

[0173] Next, an interposer 352 is formed on a surface of the first isolation layer 351 facing away from the semiconductor structure 310 .

[0174] Then, a second isolation layer 353 is formed on a surface of the interposer 352 facing away from the semiconductor structure 310 .

[0175] Among them, the first isolation layer 351, the intermediate layer 352 and the second isolation layer 353 can be formed by a thin film deposition process, and the thin film deposition process can include, for example, a chemical vapor deposition (chemical vapor deposition, CVD), a physical vapor deposition (physical vapor deposition, PVD), or an atomic layer deposition (atomic layer deposition, ALD) and an electrochemical deposition (electro-chemical-deposition, ECP) ​​process or a combination of one or more.

[0176] S2. Form a plurality of contact holes on the dielectric layer.

[0177] See also Fig.10In some examples, the contact hole 360 ​​may be a stepped hole. For example, the contact hole 360 ​​may include a first section hole 361 and a second section hole 362, wherein the first section hole 361 and the second section hole 362 are connected and arranged in sequence along the first direction F1. The first section hole 361 penetrates the first isolation layer 351, and the second section hole 362 penetrates the intermediate layer 352 and the second isolation layer 353. The first section hole 361 exposes the wiring layer 313 of the semiconductor structure 310.

[0178] The cross-sectional area of ​​the first section hole 361 is smaller than the cross-sectional area of ​​the second section hole 362, wherein the cross-sectional area of ​​the first section hole 361 refers to the cross-sectional area of ​​the first section hole 361 on the first reference plane. The cross-sectional area of ​​the second section hole 362 refers to the cross-sectional area of ​​the second section hole 362 on the second reference plane. The first reference plane and the second reference plane are both perpendicular to the first direction F1, wherein the first reference plane passes through the first section hole 361, and the second reference plane passes through the second section hole 362.

[0179] Wherein, step S2 may include the following steps: S21 to S24.

[0180] See also Figure 7 , S21, forming a plurality of first-stage holes 3601 on the dielectric layer 350, wherein the first-stage holes 3601 penetrate the first isolation layer 351, the intermediate layer 352 and the second isolation layer 353. The cross-sectional area of ​​the first-stage holes 3601 may be equal to the cross-sectional area of ​​the first-stage holes 361.

[0181] In some examples, in step S21 , the first-stage hole 3601 may be formed by an etching process.

[0182] See also Figure 8 , S22, filling the plurality of first stage holes 3601 with a sacrificial medium 3602.

[0183] See also Fig. 9 , S23, forming a plurality of second-stage holes 3603 on the dielectric layer 350, wherein the second-stage holes 3603 penetrate the intermediate layer 352 and the second isolation layer 353, wherein in the process of forming the second-stage holes 3603, the sacrificial dielectric 3602 in the intermediate layer 352 and the sacrificial dielectric 3602 in the second isolation layer 353 are removed.

[0184] Among them, the second stage hole 3603 can be used as the second section hole 362.

[0185] For example, in step S23, the second-stage hole 3603 may be formed by an etching process. In step S23, the sacrificial medium 3602 located in the first isolation layer 351 is retained.

[0186] See also Fig.10 , S24, removing the sacrificial medium 3602 (such as Fig. 9 As shown), the contact hole 360 ​​is formed. For example, in step S24, the sacrificial dielectric 3602 in the first isolation layer 351 may be removed by an etching process.

[0187] A plurality of contact holes are formed through the above steps S21 to S24.

[0188] Fig.10 The contact hole 360 ​​provided in the embodiment is a stepped hole, while in some other examples, the cross-sectional area of ​​the contact hole 360 ​​may remain unchanged along the first direction F1. Alternatively, the cross-sectional area of ​​the contact hole 360 ​​may gradually increase along the first direction F1.

[0189] S3. Form a bonding pad in the contact hole.

[0190] See also Fig.12 The bonding pad 341 includes a first portion 3411 and a second portion 3412. One end of the first portion 3411 is connected to the semiconductor structure 310. The second portion 3412 is connected to the other end of the first portion 3411. The first portion 3411 and the second portion 3412 can be formed in the same process.

[0191] The structures of the first part 3411 and the second part 3412 have been introduced in some of the above embodiments and will not be described in detail here.

[0192] Fig.15 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0193] See also Fig.15 , step S3 may include the following steps S31 and S32,

[0194] S31, depositing a metal material to fill the contact hole with the metal material.

[0195] See also Fig.11 In step S31 , the metal material 371 may not only fill the contact hole 360 ​​, but may also cover the surface of the dielectric layer 350 away from the semiconductor structure 310 , that is, cover the second surface 3501 .

[0196] The metal material may include at least one of gold, silver, copper, aluminum, titanium, molybdenum, tungsten, nickel and chromium.

[0197] In step S31, the metal material 371 may be formed by a thin film deposition process to fill the contact hole 360. For example, the thin film deposition process may include one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and electrochemical deposition.

[0198] In step S31 , the metal material 371 may completely fill the contact hole 360 ​​, and part of the metal material may protrude from the contact hole 360 ​​.

[0199] S32, removing the metal material at the top of the contact hole to form a first recess, and the metal material remaining in the contact hole is a bonding pad; the top is a region of the contact hole away from one end of the semiconductor structure.

[0200] See also Fig.12 In step S32 , in addition to removing the metal material 371 located on the top of the contact hole 360 ​​, the metal material 371 located on the second surface 3501 of the dielectric layer 350 is also removed. At this time, the metal material remaining in the contact hole 360 ​​can be used as the bonding pad 341 .

[0201] The metal material on the second surface 3501 of the dielectric layer 350 and the metal material on the top of the contact hole 360 ​​may be removed by a grinding process.

[0202] For example, the polishing process may include a CMP (chemical mechanical polishing) process.

[0203] After step S32, a bonding pad 341 is formed. The bonding pad 341 includes a third surface 3413 facing away from the semiconductor structure 310, and the dielectric layer 350 includes a second surface 3501 facing away from the semiconductor structure 310. After step S32, the third surface 3413 is closer to the semiconductor structure 310 than the second surface 3501. At this time, the third surface 3413 of the bonding pad 341 and the top area of ​​the contact hole 360 ​​can enclose a first recess 3604. The first recess 3604 is part of the contact hole 360.

[0204] In step S32, a first recess 3604 may be formed to provide a space for the metallic glass layer 342. In addition, after removing the metal material at the top of the contact hole, a bonding pad 341 may be formed, and at this time, the side of the bonding pad 341 facing away from the semiconductor structure 310 may have a flat surface.

[0205] The metal material 371 on the second surface 3501 of the dielectric layer 350 may be removed by a grinding process first, and then the metal material 371 on the top of the contact hole 360 ​​may be removed. When removing the metal material 371 on the top of the contact hole 360, the depth of the first recess 3604 may be controlled by adjusting the grinding pressure and grinding time during the grinding process.

[0206] In some examples, the depth of the first recess 3604 in the first direction F1 is greater than or equal to and less than or equal to

[0207] Wherein, by making the depth of the first recess 3604 in the first direction F1 greater than or equal to The first recess 3604 can be prevented from being too shallow, which would cause the metallic glass layer 342 disposed in the first recess 3604 to be too thin, so that the metallic glass layer 342 has a sufficient thickness. If the metallic glass layer 342 is too thin, a gap may exist between the metallic glass layer 342 and the metallic glass layer 342 in another semiconductor device 300 after the metallic glass layer 342 expands, so that the metallic glass layers 342 in the two semiconductor devices 300 are not sufficiently combined, thereby affecting the bonding effect of the metallic glass layers 342 in the two semiconductor devices 300, and further affecting the electrical connection effect of the metallic glass layers 342 in the two semiconductor devices 300.

[0208] By making the depth of the first recess 3604 in the first direction F1 less than or equal to It is possible to avoid the first recess 3604 being too deep, thereby preventing the metallic glass layer 342 disposed in the first recess 3604 from being too thick. If the metallic glass layer 342 is too thick, it is easy to cause the metallic glass layer 342 to bulge too much out of the second surface 3501 of the dielectric layer 350 after expansion, and a gap may exist after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, thereby affecting the connection effect between the two semiconductor devices 300. In addition, if the metallic glass layer 342 is too thick, it will also cause a waste of materials.

[0209] For example, the depth of the first recess 3604 in the first direction F1 is equal to At this time, the metal glass layer 342 can have a sufficient thickness to ensure the bonding effect of the metal glass layer 342 in the two semiconductor devices 300, and it can also prevent the metal glass layer 342 from being too thick, causing the metal glass layer 342 to expand and flow between the dielectric layers 350 of the two semiconductor devices 300, thereby affecting the connection effect between the metal glass layers 342 of the two semiconductor devices 300.

[0210] S4. Form a metallic glass layer in the contact hole, wherein the metallic glass layer overlaps and contacts the bonding pad.

[0211] After step S3, step S4 may be performed, wherein Fig.14 The metallic glass layer 342 can be formed in the contact hole 360 ​​and on the surface of the bonding pad 341 facing away from the semiconductor structure 310. At this time, the metallic glass layer 342 is in contact with the bonding pad 341, and the metallic glass layer 342 can be electrically connected to the bonding pad 341.

[0212] In summary, the preparation of the semiconductor device 300 is completed through the above steps S1 to S4. The metallic glass layer 342 in the semiconductor device 300 prepared through the above steps S1 to S4 has a liquid-like property when the temperature reaches or approaches the supercooled liquid phase region. In the bonding process of the metallic glass layer 342 of the bonding portion 340 in the two semiconductor devices 300, the metallic glass layers 342 in the two semiconductor devices 300 are aligned with high precision, and preliminarily mixed and bonded, and then annealed. During the annealing process, when the temperature reaches or approaches the supercooled liquid phase region, the metallic glass layers 342 of the two semiconductor devices 300 can soften and form a liquid-like state, thereby producing an effect similar to liquid flow, thereby reducing the gap at the contact interface of the metallic glass layers 342 of the two semiconductor devices 300, and further improving the contact effect of the metallic glass layers 342 of the two semiconductor devices 300, thereby improving the bonding effect of the two semiconductor devices 300, thereby improving the subsequent electrical test and reliability test of the chip 100.

[0213] In addition, the metallic glass layer 342 is an amorphous structure (i.e., a non-crystalline structure) at the microscopic level. The metal atoms in the metallic glass layer 342 do not occupy the lowest energy site, so the metal atoms are in a higher energy state in the structure. In this case, the metallic glass layer 342 can activate the movement of its local metal atomic clusters through ultrasonic vibration at room temperature, and the movement of the atomic clusters can make the atomic clusters break through the oxide layer of the bonding interface of the metallic glass layer 342. Therefore, the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300 is better. In addition, the metallic glass layer 342 in the two semiconductor devices 300 can be bonded under room temperature conditions.

[0214] In addition, during the annealing process, the movement of the metal atomic clusters will be more intense, which is more conducive to the metal atomic clusters breaking through the oxide layer of the bonding interface of the metallic glass layer 342, thereby improving the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300.

[0215] Please continue reading Fig.15 In some examples, when the method for preparing a semiconductor device includes steps S31 and S32, step S4 may include the following step S41.

[0216] S41, forming a metallic glass layer in the first recess.

[0217] In step S32 , the side of the bonding pad 341 facing away from the semiconductor structure 310 has a flat surface, which can provide a flat surface for the formation of the metallic glass layer, and is beneficial to improving the thickness uniformity of the metallic glass layer 342 .

[0218] In some examples, you can see Figure 4 , the thickness of the metallic glass layer 342 may be equal to the depth of the first recess 3604, while in some other examples, see Fig.14 , the thickness of the metallic glass layer 342 may be smaller than the first recess 3604 (eg Fig.12 shown) depth.

[0219] Next, the step S41 in the method for preparing a semiconductor device is introduced by taking the case where the thickness of the metallic glass layer 342 is smaller than the depth of the first recess 3604 as an example.

[0220] Fig.16 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0221] See also Fig.16 In some examples, step S41 may include the following steps S411 to S412.

[0222] S411 , depositing a metallic glass material, where the metallic glass material fills the first recess and covers the surface of the dielectric layer away from the semiconductor structure.

[0223] See also Fig.13 In step S411, the metallic glass material 3420 may be formed in the first recess 3604 (eg, Fig.12 As shown) and the second surface 3501 of the dielectric layer 350.

[0224] For example, the metallic glass material 3420 may include CuZr. Fig.12 As shown in the figure, in the case of the first recess 3604 and the second surface 3501 of the dielectric layer 350, an alloy target including CuZr can be pre-formed, and then the metallic glass material 3420 is deposited on the first recess 3604 and the second surface 3501 by single target sputtering.

[0225] The deposition time of the metallic glass material 3420 is relatively short, and the deposition of the metallic glass material 3420 of one semiconductor device 300 can be completed in about 10 minutes. Therefore, the time cost of using the metallic glass layer 342 to connect the semiconductor device 300 is relatively low.

[0226] Among them, Fig.13 In the example shown, in step S411, the metallic glass material 3420 can fill the first recess 3604 and protrude from the first recess 3604. At this time, the deposition thickness of the metallic glass material 3420 corresponding to the first recess 3604 is greater than the depth of the first recess 3604. The metallic glass material 3420 corresponding to the first recess 3604 refers to the thickness of the metallic glass material 3420 covered by the first recess 3604 in the first direction F1.

[0227] For example, the difference between the deposition thickness of the metallic glass material 3420 corresponding to the first recess 3604 and the depth of the first recess 3604 may be equal to

[0228] In some examples, the deposition thickness of metallic glass material 3420 corresponding to first recess 3604 is greater than or equal to Less than or equal to

[0229] In other examples, the metallic glass material 3420 may only fill a portion of the first recess 3604. In this case, a portion of the metallic glass material 3420 may be located in the bottom region of the first recess 3604, another portion of the metallic glass material 3420 may cover the sidewall of the top region of the first recess 3604, and another portion of the metallic glass material 3420 may cover the second surface 3501 of the dielectric layer 350.

[0230] S412, removing the metallic glass material covering the dielectric layer and the metallic glass material at the top of the first recess, and the metallic glass material remaining in the first recess is a metallic glass layer, wherein the top of the first recess is a region of the first recess away from one end of the semiconductor structure.

[0231] See also Fig.14 In step S412, the metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 and the metallic glass material 3420 on the top of the first recess 3604 are removed, and the metallic glass material 3420 on the bottom of the first recess 3604 can be used as the metallic glass layer 342. At this time, the first surface 3421 of the metallic glass layer 342 is closer to the semiconductor structure 310 than the second surface 3501.

[0232] At this time, the metallic glass layer 342 is sunken into the dielectric layer 350, and at this time, the first surface 3421 of the metallic glass layer 342 can enclose an expansion space with the dielectric layer 350. During the bonding process of the metallic glass layer 342 of the bonding portion 340 in the two semiconductor devices 300, the metallic glass layer 342 of the two semiconductor devices 300 can expand, and at this time, the volume of the metallic glass layer 342 can increase. By making the first surface 3421 of the metallic glass layer 342 and the dielectric layer 350 enclose an expansion space, the metallic glass layer 342 can expand into the expansion space, thereby preventing the metallic glass layer 342 from protruding too much from the second surface 3501 of the dielectric layer 350 after expansion. At this time, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, there may be a gap between the two semiconductor devices 300. Therefore, by making the first surface 3421 closer to the semiconductor structure 310 than the second surface 3501 , the phenomenon of a gap after bonding of the two semiconductor devices 300 due to expansion of the metallic glass layer 342 can be reduced.

[0233] For example, in step S412 , the metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 and the metallic glass material 3420 on the top of the first recess 3604 may be removed by a grinding process.

[0234] For example, the polishing process may include a CMP (chemical mechanical polishing) process.

[0235] The metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 may be removed by a grinding process first, and then the metallic glass material 3420 on the top of the first recess 3604 may be removed. When removing the metallic glass material 3420 on the top of the first recess 3604, the distance between the first surface 3421 and the second surface 3501 of the metallic glass layer 342 in the first direction F1 may be controlled by adjusting the grinding pressure and the grinding time during the grinding process.

[0236] In some examples, in step S412, the distance between the first surface 3421 of the metallic glass layer 342 and the second surface 3501 of the dielectric layer 350 in the first direction F1 is greater than or equal to Less than or equal to

[0237] For example, the distance between the first surface 3421 of the metallic glass layer 342 and the second surface 3501 of the dielectric layer 350 in the first direction F1 is equal to

[0238] In step S412 , the metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 and the metallic glass material 3420 on the top of the first recess 3604 are removed, and the metallic glass layer 342 occupies part of the space of the first recess 3604 .

[0239] Fig.17 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0240] See also Fig.17 In some other examples, step S41 may include steps S411 and S413, wherein step S413 may be performed after step S411.

[0241] S413, removing the metallic glass material on the surface of the dielectric layer facing away from the semiconductor structure, and retaining the metallic glass material in the first recess to form a metallic glass layer.

[0242] The metallic glass layer 342 formed in step S413 may occupy the first recess 3604 (eg Fig.12 ) of the entire space, at this time, the structure of the semiconductor device 300 can refer to Figure 4 For example, in step S413, the metallic glass material 3420 located on the second surface 3501 of the dielectric layer 350 may be removed by a grinding process. For example, the grinding process may include a CMP (chemical mechanical polishing) process.

[0243] exist Figures 7 to 14 In the provided embodiment, in step S3, during the process of forming the bonding pad in the contact hole, the bonding pad 341 may directly contact the sidewall of the contact hole 360. In other examples, before forming the bonding pad 341, a barrier layer and a seed layer may be formed in the contact hole 360, and in this case, the bonding pad 341 may be formed by electrochemical deposition.

[0244] The following takes the formation of the bonding pad 341 by an electrochemical deposition process as an example to introduce the preparation method of the bonding pad 341 .

[0245] Fig.18 Another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application; Figures 19 to 24 A step diagram of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0246] See also Fig.18 , step S3 may include the following steps S28 and S29.

[0247] S28. Form a barrier layer in the contact hole.

[0248] See also Fig.19 In step S28 , the barrier layer 372 may be formed by a thin film deposition process. In step S28 , the barrier layer 372 also covers the surface of the dielectric layer 350 away from the semiconductor structure 310 .

[0249] In some examples, the barrier layer 372 may include Ta (tantalum) and tantalum nitride. The barrier layer 372 has conductivity, and thus, the barrier layer 372 may be conductively connected to the semiconductor structure 310 .

[0250] S29. Form a seed layer in the contact hole.

[0251] See also Fig. 20 In step S29 , the seed layer 373 may be formed by physical vapor deposition. In step S29 , the seed layer 373 also covers the surface of the barrier layer 372 away from the semiconductor structure 310 .

[0252] In some examples, the seed layer 373 may include Cu, which is a conductive material, and thus the seed layer 373 may be conductively connected to the barrier layer 372 .

[0253] After step S29 , step S3 may be performed to form a bonding pad in the contact hole.

[0254] It should be noted that the bonding pad 341 is formed in the contact hole 360. At this time, the bonding pad 341 can be spaced apart from the hole wall of the contact hole 360. For example, a barrier layer 372 and a seed layer 373 are spaced apart between the bonding pad 341 and the hole wall of the contact hole 360. The barrier layer 372 can prevent the Cu in the bonding pad 341 from diffusing into the interconnection layer 330, thereby ensuring the insulation of the interconnection layer 330. By forming the seed layer 373 in the contact hole 360, the bonding pad 341 can be easily bonded.

[0255] Wherein, step S3 may include the following steps S33 and S34.

[0256] S33, depositing metal material to fill the contact hole with the metal material.

[0257] See also Fig.21 In step S33, the metal material can not only fill the contact hole 360, but also cover the second surface 3501 of the dielectric layer 350. In the embodiment of the present application, when the metal material 371 covers the second surface 3501, the metal material 371 can directly contact the second surface 3501. At this time, the positional relationship between the metal material 371 and the second surface 3501 can be as follows: Fig.11Alternatively, the metal material 371 may be spaced apart from the second surface 3501 , and in this case, a barrier layer 372 and a seed layer 373 are spaced apart from the metal material 371 and the second surface 3501 .

[0258] The deposition process of the metal material 371 has been introduced in some of the above embodiments and will not be described again here.

[0259] S34, removing the metal material at the top of the contact hole and the seed layer at the top of the contact hole to form a second recess, and the metal material retained in the contact hole is a bonding pad; the top of the contact hole is the area of ​​the contact hole away from one end of the semiconductor structure.

[0260] See also Fig. 22 In step S34, in addition to removing the metal material 371 on the top of the contact hole 360, the metal material 371 on the surface of the seed layer 373 facing away from the second surface 3501 is also removed. In addition, the seed layer 373 on the surface of the barrier layer 372 facing away from the second surface 3501 and the seed layer 373 on the top of the contact hole 360 ​​are also removed. The metal material 371 retained in the contact hole 360 ​​can be used as a bonding pad 341.

[0261] At this time, the bonding pad 341, the seed layer 373 in the contact hole 360, and the barrier layer 372 in the contact hole 360 ​​may surround a second recess 3605. Fig. 22 In the figure, the dotted frame indicated by the label 3605 is the location of the second recess 3605. It should be noted that the dotted frame indicated by the label 3605 is only used to indicate the location of the second recess 3605, and does not represent the actual boundary of the second recess 3605.

[0262] After step S34 , step S4 may be performed to form a metallic glass layer in the contact hole, wherein the metallic glass layer overlaps and contacts the bonding pad.

[0263] In some examples, step S4 may include S414 and S415.

[0264] S414 , depositing a metallic glass material, and filling the second recess with the metallic glass material.

[0265] See also Fig.23 In step S414, the metallic glass material 3420 may be filled in the second recess 3605 (eg Fig. 22 As shown), at this time, the metallic glass layer 342O can fill the second recess 3605 and protrude from the second recess 3605.

[0266] In addition, the metallic glass material 3420 may also cover the surface of the barrier layer 372 facing away from the second surface 3501 of the dielectric layer 350 .

[0267] S415, removing the metallic glass material at the top of the second recess, and the metallic glass material remaining in the second recess is a metallic glass layer, wherein the top of the second recess is a region of the second recess away from one end of the semiconductor structure.

[0268] See also Fig.24 The metallic glass layer 342 formed in step S415 may occupy the second recess 3605 (eg Fig.23 Therefore, the thickness of the metallic glass layer 342 is less than the depth of the second recess 3605. At this time, the first surface 3421 of the metallic glass layer 342 is closer to the semiconductor structure 310 than the second surface 3501.

[0269] The metallic glass layer 342 is sunken into the dielectric layer 350. At this time, the first surface 3421 of the metallic glass layer 342 can enclose an expansion space with the dielectric layer 350. During the bonding process of the metallic glass layer 342 of the bonding portion 340 in the two semiconductor devices 300, the metallic glass layer 342 of the two semiconductor devices 300 can expand. At this time, the volume of the metallic glass layer 342 can increase. By making the first surface 3421 of the metallic glass layer 342 and the dielectric layer 350 enclose an expansion space, the metallic glass layer 342 can expand into the expansion space, thereby preventing the metallic glass layer 342 from protruding too much from the second surface 3501 of the dielectric layer 350 after expansion. At this time, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, there may be a gap between the two semiconductor devices 300. Therefore, by making the first surface 3421 closer to the semiconductor structure 310 than the second surface 3501 , the phenomenon of a gap after bonding of the two semiconductor devices 300 due to expansion of the metallic glass layer 342 can be reduced.

[0270] In some examples, the method for preparing a semiconductor device may further include: S416 , removing the barrier layer 372 on the second surface.

[0271] See also Fig.24 After removing the barrier layer 372 on the second surface 3501, the second surface 3501 of the dielectric layer 350 can be exposed. The barrier layer 372 can be electrically connected to the metallic glass layer 342 through the seed layer 373. Therefore, after removing the barrier layer 372 on the second surface 3501, electrical connection of multiple metallic glass layers 342 through the barrier layer 372 can be avoided.

[0272] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: semiconductor structures and interconnect layers; The interconnection layer is located on one side of the semiconductor structure, and the interconnection layer includes a plurality of bonding parts arranged at intervals, and the bonding parts include bonding pads and a metallic glass layer, wherein the bonding pads are connected to the semiconductor structure, and the metallic glass layer covers a side of the bonding pads away from the semiconductor structure.

2. The semiconductor device according to claim 1, wherein: The interconnection layer further comprises: a dielectric layer, the bonding portion is embedded in the dielectric layer, the dielectric layer exposes a first surface of the metallic glass layer, and the first surface is a surface of the metallic glass layer away from the semiconductor structure; The dielectric layer includes a second surface facing away from the semiconductor structure; The first surface is closer to the semiconductor structure than the second surface.

3. The semiconductor device according to claim 2, characterized in that The distance between the first surface and the second surface in the first direction is greater than or equal to and less than or equal to Wherein, the first direction is perpendicular to the first surface.

4. The semiconductor device according to claim 2 or 3, characterized in that: The dielectric layer includes a first isolation layer, an intermediate layer, and a second isolation layer sequentially stacked on the semiconductor structure; The bonding pad is embedded in the first isolation layer, the intermediate layer and the second isolation layer, and the metallic glass layer is embedded in the second isolation layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: A ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is greater than or equal to 10.55 and less than or equal to 158.

9.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The bonding pad comprises a first portion and a second portion, one end of the first portion is connected to the semiconductor structure, the second portion is connected to the other end of the first portion, a cross-sectional area of ​​the first portion on a first reference plane is smaller than a cross-sectional area of ​​the second portion on a second reference plane, wherein the first reference plane and the second reference plane are both parallel to a surface of the metallic glass layer facing away from the semiconductor structure; Wherein, the ratio of the thickness of the first portion to the thickness of the metallic glass layer is greater than or equal to 5.55 and less than or equal to 75; A ratio of a thickness of the second portion to a thickness of the metallic glass layer is greater than or equal to 5 and less than or equal to 83.

9.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The thickness of the metallic glass layer is greater than or equal to and less than or equal to 8. The semiconductor device according to any one of claims 1 to 7, characterized in that: The thickness of the bonding pad is greater than or equal to and less than or equal to 9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The material of the metallic glass layer includes CuZr.

10. A chip, characterized in that: include: Two semiconductor devices according to any one of claims 1 to 8, wherein the metallic glass layers of the multiple bonding portions of the two semiconductor devices are bonded to form a plurality of bonding connection portions.

11. The chip according to claim 10, characterized in that: In the semiconductor device, a bonding pad of the bonding portion has a recess on a surface facing away from the semiconductor structure of the semiconductor device, and a portion of the bonding connection portion is filled in the recess.

12. The chip according to claim 10 or 11, characterized in that: The material of the bonding connection includes CuZr and single crystal Cu.

13. An electronic device, characterized in that: include: Circuit boards; The chip according to any one of claims 10 to 12, wherein the chip is arranged on the circuit board.

14. A method for preparing a semiconductor device, characterized in that: include: forming a dielectric layer on a surface of the semiconductor structure; forming a plurality of contact holes on the dielectric layer; forming a bonding pad in the contact hole; A metallic glass layer is formed in the contact hole, the metallic glass layer overlapping and contacting the bonding pad.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The step of forming bonding pads in the plurality of contact holes comprises: Depositing a metal material, wherein the metal material fills the contact hole; The metal material at the top of the contact hole is removed to form a first recess, and the metal material remaining in the contact hole is the bonding pad; the top of the contact hole is a region of the contact hole away from one end of the semiconductor structure; The forming of a metallic glass layer in the contact hole comprises: The metallic glass layer is formed in the first recess.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: The forming of the metallic glass layer in the first recess comprises: Depositing a metallic glass material, wherein the metallic glass material fills the first recess and covers a surface of the dielectric layer facing away from the semiconductor structure; The metallic glass material on the surface of the dielectric layer facing away from the semiconductor structure is removed, and the metallic glass material in the first recess is retained to form the metallic glass layer.

17. The method for preparing a semiconductor device according to claim 15, characterized in that: The forming of the metallic glass layer in the first recess comprises: Depositing a metallic glass material, wherein the metallic glass material fills the first recess and covers a surface of the dielectric layer facing away from the semiconductor structure; The metallic glass material on the surface of the dielectric layer facing away from the semiconductor structure and the metallic glass material located at the top of the first recess are removed, and the metallic glass material retained in the first recess is the metallic glass layer, wherein the top of the first recess is the region at one end of the first recess facing away from the semiconductor structure.

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