MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) semiconductor structure for optimizing source-drain contact and preparation method thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor structure for optimizing source and drain contact, which comprises a drain, a semiconductor epitaxial layer, a source and a grid, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P well layer, an N well layer and a P-layer, the P-layer is internally provided with source polycrystalline silicon, and the N drift layer is internally provided with drain polycrystalline silicon. The top end of the source polycrystalline silicon is in ohmic contact with the source electrode; three metal oxide layers are arranged in the N well layer, and the top ends of the three metal oxide layers are connected with a source electrode; a plurality of semicircular metal layers are also arranged in the drain electrode; and the semicircular metal layers are in ohmic contact with the N substrate layer. According to the invention, a low-resistance channel is formed through the high-concentration phosphorus-doped heavily-doped gate, the charge and discharge time of gate charges is reduced, and the doped gate provides an additional conductive path, so that the switching time is reduced, the power conversion efficiency is improved, and the heat loss is reduced.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and more particularly to a MOSFET semiconductor structure with optimized source-drain contacts and a method for manufacturing the same. Background Art

[0002] With the rapid development of power electronics technology, metal-oxide-semiconductor field-effect transistors (MOSFETs), as core power switching devices, have been widely used in fields such as new energy conversion, motor drives, and high-frequency power supplies.

[0003] However, traditional MOSFETs typically employ an ohmic contact structure of planar polysilicon and metal. Due to uneven interfacial impurity diffusion or limited contact area, the contact resistance is prone to being relatively high. For example, the design of the polysilicon doping concentration gradient in the source region is insufficient, resulting in a tortuous carrier transport path and further increasing the on-resistance (Rds(on)). Although existing technologies attempt to reduce the contact resistance through metal silicides, the interfacial stability of silicides is poor in high-temperature processes, easily leading to contact degradation and affecting the long-term reliability of the device.

[0004] A prior patent discloses a hybrid-gate SiC MOSFET cell structure, device, and manufacturing method (publication number CN116053316A), belonging to the field of semiconductor device technology. The cell structure includes an N++ type SiC substrate; an N-type SiC drift layer disposed above the substrate. In the technology disclosed in this patent, in high-current applications, local hotspots are likely to occur in the drain region due to current density concentration, leading to an aggravated hot carrier injection effect and even thermal breakdown. Existing solutions mostly rely on increasing the thermal conductivity of heat sinks or packaging materials, but such methods cannot fundamentally optimize the internal thermal distribution of the device. In addition, the traditional drain structure has limited ability to regulate the electric field. Under high-voltage operating conditions, the phenomenon of electric field edge concentration (such as insufficient optimization of the RESURF effect) will reduce the breakdown voltage (BVDSS), restricting the high-voltage application scenarios of the device. Summary of the Invention

[0005] The present invention provides a MOSFET semiconductor structure with optimized source-drain contacts and a method for manufacturing the same to solve the existing technical problems and address the issues in the above background art.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a MOSFET semiconductor structure with optimized source-drain contacts includes a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P well layer, an N well layer, and a P- layer. A source polysilicon is provided inside the P- layer, and the top of the source polysilicon is in ohmic contact with the source. Inside the N-well layer, there are three metal oxide layers, and the tops of the three metal oxide layers are connected to the source electrode; Inside the drain electrode, there are also several semicircular metal layers, and the semicircular metal layers are in ohmic contact with the N-substrate layer.

[0007] Furthermore, the cross-sectional profile of the P-layer is in an "L" shape.

[0008] Furthermore, on both the left and right sides of the bottom end of the semiconductor epitaxial layer, there are drain polysilicons, and the bottom ends of the drain polysilicons are in contact with the drain electrode.

[0009] Furthermore, the N-substrate layer also includes a first substrate layer, and the top end of the drain polysilicon is in ohmic contact with the N-drift layer.

[0010] Furthermore, the N-substrate layer also includes a second substrate layer, and the entire N-substrate layer is wrapped by the second substrate layer.

[0011] Furthermore, the N-substrate layer also includes a third substrate layer, and the cross-sectional profile of the third substrate layer is in a shape with both sides bulging and the middle concave.

[0012] Furthermore, four heavily doped gates are formed by ion implantation in the middle concave portion of the third substrate layer.

[0013] A preparation method for an optimized source-drain contact MOSFET semiconductor structure, the specific steps are as follows: S1. Sequentially grow an N-drift layer, a P-well layer, an N-well layer, and a P-layer by chemical vapor deposition; S2. Deposit source polysilicon on the surface of the P-layer, and form N+ doping through phosphorus ion implantation to achieve ohmic contact with the source electrode; S3. Deposit drain polysilicon layers on both the left and right sides of the N-substrate layer, define the drain polysilicon regions through photolithography and etching, and then perform annealing to optimize the contact resistance; S4. Deposit tungsten oxide inside the N-well layer, form three metal oxide layers through photolithography and dry etching, and connect them to the source electrode; S5. Deposit metal aluminum or in the drain region, and form semicircular metal layers through patterned etching; S6. Form the third substrate layer in the N-substrate layer through photolithography and ion implantation, and its cross-section is in a shape with both sides bulging and the middle concave; S7. Perform high-concentration phosphorus implantation in the concave region of the third substrate layer to form four heavily doped gates; S8. Perform electrical performance detection on the MOSFET semiconductor structure containing four heavily doped gates.

[0014] Further, in step S8, according to the variation of the on-resistance, threshold voltage, and switching time of the MOSFET semiconductor structure from 25°C to 100°C, the performance of the MOSFET semiconductor structure is determined. Then, we have: ; In the formula, represents the performance stability coefficient of the MOSFET semiconductor structure; represents the variation of the on-resistance of the MOSFET semiconductor structure from 25°C to 100°C; represents the variation of the switching time of the MOSFET semiconductor structure from 25°C to 100°C.

[0015] An optimized source-drain contact MOSFET semiconductor structure and its manufacturing method provided by the present invention, compared with the prior art, the effects achieved by this method are as follows: 1. Through the ohmic contact design between the semi-circular metal layer and the N substrate layer, the present invention utilizes the semi-circular structure to disperse the current density, avoid local hot spots, enhance the heat dissipation capacity of the drain, and improve the high-current carrying stability of the device.

[0016] 2. By directly forming a low-resistance contact between the drain polysilicon and the N drift layer, the present invention shortens the transmission path of carriers from the drain to the drift layer, reduces the total resistance in the drain region, and improves the efficiency of the device in high-voltage applications.

[0017] 3. By using a high-thermal conductivity material for the second substrate layer, the present invention quickly conducts heat from the N substrate layer to the package substrate, reduces the operating temperature of the device, extends the lifespan, and improves the stability in a high-temperature environment.

[0018] 4. By dispersing the electric field line density in the recessed area of the third substrate layer, the present invention avoids the concentration of the edge electric field, increases the breakdown voltage, and enhances the voltage withstand capacity of the device.

[0019] 5. By forming a low-resistance channel with a highly doped phosphorus-doped gate, the present invention reduces the charge charging and discharging time of the gate, and the doped gate provides an additional conduction path, reduces the switching time, improves the power conversion efficiency, and reduces heat loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic structural diagram of the first embodiment of the present invention; Figure 2 is a schematic structural diagram of the second embodiment of the present invention; Figure 3 is a schematic structural diagram of the third embodiment of the present invention; Figure 4 is a schematic structural diagram of the fourth embodiment of the present invention; Figure 5This is the schematic structural diagram of Embodiment 5 in the present invention.

[0021] In the figure: 1, drain; 2, N substrate layer; 3, N drift layer; 4, source; 5, gate; 6, P well layer; 7, N well layer; 8, P- layer; 9, source polysilicon; 10, metal oxide layer; 11, semi-circular metal layer; 12, drain polysilicon; 13, heavily doped gate; 21, substrate layer 1; 22, substrate layer 2; 23, substrate layer 3. Specific Embodiments

[0022] To make the technical solutions of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0023] As Figures 1-5 shown, a preparation method for an optimized source-drain contact MOSFET semiconductor structure includes the following specific steps: Step 1: Sequentially grow an N drift layer 3, a P well layer 6, an N well layer 7, and a P- layer 8 by chemical vapor deposition; Step 2: Deposit source polysilicon 9 on the surface of the P- layer 8, and form an N+ doping through phosphorus ion implantation to achieve an ohmic contact with the source 4; Step 3: Deposit a drain polysilicon layer 12 on both the left and right sides of the N substrate layer 2, define the drain polysilicon 12 region through photolithography and etching, and then perform annealing to optimize the contact resistance; Step 4: Deposit tungsten oxide inside the N well layer 7, form three metal oxide layers 10 through photolithography and dry etching, and connect them to the source 4; Step 5: Deposit metal aluminum or in the drain 1 region, and form a semi-circular metal layer 11 through patterned etching; Step 6: Form a substrate layer 3 in the N substrate layer 2 through photolithography and ion implantation, and its cross-section has a shape with convex sides and a concave middle; Step 7: Perform high-concentration phosphorus implantation in the concave region of the substrate layer 3 to form four heavily doped gates 13; Step 8: Perform electrical performance detection on the MOSFET semiconductor structure containing four heavily doped gates 13. According to the change amounts of the on-resistance, threshold voltage, and switching time of the MOSFET semiconductor structure from 25°C to 100°C, determine the performance of the MOSFET semiconductor structure, then there is: ; In the formula, represents the performance stability coefficient of the MOSFET semiconductor structure; represents the change amount of the on-resistance of the MOSFET semiconductor structure from 25°C to 100°C; represents the change amount of the switching time of the MOSFET semiconductor structure from 25°C to 100°C.

[0024] Among them, the performance temperature coefficient of the device with any power is calculated. The change in the on-resistance of the MOSFET semiconductor structure from 25°C to 100°C is taken as (Change in on-resistance = |On-resistance at 100°C - On-resistance at 25°C| ÷ On-resistance at 20°C × 100%). The change in the switching time of the MOSFET semiconductor structure from 25°C to 100°C is taken as (Change in switching time = |Switching time at 100°C - Switching time at 25°C| ÷ Switching time at 20°C × 100%). Then there is: It can be known from the above calculations that the performance stability coefficient of the MOSFET semiconductor structure is .

[0025] Again, the performance temperature coefficient of the traditional device with the same power is calculated. The change in the on-resistance of the traditional MOSFET semiconductor structure from 25°C to 100°C is taken as . The change in the switching time of the traditional MOSFET semiconductor structure from 25°C to 100°C is taken as , then there is: It can be known from the above calculations that the performance stability coefficient of the MOSFET semiconductor structure in this application is increased by 36.3% compared with the traditional MOSFET semiconductor structure.

[0026] Example 1 As Figure 1 shown, according to one aspect of the present invention, a MOSFET semiconductor structure with optimized source-drain contact is provided, including a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5. The semiconductor epitaxial layer includes an N substrate layer 2, an N drift layer 3, a P-well layer 6, an N-well layer 7, and a P-layer. A source polysilicon 9 is provided inside the P-layer 8, and the top of the source polysilicon 9 is in ohmic contact with the source 4; three metal oxide layers 10 are provided inside the N-well layer 7, and the tops of the three metal oxide layers 10 are connected to the source 4; the inside of the drain 1 further includes a plurality of semi-circular metal layers 11, and the semi-circular metal layers 11 are in ohmic contact with the N substrate layer 2. The ohmic contact design between the semi-circular metal layers 11 and the N substrate layer 2 uses a semi-circular structure to disperse the current density, avoid local hot spots, enhance the heat dissipation ability of the drain, and improve the high-current carrying stability of the device.

[0027] The cross-sectional profile of the P-layer 8 is in the shape of an "L". The "L"-shaped P-layer 8 increases the contact area between the source electrode 4 and the P-layer 8, reduces the tortuosity of the carrier transmission path, and at the same time, the source polysilicon 9 is in direct ohmic contact with the source electrode 4, significantly reducing the contact resistance, improving the current conduction efficiency, and reducing the conduction loss.

[0028] Example 2 As Figure 2 shown, drain polysilicons 12 are provided on both the left and right sides of the bottom end of the semiconductor epitaxial layer, and the bottom end of the drain polysilicon 12 is in contact with the drain electrode 1. The N-substrate layer 2 further includes a substrate layer one 21, wherein the top end of the drain polysilicon 12 is in ohmic contact with the N-drift layer 3. The drain polysilicon 12 directly forms a low-resistance contact with the N-drift layer 3, shortening the carrier transmission path from the drain electrode to the drift layer, reducing the total resistance of the drain region, and improving the efficiency of the device in high-voltage applications.

[0029] Moreover, the substrate layer one 21 serves as a buffer layer, reducing the lattice mismatch between the N-substrate layer 2 and the N-drift layer 3, reducing the interface defect density, suppressing the leakage current, and improving the device reliability.

[0030] Example 3 As Figure 3 shown, drain polysilicons 12 are provided on both the left and right sides of the bottom end of the semiconductor epitaxial layer, and the bottom end of the drain polysilicon 12 is in contact with the drain electrode 1. The N-substrate layer 2 further includes a substrate layer two 22, wherein the entire N-substrate layer 2 is wrapped by the substrate layer two 22. The substrate layer two 22 is made of a material with high thermal conductivity, quickly conducting heat from the N-substrate layer 2 to the package substrate, reducing the device operating temperature, extending the life, and enhancing the stability in a high-temperature environment.

[0031] Example 4 As Figure 4 shown, drain polysilicons 12 are provided on both the left and right sides of the bottom end of the semiconductor epitaxial layer, and the bottom end of the drain polysilicon 12 is in contact with the drain electrode 1. The N-substrate layer 2 further includes a substrate layer three 23, wherein the cross-sectional profile of the substrate layer three 23 is in the shape of two convex sides and a concave middle. The concave region disperses the electric field line density, avoiding edge electric field concentration (such as the RESURF effect), and at the same time increasing the breakdown voltage (BVDSS) and enhancing the voltage withstand capacity of the device.

[0032] The two convex structures on both sides guide the carriers to concentrate in the central concave region, reducing the on-resistance, increasing the current density, and improving the dynamic response speed.

[0033] Example 5 As Figure 5As shown, drain polysilicons 12 are provided on both the left and right sides at the bottom end of the semiconductor epitaxial layer. The bottom end of the drain polysilicon 12 is in contact with the drain electrode 1. The N-type substrate layer 2 further includes a substrate layer three 23, wherein the cross-sectional profile of the substrate layer three 23 is in the shape of two convex sides and a concave middle. Four heavily doped gates 13 are formed in the middle concave portion of the substrate layer three 23 by ion implantation. The heavily doped gates 13 doped with high-concentration phosphorus form a low-resistance channel, reducing the charge and discharge time of the gate charge, and the doped gates 13 provide an additional conduction path, reducing the switching time, improving the power conversion efficiency, and reducing heat loss.

[0034] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. A MOSFET semiconductor structure with optimized source-drain contact, comprising a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (5), wherein the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P well layer (6), an N well layer (7) and a P-layer, characterized in that: A source polysilicon (9) is provided inside the P-layer (8), and the top of the source polysilicon (9) is in ohmic contact with the source electrode (4); Three metal oxide layers (10) are provided inside the N-well layer (7), and the tops of the three metal oxide layers (10) are connected to the source electrode (4); The drain electrode (1) further comprises a plurality of semicircular metal layers (11) inside, and the semicircular metal layers (11) are in ohmic contact with the N substrate layer (2).

2. The MOSFET semiconductor structure with optimized source-drain contact according to claim 1, characterized in that: The cross-sectional profile of the P-layer (8) is in an "L" shape.

3. The MOSFET semiconductor structure with optimized source-drain contact according to claim 1, characterized in that: Drain polysilicon (12) is provided on both left and right sides of the bottom of the semiconductor epitaxial layer, and the bottom of the drain polysilicon (12) is in contact with the drain electrode (1).

4. The MOSFET semiconductor structure with optimized source-drain contact according to claim 3, characterized in that: The N substrate layer (2) further comprises a substrate layer 1 (21), wherein the top of the drain polysilicon (12) is in ohmic contact with the N drift layer (3).

5. The MOSFET semiconductor structure with optimized source-drain contact according to claim 3, characterized in that: The N substrate layer (2) further comprises a substrate layer 2 (22), wherein the N substrate layer (2) is completely wrapped by the substrate layer 2 (22).

6. The MOSFET semiconductor structure with optimized source-drain contact according to claim 3, characterized in that: The N substrate layer (2) further comprises a substrate layer three (23), wherein the cross-sectional profile of the substrate layer three (23) is in the shape of convexities on two sides and a concave middle.

7. The MOSFET semiconductor structure with optimized source-drain contacts according to claim 6, characterized in that: Four heavily doped gates (13) are formed in the middle recess of the substrate layer three (23) by ion implantation.

8. A method for preparing a MOSFET semiconductor structure with optimized source-drain contact, characterized in that: The MOSFET semiconductor structure applied to any one of claims 1 to 7, wherein the preparation method comprises the following specific steps: S1, sequentially growing an N drift layer (3), a P well layer (6), an N well layer (7), and a P-layer (8) by chemical vapor deposition; S2, depositing source polysilicon (9) on the surface of the P-layer (8), and forming N+ doping by phosphorus ion implantation to achieve ohmic contact with the source electrode (4); S3, depositing a drain polysilicon layer (12) on the left and right sides of the N substrate layer (2), defining the drain polysilicon (12) region by photolithography and etching, and then performing annealing to optimize the contact resistance; S4, depositing tungsten oxide inside the N-well layer 7, forming three metal oxide layers (10) by photolithography and dry etching, and connecting them to the source electrode (4); S5, depositing metal aluminum in the drain (1) region or forming a semicircular metal layer (11) by patterning and etching; S6. Forming a substrate layer three (23) in the N substrate layer (2) by photolithography and ion implantation, wherein the cross section of the substrate layer has convex sides and a concave middle; S7, implanting high concentration phosphorus into the recessed area of ​​the substrate layer 3 (23) to form four heavily doped gates (13); S8. Conduct electrical performance testing on the MOSFET semiconductor structure containing four heavily doped gates (13).

9. The method for preparing a MOSFET semiconductor structure with optimized source-drain contacts according to claim 8, characterized in that: In step S8, the performance of the MOSFET semiconductor structure is determined according to the changes in the on-resistance, threshold voltage and switching time of the MOSFET semiconductor structure when the temperature changes from 25° C. to 100° C., then: ； In the formula, Indicates the performance stability coefficient of the MOSFET semiconductor structure; It indicates the change of on-resistance of the MOSFET semiconductor structure from 25℃ to 100℃; It indicates the change in switching time of the MOSFET semiconductor structure from 25°C to 100°C.

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