MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure with nanosheet full-surrounding grid electrode and manufacturing process thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a MOSFET structure with nanosheet all-around gate and a manufacturing process thereof. BACKGROUND

[0002] With the miniaturization of semiconductor devices approaching the physical limit, traditional planar gate and FinFET structures face the challenges of weakened gate control ability and significantly intensified short channel effect at nodes below 5 nanometers. Although nanosheet transistors with all-around gate (GAA) improve gate control ability through three-dimensional channels, the existing structure still has key bottlenecks: first, the contact resistance between the nanosheet gate and the external electrode is high, which restricts the drive current density; second, high-density nanosheet arrays are prone to cause local concentration of electric field in high-voltage applications, leading to premature breakdown of the drift region, and the conventional guard ring design is difficult to balance the improvement of withstand voltage and the optimization of on-resistance (Rdson); third, uneven terminal electric field distribution induces edge breakdown, limiting high-voltage reliability. In addition, the existing manufacturing process lacks sufficient precision in the coordinated control of complex three-dimensional gate integration and customized doping, affecting performance uniformity.

[0003] An existing patent discloses a MOSFET with GAA structure (CN118299423A), which includes a silicon substrate, a semiconductor layer including a source region, a drain region, and a nanowire channel, a gate oxide layer, a gate polysilicon fully surrounding the nanowire channel, a source electrode, and a drain electrode. The semiconductor layer and the silicon substrate are integrally formed as a silicon wafer. The existing GAA structure is not optimized for high-voltage applications, and uneven electric field distribution in the drift region can easily cause local breakdown. Moreover, the existing patent uses a traditional polysilicon gate in direct contact with metal, resulting in high gate resistance. SUMMARY

[0004] The present application provides a MOSFET structure with nanosheet all-around gate and a manufacturing process thereof to solve the existing technical problems, solving the problem of uneven electric field distribution in the drift region that can easily cause local breakdown.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a MOSFET structure with nanosheet all-around gate includes a plurality of MOS cells arranged side by side, each MOS cell includes a drain electrode, a semiconductor epitaxial layer, a gate electrode, a gate oxide layer, and a source electrode, the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a P+ layer, and a P well layer, and the gate electrode includes a gate cover layer and a gate nanosheet. The gate nanosheet in each MOS cell has a plurality of gate nanosheets arranged in a horizontal matrix, and the gate nanosheet extends into the interior of the gate cover layer and is in direct contact with it.

[0006] Furthermore, the gate nanosheet is made of P-type polysilicon.

[0007] Furthermore, the gate covering layer is made of titanium nitride or tungsten nitride.

[0008] Furthermore, a P-type guard ring is formed inside the N-drift layer of a single MOS cell and directly below the gate nanosheet by ion implantation; The number and position of the P-type guard rings correspond only to the number and position of the gate nanosheets in the middle region.

[0009] Furthermore, the P-type protection ring also includes a convex protection ring; Among them, the cross-sectional profiles of all convex guard ring regions in a single MOS cell are convex downward in the middle.

[0010] Furthermore, an N+ capping layer is formed inside the N drift layer and below the convex guard ring by ion implantation, and both ends of the N+ capping layer are in direct contact with the P well layer.

[0011] Furthermore, a single MOS cell is provided with a P-type matrix region on both sides of the N substrate layer, and the P-type matrix region is composed of a plurality of P-type gates distributed in an array.

[0012] Furthermore, the top of the P-type gate extends to the inside of the N-drift layer, and the bottom of the P-type gate is in ohmic contact with the drain.

[0013] A manufacturing process for a nanosheet all-around gate MOSFET structure, comprising the following steps: S1, using an N-type substrate as a starting substrate, epitaxially growing an N drift layer and an N well layer thereon, and forming a P well layer and a P+ layer by ion implantation; S2. Depositing and patterning a sacrificial material layer on the epitaxial layer to define a plurality of channel regions distributed in a horizontal matrix; forming a semiconductor material layer that will subsequently serve as a gate nanosheet in the channel region by a selective epitaxial growth or deposition process, and suspending the gate nanosheet above the epitaxial layer by an etching process; S3, growing a gate oxide layer on the entire surface of the suspended semiconductor material layer; then depositing a conductive material for the gate nanosheet to fill and wrap the suspended structure, and removing excess material by an etch-back process; S4. Depositing a gate covering layer material on the structure including the gate nanosheet; patterning the gate covering layer by photolithography and etching processes to ensure that the end of the gate nanosheet extends and is embedded in the patterned gate covering layer to form direct electrical and physical contact therewith; S5. Forming ohmic contact regions of the source and drain on both sides of the gate structure through ion implantation and annealing processes; S6, depositing an interlayer dielectric layer and forming a contact hole by photolithography and etching, and depositing a metal to fill the contact hole, and finally forming a cover layer covering the source, the drain and the gate.

[0014] The MOSFET structure with nanosheet full-surrounding gate and the manufacturing process thereof provided by the application have the following effects compared with the prior art: 1. The three-dimensional embedded contact of the horizontal matrix distributed nanosheet gate and the high conductivity cover layer significantly enhances the channel electrostatic control ability, reduces the gate resistance, realizes higher current driving density and better switching characteristics, and breaks through the physical limitation of the traditional planar device.

[0015] 2. The P-type guard ring selectively arranged in the application cooperates with the convex structure to optimize the drift region electric field distribution, accurately suppresses the electric field peak below the gate nanosheet, improves the device voltage withstand capability while avoiding the additional loss of on-resistance, and solves the local breakdown risk of the high-density nanosheet array.

[0016] 3. The N+ cover layer and the convex guard ring constitute the carrier "shunting-shielding" double mechanism, which accelerates the electron to pass through the high-voltage drift region to reduce the dynamic resistance, eliminates the floating effect by connecting the P-well layer, and significantly improves the switching stability and high-frequency response characteristics of the device.

[0017] 4. The array type P-type matrix area reconstructs the terminal electric field distribution of the device, disperses the edge electric field peak to eliminate the terminal breakdown risk, provides vertical current bypass to reduce the overall on-resistance, and uses the array heat dissipation advantage to improve the reliability under large current working conditions.

[0018] 5. The application realizes high-precision manufacturing of complex three-dimensional structures through the synergistic innovation of sacrificial layer release, full-surrounding gate integration and customized doping through the whole process flow, guarantees the process compatibility, and provides a solution with high density, high voltage resistance and low loss for high-voltage high-power applications. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic diagram of example one in the application; Figure 2 is a schematic diagram of example two in the application; Figure 3 is a schematic diagram of example three in the application; Figure 4 is a schematic diagram of example four in the application; Figure 5 is a schematic diagram of example five in the application.

[0020] In the figure: 1. drain; 2. gate cover layer; 3. gate nanosheet; 4. gate oxide layer; 5. source; 6. N substrate layer; 7. N drift layer; 8. N well layer; 9. P+ layer; 10. P well layer; 11. P-type guard ring; 12. N+ cover layer; 13. P-type matrix region; 1101. convex guard ring. DETAILED DESCRIPTION

[0021] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1 As shown, a manufacturing process of a MOSFET structure with a nanosheet all-around gate includes the following steps: Step 1: Using the N-type substrate layer 6 as the starting substrate, an N-drift layer 7 and an N-well layer 8 are epitaxially grown thereon in sequence, and a P-well layer 10 and a P+ layer 9 are formed by ion implantation. Through sequential epitaxial growth (N-drift layer 7 to N-well layer 8) and selective ion implantation (P-well layer 10 or P+ layer 9), an optimized carrier concentration distribution is formed on the N-substrate 6, providing a low-defect base for the nanosheet channel and laying the foundation for the device's withstand voltage and conduction characteristics.

[0023] Step 2: Deposit and pattern a sacrificial material layer on the epitaxial layer to define several channel areas distributed in a horizontal matrix; through selective epitaxy or deposition process, form a semiconductor material layer that will subsequently serve as the gate nanosheet 3 in the channel area, and suspend it above the epitaxial layer through etching process; the sacrificial layer patterning accurately defines the horizontal matrix channel position, and selective epitaxy / deposition ensures the lattice quality of the nanosheet material (later converted into the gate nanosheet 3); suspended etching releases the channel area, creating physical space for the full-surround gate oxide layer wrapping, breaking through the planar structure limitations.

[0024] Step 3: Grow a gate oxide layer 4 over the entire surface of the suspended semiconductor material layer; then deposit the conductive material of the gate nanosheet 3 to fill and wrap the suspended structure, and remove excess material through a back-etching process; grow a gate oxide layer 4 on the surface of the suspended nanosheet to achieve uniform dielectric isolation; fill and wrap with P-type polysilicon to form the conductive body of the gate nanosheet 3; the back-etching process precisely controls the thickness / morphology of the nanosheet, simultaneously ensuring the channel electrostatic control force and carrier mobility.

[0025] Step 4: Deposit the material of the gate cover layer 2 on the structure containing the gate nanosheet 3; pattern the gate cover layer 2 through photolithography and etching processes to ensure that the end of the gate nanosheet 3 extends and embeds into the patterned gate cover layer 2, forming direct electrical and physical contact with it; the titanium nitride / tungsten nitride gate cover layer 2 deposition provides a highly conductive path; photolithography-etching patterning causes the end of the nanosheet to embed into the cover layer, forming a nanoscale ohmic contact, significantly reducing the gate resistance (>30% lower than traditional interfaces) and having strong process compatibility.

[0026] Step 5: Through ion implantation and annealing processes, ohmic contact regions of the source 5 and drain 1 are formed on both sides of the gate structure. Ion implantation is performed using the gate structure as a mask to ensure that the source 5 / drain 1 is precisely aligned with the channel. The annealing process simultaneously activates impurities and repairs damage to form an ohmic junction with low contact resistance, and completes the electrical activation of customized doping structures such as the guard ring (11 / 1101).

[0027] Step 6: Deposit an interlayer dielectric layer and form contact holes through photolithography and etching. Metal is then deposited to fill the contact holes, ultimately forming the source 5, drain 1, and gate cap layer 2. The interlayer dielectric is flattened to avoid topological differences; contact hole photolithography precisely exposes key nodes in the source / drain / gate cap layer 2; and metal filling forms a low-resistance interconnect network, extending the low-resistance advantage of the gate cap layer and ultimately achieving efficient device performance.

[0028] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a MOSFET structure with a nanosheet-surrounding gate is provided, comprising several mutually parallel MOS cells. Each MOS cell comprises a drain 1, a semiconductor epitaxial layer, a gate, a gate oxide layer 4, and a source 5. The semiconductor epitaxial layer comprises an N substrate layer 6, an N drift layer 7, an N well layer 8, a P+ layer 9, and a P well layer 10. The gate comprises a gate cap layer 2 and a gate nanosheet 3. A plurality of gate nanosheets 3 are present in a single MOS cell, and the plurality of gate nanosheets 3 are arranged in a horizontal matrix. The gate nanosheets 3 extend into and directly contact the gate cap layer 2. The gate nanosheet 3 is made of P-type polysilicon. The gate cap layer 2 is made of either titanium nitride or tungsten nitride.

[0029] A three-dimensional electrical contact is formed by embedding a titanium nitride and tungsten nitride gate cap layer 2 with P-type polysilicon gate nanosheets 3 arranged in a horizontal matrix. The fully encircling nanosheet structure provides stronger channel electrostatic control, thereby enhancing gate control capabilities. The direct contact between the nanosheets and the highly conductive cap layer reduces current path impedance and thus contact resistance. The horizontal matrix arrangement enables higher drive current per unit area, thereby increasing integration density.

[0030] Example 2 As shown in Figure 2 The P-type guard rings 11 are formed in the N-drift layer 7 of the single MOS cell by ion implantation, and are located directly below the gate nanosheet 3. The number and position of the P-type guard rings 11 correspond one-to-one to the number and position of the gate nanosheets 3 in the middle region.

[0031] The P-type guard rings 11 selectively implanted in the N-drift layer 7 directly below the middle gate nanosheet form a local charge balance region. This design of guard ring suppresses the electric field peak below the middle nanosheet, optimizes the electric field distribution, and avoids local breakdown, thereby homogenizing the cell breakdown voltage and improving the withstand voltage capability. Moreover, only for the middle region nanosheet at risk of high electric field, the on-resistance is not excessively sacrificed.

[0032] Embodiment 3 As shown in Figure 3 The P-type guard rings 11 are formed in the N-drift layer 7 of the single MOS cell by ion implantation, and are located directly below the gate nanosheet 3. The number and position of the P-type guard rings 11 correspond one-to-one to the number and position of the gate nanosheets 3 in the middle region. The P-type guard rings 11 further include convex guard rings 1101. The cross-sectional profile of all convex guard ring 1101 regions in the single MOS cell is in the shape of a middle-down convex.

[0033] The P-type guard rings 11 are designed as convex guard rings 1101 that are convex downward, forming a three-dimensional charge compensation structure. The convex profile expands the depletion region volume, more effectively disperses the electric field, and the curved junction depth improves the drift region carrier extraction efficiency to enhance carrier control. This is achieved by adjusting the ion implantation angle / energy without additional masks.

[0034] Embodiment 4 As shown in Figure 4 The P-type guard rings 11 are formed in the N-drift layer 7 of the single MOS cell by ion implantation, and are located directly below the gate nanosheet 3. The number and position of the P-type guard rings 11 correspond one-to-one to the number and position of the gate nanosheets 3 in the middle region. The P-type guard rings 11 further include convex guard rings 1101. The cross-sectional profile of all convex guard ring 1101 regions in the single MOS cell is in the shape of a middle-down convex. An N+ cover layer 12 is formed in the N-drift layer 7 directly below the convex guard ring 1101 by ion implantation, and the two ends of the N+ cover layer 12 are in direct contact with the P-well layer 10.

[0035] N+ cover layer 12 is injected below convex guard ring 1101, and both ends of N+ cover layer 12 are connected with P well layer 10 to form a carrier acceleration channel. N+ cover layer 12 provides a low-resistance path to accelerate electrons to pass through a high-voltage drift region to realize dynamic resistance optimization, and both ends of N+ cover layer 12 are connected with P well layer 10 to avoid floating effect and improve switching stability to suppress parasitic effects; and the design and the convex guard ring constitute a "electric field shielding-carrier dredging" double mechanism.

[0036] Embodiment 5 As shown in Figure 5 P-type matrix region 13 is arranged in a single MOS cell and on both sides of N substrate layer 6, and P-type matrix region 13 is composed of a plurality of P-type gates arranged in an array. The top end of the P-type gate extends to the inside of N drift layer 7, and the bottom end of the P-type gate is in ohmic contact with drain 1.

[0037] Arrayed P-type matrix region 13 is constructed on both sides of N substrate (6), the top end of the P-type gate extends to N drift layer 7, and the bottom end of the P-type gate is connected with drain 1. P-type matrix region 13 disperses the edge electric field and eliminates the risk of terminal breakdown; and the P-type gate provides a vertical current bypass to reduce the overall on-resistance and thus improve the on-state characteristics; and the arrayed distribution avoids local heat concentration and enhances the reliability of large current.

[0038] The above-described embodiments only express several embodiments of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A MOSFET structure with a nanosheet all-around gate, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain (1), a semiconductor epitaxial layer, a gate, a gate oxide layer (4) and a source (5), wherein the semiconductor epitaxial layer comprises an N substrate layer (6), an N drift layer (7), an N well layer (8), a P+ layer (9) and a P well layer (10), and is characterized in that: The gate comprises a gate covering layer (2) and a gate nanosheet (3); There are a plurality of gate nanosheets (3) in a single MOS cell, and the plurality of gate nanosheets (3) are distributed in a horizontal matrix, and the gate nanosheets (3) extend to the interior of the gate covering layer (2) and are in direct contact therewith.

2. The MOSFET structure with a nanosheet all-around gate according to claim 1, wherein: The gate nanosheet (3) is made of P-type polysilicon.

3. The MOSFET structure with a nanosheet-all-around gate according to claim 1, wherein: The gate covering layer (2) is made of titanium nitride or tungsten nitride.

4. The MOSFET structure with a nanosheet-all-around gate according to claim 1, wherein: A P-type guard ring (11) is formed by ion implantation inside the N-drift layer (7) in a single MOS cell and directly below the gate nanosheet (3); The number and position of the P-type protection rings (11) correspond only to the number and position of the gate nanosheets (3) in the middle region.

5. The MOSFET structure with a nanosheet-all-around gate according to claim 4, wherein: The P-type protection ring (11) further includes a convex protection ring (1101); Among them, the cross-sectional profiles of all convex protection ring (1101) regions in a single MOS cell are convex downward in the middle.

6. The MOSFET structure with a nanosheet-all-around gate according to claim 5, wherein: An N+ covering layer (12) is formed inside the N drift layer (7) and below the convex protection ring (1101) by ion implantation, and both ends of the N+ covering layer (12) are in direct contact with the P well layer (10).

7. The MOSFET structure with a nanosheet all-around gate according to claim 1, wherein: A P-type matrix region (13) is provided in a single MOS cell and is located on both sides of the N substrate layer (6). The P-type matrix region (13) is composed of a plurality of P-type gates distributed in an array.

8. The MOSFET structure with a nanosheet all-around gate according to claim 7, wherein: The top of the P-type gate extends to the inside of the N-drift layer (7), and the bottom of the P-type gate is in ohmic contact with the drain (1).

9. A process for manufacturing a nanosheet all-around gate MOSFET structure, characterized in that: The MOSFET structure with a nanosheet all-around gate as claimed in claim 1 is applied, and the manufacturing process of the MOSFET structure with a nanosheet all-around gate comprises the following specific steps: S1, using an N-type substrate layer (6) as a starting substrate, sequentially epitaxially growing an N drift layer (7) and an N well layer (8) thereon, and forming a P well layer (10) and a P+ layer (9) by ion implantation; S2, depositing and patterning a sacrificial material layer on the epitaxial layer to define a plurality of channel regions distributed in a horizontal matrix; forming a semiconductor material layer that will subsequently serve as a gate nanosheet (3) in the channel region through a selective epitaxial or deposition process, and making it suspended above the epitaxial layer through an etching process; S3, growing a gate oxide layer (4) on the entire surface of the suspended semiconductor material layer; then depositing the conductive material of the gate nanosheet (3) to fill and wrap the suspended structure, and removing excess material through an etching back process; S4, depositing a material of a gate covering layer (2) on a structure comprising a gate nanosheet (3); patterning the gate covering layer (2) by photolithography and etching processes, ensuring that the end of the gate nanosheet (3) extends and is embedded in the patterned gate covering layer (2), forming direct electrical and physical contact therewith; S5, forming ohmic contact regions of the source (5) and the drain (1) on both sides of the gate structure through ion implantation and annealing processes; S6, depositing an interlayer dielectric layer and forming a contact hole by photolithography and etching, and depositing metal to fill the contact hole, and finally forming a source electrode (5), a drain electrode (1) and a gate covering layer (2).

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