Board-level packaging structure, packaging method and board-level packaging system

Abstract

The embodiment of the invention provides a board-level packaging structure, a packaging method and a board-level packaging system. The structure comprises a square panel, a plurality of bridging chips, a rewiring layer, a chip operation module and a connection module. A plurality of grooves are formed in the surface of the square panel; the non-functional surfaces of the plurality of bridging chips are arranged in the grooves corresponding to the non-functional surfaces; the rewiring layer is arranged on the surface of the square panel and the functional surface of the bridging chip, and is electrically connected with the bridging chip; the chip operation module and the connection module are arranged on the rewiring layer. Each board-level packaging unit in the structure adopts a large-area square panel, so that the chip carrying capacity, the area utilization rate and the I / O density are remarkably improved, the system performance is remarkably improved, and high computing power integration is realized; the chip operation module realizes high-density interconnection by means of a plurality of bridging chips; and the bridging chip is arranged in the groove, so that the packaging height of the whole packaging structure is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a board-level packaging structure and packaging method, and a board-level packaging system. Background Art

[0002] SoW (System on wafer) integrates a certain number of computing chips onto a whole wafer as a whole to form an ultra-high performance (HPC) chip system.

[0003] SoW uses FO technology to reconstruct the computing chip into a wafer with a glass carrier as the carrier, completes the interconnection between chips through plastic packaging and rewiring, peels off the carrier, and interconnects the power device with the computing chip through flip-chip on the reconstructed wafer to form the entire on-wafer system.

[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.

[0005] In view of the above problems, it is necessary to propose a board-level packaging structure and packaging method, and a board-level packaging system that are reasonably designed and effectively solve the above problems. Summary of the invention

[0006] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a board-level packaging structure and packaging method, and a board-level packaging system.

[0007] The present disclosure provides a board-level packaging structure, including:

[0008] A square panel, wherein a plurality of grooves are arranged on the surface of the square panel;

[0009] A plurality of bridge chips, wherein the non-functional surfaces of the bridge chips are arranged in the grooves corresponding thereto;

[0010] A redistribution layer is disposed on the surface of the square panel and the functional surface of the bridge chip and is electrically connected to the bridge chip;

[0011] The chip operation module and the connection module are both arranged on the redistribution layer and are both electrically connected to the redistribution layer.

[0012] Optionally, there is a gap between the bridge chip and the sidewall of the groove; the redistribution layer includes a dielectric layer and a metal layer; wherein,

[0013] The dielectric layer is disposed on the gap, the surface of the square panel and the functional surface of the bridge chip;

[0014] The dielectric layer located on the surface of the square panel and the functional surface of the bridge chip is provided with an opening, and the metal layer electrically connected to the bridge chip is provided in the opening.

[0015] Optionally, the square panel is a glass panel.

[0016] Optionally, the connection module includes a plurality of connectors arranged on the redistribution layer and cables arranged on the connectors.

[0017] Optionally, the connection module further includes a plurality of photoelectric conversion chips arranged in the redistribution layer and optical fibers arranged in the photoelectric conversion chips.

[0018] Another aspect of the present disclosure provides a board-level packaging method, the packaging method comprising:

[0019] Providing a square panel, wherein a plurality of grooves are arranged on a surface of the square panel;

[0020] Mounting the non-functional surfaces of a plurality of bridge chips in the corresponding grooves;

[0021] forming a redistribution layer on the surface of the square panel and the functional surface of the bridge chip;

[0022] The chip operation module and the connection module are both mounted on the redistribution layer.

[0023] Optionally, mounting the plurality of bridge chips in the corresponding grooves includes:

[0024] Mounting the non-functional surfaces of the plurality of bridge chips on the bottom wall of the corresponding groove, with a gap between the bridge chip and the side wall of the groove;

[0025] The forming of a redistribution layer on the surface of the square panel and the functional surface of the bridge chip comprises:

[0026] forming a dielectric layer in the gap, on the surface of the square panel, and on the functional surface of the bridge chip;

[0027] Patterning the dielectric layer on the surface of the square panel and the functional surface of the bridge chip to form a plurality of openings;

[0028] A metal layer electrically connected to the bridge chip is formed in the opening.

[0029] Optionally, mounting the connection module on the redistribution layer includes:

[0030] Mounting a plurality of connectors provided with cables on the edge area of ​​the redistribution layer; or,

[0031] A plurality of photoelectric conversion chips provided with optical fibers are mounted on the edge area of ​​the redistribution layer.

[0032] Optionally, the square panel is a glass panel.

[0033] Another aspect of the present disclosure provides a board-level packaging system, comprising at least one board-level packaging structure as described above; wherein:

[0034] When the board-level packaging system includes a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the connection module.

[0035] The board-level packaging structure and packaging method, and the board-level packaging system of the embodiments of the present disclosure adopt a large-area square panel to significantly improve the chip capacity, area utilization and I / O density, and significantly improve the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip operation module realizes high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine circuit structure in the RDL; the square panel is provided with multiple grooves, and multiple bridge chips are arranged in the grooves of the corresponding square panel, thereby reducing the packaging height of the entire packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A cross-sectional view of a board-level packaging structure according to an embodiment of the present disclosure;

[0037] Figure 2 A cross-sectional view of a board-level packaging structure of another embodiment of the disclosed embodiments;

[0038] Figure 3 It is a plan view of a board-level packaging structure of another embodiment of the disclosed embodiment;

[0039] Figure 4 A schematic diagram of a process of a board-level packaging method according to another embodiment of the present disclosure;

[0040] Figures 5 to 10 A process schematic diagram of a board-level packaging structure method according to another embodiment of the present disclosure;

[0041] Fig.11 It is a structural schematic diagram of a board-level packaging system of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0043] like Figures 1 to 3 As shown, one aspect of an embodiment of the present disclosure provides a board-level packaging structure 100 , including a square panel 22 , a plurality of bridge chips 24 , a redistribution layer, a chip operation module 32 , and a connection module.

[0044] The surface of the square panel 22 is provided with a plurality of grooves.

[0045] The non-functional surfaces of the plurality of bridge chips 24 are arranged in the corresponding grooves. Specifically, the plurality of grooves are distributed in a matrix on the surface of the square panel 22, wherein the number and distribution of the grooves are not specifically limited in this embodiment and can be selected according to actual needs.

[0046] The redistribution layer is disposed on the surface of the square panel 22 and the functional surface of the bridge chip 24 and is electrically connected to the bridge chip 24. Specifically, the redistribution layer is disposed on the surface of the square panel 22 facing the chip computing module 32 and the bumps on the functional surface of the bridge chip 24.

[0047] The chip operation module 32 and the connection module are both arranged in the redistribution layer and are both electrically connected to the redistribution layer. Specifically, as shown in the figure, in this embodiment, the chip operation module 32 is arranged in the central area of ​​the redistribution layer, and the connection module is arranged in the edge area of ​​the redistribution layer.

[0048] The board-level packaging structure of the disclosed embodiment adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip computing module realizes high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine circuit structure in the RDL; the square panel is provided with multiple grooves, and multiple bridge chips are arranged in the grooves of the corresponding square panel, thereby reducing the packaging height of the entire packaging structure.

[0049] For example, Figure 1 and Figure 2 As shown, there is a gap between the bridge chip 24 and the sidewall of the groove, and the redistribution layer includes a dielectric layer 28 and a metal layer 30. The dielectric layer 28 is disposed in the gap, the surface of the square panel 22, and the functional surface of the bridge chip 24. In other words, the dielectric material fills the gap between the bridge chip 24 and the sidewall of the groove, and is laid on the surface of the square panel 22 and the bumps on the functional surface of the bridge chip 24.

[0050] The dielectric layer 28 located on the surface of the square panel 22 and the functional surface of the bridge chip 24 is provided with an opening, and a metal layer 30 electrically connected to the bridge chip 24 is provided in the opening.

[0051] For example, in this embodiment, the square panel 22 is a glass panel. In the prior art, the carrier is peeled off during the packaging process, and the final packaging structure does not contain the carrier. However, the board-level packaging structure of the disclosed embodiment retains the square glass panel, and the rigidity of the glass panel is used to effectively control the warping of the board-level packaging structure, solve the problem of large-area EMC and chip CTE mismatch, and improve the reliability of the board-level packaging structure.

[0052] For example, Figure 1 As shown, in one embodiment, the connection module includes a plurality of connectors 34 disposed on the redistribution layer and cables 36 disposed on the connectors 34 .

[0053] Specifically, Figure 3 As shown, a plurality of connectors 34 are disposed on the redistribution layer at the edge region of the square panel 22 , and a cable 36 is disposed on each connector 34 .

[0054] For example, Figure 2 As shown, in another embodiment, the connection module further includes a plurality of photoelectric conversion chips 38 disposed in the redistribution layer and optical fibers 40 disposed in the photoelectric conversion chips 38 .

[0055] Specifically, Figure 3 As shown, a plurality of photoelectric conversion chips 38 are disposed on a redistribution layer in an edge region of the square panel 22 , and a cable 36 is disposed on each connector 34 .

[0056] It should be noted that there is no specific limitation on the specific type of the connection module, and it can be selected according to actual needs.

[0057] Exemplarily, the chip operation module 32 may include only a plurality of computing chips, or the chip operation module 32 may include a plurality of computing chips and a plurality of storage chips. Of course, the chip operation module 32 may also include other types of chips. The chips in the chip operation module 32 are electrically interconnected through the redistribution layer and the bridge chip 24.

[0058] Among them, according to the area of ​​the square panel 22, the chip operation modules 32 are distributed in a matrix, which significantly improves the chip capacity, area utilization and I / O density of the entire packaging structure.

[0059] It should be noted that there is no specific limitation on the type and quantity of the chip operation module 32 , and they can be selected according to actual needs.

[0060] For example, Figure 4 As shown, another aspect of the embodiment of the present disclosure provides a board-level packaging method S100, the board-level packaging method S100 comprising:

[0061] S110, providing a square panel, wherein a plurality of grooves are arranged on a surface of the square panel.

[0062] like Figure 5 As shown, a square panel 22 is provided, and a plurality of grooves 44 are arranged on the surface of the square panel 22. The plurality of grooves 44 are distributed in a matrix, wherein the number and distribution of the grooves 44 are not specifically limited in this embodiment and can be selected according to actual needs.

[0063] In this embodiment, preferably, a glass panel is used as the square panel 22. The size of the square panel 22 is not specifically limited and can be selected according to actual needs. The shape of the square panel 22 can be square or rectangular, which is not specifically limited in this embodiment.

[0064] The board-level packaging structure of the disclosed embodiment retains the square glass panel and utilizes the rigidity of the glass panel to effectively control the warping of the board-level packaging structure, thereby solving the problem of large-area EMC and chip CTE mismatch and improving the reliability of the board-level packaging structure.

[0065] S120, mounting the non-functional surfaces of the plurality of bridge chips in the corresponding grooves.

[0066] like Figure 6 As shown, the non-functional surfaces of the plurality of bridge chips 24 are mounted on the bottom walls of the corresponding grooves 44 , wherein a gap is provided between the bridge chips 24 and the side walls of the grooves 44 .

[0067] In this embodiment, a plurality of bridge chips are disposed in the grooves of the corresponding square panels, thereby reducing the packaging height of the entire packaging structure.

[0068] S130 , forming a redistribution layer on the surface of the square panel and the functional surface of the bridge chip.

[0069] like Figure 7 As shown, first, a dielectric layer 28 is formed in the gap between the bridge chip 24 and the sidewall of the groove 44 , the surface of the square panel 22 , and the functional surface of the bridge chip 24 .

[0070] Secondly, if Figure 8 As shown, the dielectric layer 28 located on the surface of the square panel 22 and the functional surface of the bridge chip 24 is patterned by photolithography and etching processes to form a plurality of openings on the dielectric layer 28 .

[0071] Again, if Figure 8 As shown, a metal layer 30 electrically connected to the bridge chip 24 is formed in the opening by electroplating or sputtering process, thereby forming a redistribution layer.

[0072] S140, mounting the chip operation module and the connection module on the redistribution layer.

[0073] like Fig. 9 and Fig.10 As shown, in this embodiment, the chip operation module 32 is mounted on the central area of ​​the redistribution layer, and the connection module is mounted on the edge area of ​​the redistribution layer to form a board-level packaging structure 100.

[0074] like Fig. 9 As shown, in one embodiment, mounting the connection module on the edge area of ​​the redistribution layer includes:

[0075] A plurality of connectors 34 provided with cables 36 are mounted on the edge area of ​​the redistribution layer. In other words, the plurality of connectors 34 are distributed on the edge area of ​​the square panel 22.

[0076] like Fig.10 As shown, in another embodiment, the connection module is mounted on the edge area of ​​the redistribution layer, and further includes:

[0077] A plurality of photoelectric conversion chips 38 provided with optical fibers 40 are mounted on the edge region of the redistribution layer. In other words, the plurality of photoelectric conversion chips 38 are distributed on the edge region of the square panel 22 .

[0078] It should be noted that there is no specific limitation on the specific type of the connection module, and it can be selected according to actual needs.

[0079] The board-level packaging structure method of the embodiment of the present disclosure sets multiple bridge chips in the grooves of the corresponding square panel, thereby reducing the packaging height of the entire packaging structure. The board-level packaging structure formed in the method adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip computing layer realizes high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine circuit structure in RDL.

[0080] like Fig.11 As shown, another aspect of the embodiment of the present disclosure provides a board-level packaging system A, comprising at least one board-level packaging structure 100 as described above. The specific structural features of the board-level packaging structure 100 have been described in detail above and will not be repeated here.

[0081] When the board-level packaging system A includes a plurality of board-level packaging structures 100 , the plurality of board-level packaging structures 100 are electrically connected via a connection module.

[0082] In one embodiment, multiple board-level packaging structures 100 can be electrically connected through cables 36 of connectors 34 to form Fig.11 Board-level packaging system A is shown.

[0083] In another embodiment, multiple board-level packaging structures A can be electrically connected through the optical fiber 40 of the photoelectric conversion chip 38 to form Fig.11 Board-level packaging system A is shown.

[0084] It should be noted that, in this embodiment, there is no specific limitation on the electrical connection method between the multiple board-level packaging structures 100, and it can be selected according to actual needs.

[0085] It should be further explained that there is no specific requirement for the number of board-level packaging structures 100 in the board-level packaging system A, and the number can be selected according to the size of the board-level packaging structure.

[0086] The board-level packaging system of the disclosed embodiment includes at least one board-level packaging structure as described above. The board-level packaging structure adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and achieving high computing power integration; the chip computing layer achieves high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine circuit structure in the RDL.

[0087] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A board-level packaging structure, characterized in that: include: A square panel, wherein a plurality of grooves are arranged on the surface of the square panel; A plurality of bridge chips, wherein the non-functional surfaces of the bridge chips are arranged in the grooves corresponding thereto; A redistribution layer is disposed on the surface of the square panel and the functional surface of the bridge chip and is electrically connected to the bridge chip; The chip operation module and the connection module are both arranged on the redistribution layer and are both electrically connected to the redistribution layer.

2. The board-level packaging structure according to claim 1, characterized in that: There is a gap between the bridge chip and the sidewall of the groove; the redistribution layer includes a dielectric layer and a metal layer; wherein, The dielectric layer is disposed on the gap, the surface of the square panel and the functional surface of the bridge chip; The dielectric layer located on the surface of the square panel and the functional surface of the bridge chip is provided with an opening, and the metal layer electrically connected to the bridge chip is provided in the opening.

3. The board-level packaging structure according to claim 1, characterized in that: The square panel is a glass panel.

4. The board-level packaging structure according to any one of claims 1 to 3, characterized in that: The connection module includes a plurality of connectors arranged on the redistribution layer and cables arranged on the connectors.

5. The board-level packaging structure according to any one of claims 1 to 3, characterized in that: The connection module further includes a plurality of photoelectric conversion chips arranged on the redistribution layer and optical fibers arranged on the photoelectric conversion chips.

6. A board-level packaging method, characterized in that: The packaging method comprises: Providing a square panel, wherein a plurality of grooves are arranged on a surface of the square panel; Mounting the non-functional surfaces of a plurality of bridge chips in the corresponding grooves; forming a redistribution layer on the surface of the square panel and the functional surface of the bridge chip; The chip operation module and the connection module are both mounted on the redistribution layer.

7. The board-level packaging method according to claim 6, characterized in that: The step of mounting a plurality of bridge chips in the corresponding grooves includes: Mounting the non-functional surfaces of the plurality of bridge chips on the bottom wall of the corresponding groove, with a gap between the bridge chip and the side wall of the groove; The redistribution layer is formed on the surface of the square panel and the functional surface of the bridge chip, comprising: forming a dielectric layer in the gap, on the surface of the square panel, and on the functional surface of the bridge chip; Patterning the dielectric layer on the surface of the square panel and the functional surface of the bridge chip to form a plurality of openings; A metal layer electrically connected to the bridge chip is formed in the opening.

8. The board-level packaging method according to claim 6, characterized in that: Mounting the connection module on the redistribution layer includes: Mounting a plurality of connectors provided with cables on the edge area of ​​the redistribution layer; or, A plurality of photoelectric conversion chips provided with optical fibers are mounted on the edge area of ​​the redistribution layer.

9. The board-level packaging method according to any one of claims 6 to 8, characterized in that: The square panel is a glass panel.

10. A board-level packaging system, characterized in that: Comprising at least one board-level packaging structure according to any one of claims 1 to 5; wherein, When the board-level packaging system includes a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the connection module.

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