Chip packaging structure and electronic equipment

Abstract

The invention discloses a chip packaging structure and electronic equipment, and belongs to the technical field of semiconductors. The chip packaging structure comprises a substrate which is provided with a first side and a second side which are oppositely arranged, the first side of the substrate is provided with a first groove, and the second side of the substrate is provided with a second groove; the first chip is located in the first groove; the metal interconnection layer is positioned on the first side of the substrate and is electrically connected with the first chip; the through hole structure penetrates through the substrate and is electrically connected with the metal interconnection layer; the second chip is positioned on the second side of the substrate and is electrically connected with the through hole structure; the capacitor is located in the second groove and electrically connected with a power line of the second chip, and the power line comprises a line transmitting power to the second chip through the metal interconnection layer and the through hole structure. The problem of power supply integrity can be solved, high-speed data transmission is realized, the packaging design difficulty is reduced, and the system integration degree is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure and an electronic device. Background Art

[0002] As the performance requirements of smartphones continue to increase, the speed of chip communication interfaces in smartphones continues to increase, and the requirements for power integrity are becoming increasingly higher.

[0003] The chip packaging structure in the related art consists of two chips, one above and one below, which are interconnected through TMV (Through Molding Via) in the molding material around the lower chip. In order to solve the problem of power integrity, the related art optimizes the power supply by optimizing the power routing of the package, increasing the number of power through holes and increasing the number of power TMVs. However, there are many modules and interfaces integrated in the mobile phone SoC (System on Chip), and the packaging design of this type of optimization method is difficult and the optimization capability is limited. The related art also uses back-mounted capacitors to optimize the power supply. However, back-mounted capacitors will occupy the welding part resources of the chip, and the routing path between the back-mounted capacitors and the upper chip is long, the routing parasitic value is high, and the power optimization effect is poor. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a chip packaging structure and electronic equipment that can solve the power integrity problem, achieve high-speed data transmission, reduce the difficulty of packaging design, and improve system integration.

[0005] The present application provides a chip packaging structure, including:

[0006] A substrate having a first side and a second side arranged opposite to each other, wherein the first side of the substrate has a first groove, and the second side of the substrate has a second groove;

[0007] A first chip, located in the first groove;

[0008] a metal interconnection layer, located on the first side of the substrate and electrically connected to the first chip;

[0009] A through-hole structure, penetrating the substrate and electrically connected to the metal interconnection layer;

[0010] A second chip is located on the second side of the substrate and is electrically connected to the through-hole structure;

[0011] The capacitor is located in the second groove and is electrically connected to the power supply wiring of the second chip, wherein the power supply wiring includes a wiring that transmits power to the second chip through the metal interconnection layer and the through-hole structure.

[0012] According to an embodiment of the present application, the chip packaging structure further includes:

[0013] A connecting line is located between the substrate and the second chip, and the second chip is electrically connected to the through-hole structure through the connecting line; the power line includes a line that transmits power to the second chip through the metal interconnection layer, the through-hole structure and the connecting line, and the capacitor is electrically connected to the power line through the connecting line.

[0014] According to an embodiment of the present application, the chip packaging structure further includes:

[0015] The first welding portion is located on a side of the metal interconnect layer away from the substrate and is electrically connected to the metal interconnect layer; the power supply line includes a line that transmits power to the second chip through the first welding portion, the metal interconnect layer, the through-hole structure and the connecting line.

[0016] According to an embodiment of the present application, the chip packaging structure further includes:

[0017] A second welding portion is located between the connecting wire and the second chip, and the second chip is electrically connected to the connecting wire through the second welding portion; the power supply wire includes a wire that transmits power to the second chip through the first welding portion, the metal interconnection layer, the through-hole structure, the connecting wire and the second welding portion.

[0018] According to an embodiment of the present application, the capacitor is arranged close to the power supply line.

[0019] According to an embodiment of the present application, the capacitor is disposed close to the through-hole structure in the power supply line.

[0020] According to an embodiment of the present application, the capacitor includes a deep trench capacitor.

[0021] According to one embodiment of the present application, the substrate includes a silicon substrate or a glass substrate.

[0022] According to an embodiment of the present application, the first chip includes a processing chip, and the second chip includes a memory chip.

[0023] The present application provides an electronic device, comprising an external power supply and a chip packaging structure as described in any one of the above embodiments, wherein the external power supply is connected to a power supply line in the chip packaging structure.

[0024] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0025] By setting a capacitor in the substrate, the capacitor is electrically connected to the power line of the second chip, the impedance of the power line of the second chip is reduced, the power integrity problem of the second chip is solved, the normal operation of the high-speed communication interface of the second chip is ensured, and high-speed and stable data transmission is achieved without affecting the welding resources of the first chip and the second chip, and there is no need to optimize the power line and through-hole layout of the package, thereby reducing the difficulty of package design; the capacitor is located on the side of the substrate close to the second chip, the routing path between the capacitor and the second chip is reduced, the routing parasitics is low, and the power optimization effect is improved; the first chip and the capacitor are both located in the groove of the substrate, thereby improving the integration of the system.

[0026] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0028] Figure 1 It is a structural schematic diagram of the chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] Smartphones are widely used intelligent device terminals in modern science and technology society, playing an important role in communication, information acquisition, entertainment, learning and work, health and life assistant. The core chip in smartphones is the mobile phone processor SoC. As people's demand for smartphone photography, games, artificial intelligence applications, power saving and low prices continues to increase, smartphone processor SoC is also constantly developing in the direction of high integration, high performance, high storage, low power consumption and low cost. Under this trend, the chip capacity of smartphones is getting higher and higher, and the speed of chip communication interface is getting faster and faster.

[0031] In the related art, the chip packaging structure in a smartphone consists of two chips, one above and one below (e.g., the upper chip is a DRAM chip and the lower chip is a logic chip). The two chips are interconnected through the TMV in the molding compound around the lower chip, and a metal interconnection layer connected to the TMV is provided at the bottom of the lower chip, and a welding portion is provided at the bottom of the metal interconnection layer to achieve electrical interconnection between external devices and the two chips.

[0032] As the speed requirements for the communication interface of the chip in the smartphone continue to increase, according to the standard requirements of JEDEC (Solid State Technology Association), there will be more stringent impedance requirements for the power supply related to the high-speed communication interface (such as the memory read interface of the DRAM chip). This poses a great power integrity design challenge to the current smartphone chip packaging structure. Solving the power integrity problem of the high-speed communication interface can ensure the normal operation of the high-speed communication interface, maintain the data transmission speed, and make products that better meet market demand.

[0033] Related technologies solve the problem of power integrity by optimizing package power routing, increasing the number of power vias, and increasing the number of power via structures (such as TMVs in molding compounds), and optimizing the power supply to improve the stability of high-speed data transmission of the chip communication interface. However, smartphone processor SoCs integrate many modules and interfaces, and routing resources are tight, leaving limited room for optimization of high-speed communication interfaces. The increase in the speed of the chip communication interface will also increase the demand for DQ (data queue) signals (such as dual channels and 128 bits, etc.), and the area resources left for the chip welding part, via structure and power routing will decrease. Therefore, methods such as increasing the package power routing, the number of power vias, and the number of power via structures have limited optimization capabilities.

[0034] Related technologies also use the method of attaching capacitors (i.e., back-attached capacitors) to the soldering parts at the bottom of the metal interconnect layer for power optimization. However, back-attached capacitors will occupy soldering part resources, reduce the number of input and output of the system, or reduce the number of soldering parts of other power supplies, and the routing path between the back-attached capacitor and the upper chip is long, and its routing parasitic value is high, the parasitic capacitance is large, and the power optimization effect is poor. Moreover, the back-attached capacitor is a passive capacitor, which increases the number of materials and costs. Moreover, this method of back-attached capacitors has fewer optional capacitance values ​​and needs to be customized based on the upper chip, and the customization cost is high.

[0035] Based on this, an embodiment of the present application provides a chip packaging structure and an electronic device.

[0036] The chip packaging structure and electronic device provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0037] Figure 1 A schematic diagram of the chip packaging structure provided in an embodiment of the present application.

[0038] like Figure 1 As shown, the chip packaging structure provided by the embodiment of the present application includes a substrate 1, the substrate 1 has a first side and a second side arranged opposite to each other, the first side of the substrate 1 has a first groove 11, and the second side of the substrate 1 has a second groove 12. For example, the first side of the substrate 1 can be the bottom of the substrate 1, the first groove 11 is located at the bottom of the substrate 1, and the first groove 11 can extend from the bottom surface of the substrate 1 to the inside of the substrate 1 along the longitudinal direction. The second side of the substrate 1 can be the top of the substrate 1, the second groove 12 is located at the top of the substrate 1, and the second groove 12 can extend from the top surface of the substrate 1 to the inside of the substrate 1 along the longitudinal direction. The first groove 11 and the second groove 12 can be spaced in the substrate 1 along the transverse direction. The transverse direction and the longitudinal direction are perpendicular to each other.

[0039] The chip packaging structure may further include a first chip 2, and the first chip 2 is located in the first groove 11. The shapes and sizes of the first chip 2 and the first groove 11 may match each other, so that the first chip 2 can be located in the first groove 11. The surface of the first side of the first chip 2 may not exceed the surface of the first side of the substrate 1, and the first side of the first chip 2 and the first side of the substrate 1 are located on the same side.

[0040] The chip packaging structure may further include a metal interconnection layer 3, which is located on the first side of the substrate 1 and is electrically connected to the first chip 2. Figure 1 As shown, the metal interconnection layer 3 covers the substrate 1 and the first chip 2. In some embodiments, the metal interconnection layer 3 may include a dielectric layer 31 and an interconnection line 32. The interconnection line 32 is located in the dielectric layer 31 and vertically penetrates the dielectric layer 31, and is electrically connected to the first chip 2. The first chip 2 can realize signal and data transmission with external devices through the interconnection line 32. The metal interconnection layer 3 may include an RDL (Redistribution Layer) and the like. The material of the dielectric layer 31 may include an organic material and the like. The material of the interconnection line 32 may include a metal (e.g., copper) and the like.

[0041] The chip packaging structure may further include a through-hole structure 4, which penetrates the substrate 1 and is electrically connected to the metal interconnection layer 3. Figure 1 As shown, the through-hole structure 4 penetrates the substrate 1 in the longitudinal direction, the metal interconnection layer 3 covers the bottom of the through-hole structure 4, and the bottom of the through-hole structure 4 is connected to the interconnection trace 32 in the metal interconnection layer 3. In some embodiments, the chip packaging structure may include one or more through-hole structures 4, each through-hole structure 4 penetrates the substrate 1, and each through-hole structure 4 is respectively connected to the interconnection trace 32 in the metal interconnection layer 3. Multiple through-hole structures 4 are located in the substrate 1 at intervals in the lateral direction. The first groove 11, the second groove 12 and the through-hole structure 4 can be located in the substrate 1 at intervals in the lateral direction.

[0042] The chip packaging structure may further include a second chip 7, which is located on the second side of the substrate 1 and is electrically connected to the through-hole structure 4. Figure 1 As shown, the second chip 7 is located above the substrate 1. The second chip 7 can be electrically connected to the interconnection traces 32 in the metal interconnection layer 3 through the through-hole structure 4. The second chip 7 can transmit signals and data with the first chip 2 or external devices through the through-hole structure 4 and the interconnection traces 32 in the metal interconnection layer 3.

[0043] In some embodiments, the second chip 7 may include a high-speed communication interface, which is an interface for realizing high-speed data transmission. The high-speed communication interface of the second chip 7 may be electrically connected to the through-hole structure 4, so that the second chip 7 can perform high-speed data transmission with the first chip 2 or an external device through the high-speed communication interface, the through-hole structure 4 and the metal interconnection layer 3.

[0044] The chip packaging structure may further include a capacitor 5 , which is located in the second groove 12 and electrically connected to a power line of the second chip 7 . The power line includes a line that transmits power to the second chip 7 via the metal interconnection layer 3 and the through-hole structure 4 .

[0045] One end of the power supply line of the second chip 7 is connected to the external power supply, and the other end of the power supply line is connected to the second chip 7, and the external power supply can supply power to the second chip 7 through the power supply line. In some embodiments, the other end of the power supply line is connected to the high-speed communication interface of the second chip 7, and the external power supply can supply power to the high-speed communication interface of the second chip 7 through the power supply line. The power supply line includes a line segment passing through the metal interconnection layer 3 and the through-hole structure 4, that is, the external power supply can supply power to the second chip 7 through the metal interconnection layer 3 and the through-hole structure 4.

[0046] It should be noted that the metal interconnection layer 3 has multiple interconnection lines 32, and the number of through-hole structures 4 is multiple. The connection between the multiple interconnection lines 32 and the multiple through-hole structures 4 can constitute lines for transmitting different signals and data, and is not limited to power lines.

[0047] The shapes and sizes of the capacitor 5 and the second groove 12 may match each other so that the capacitor 5 can be located in the second groove 12. The surface of the second side of the capacitor 5 may not exceed the surface of the second side of the substrate 1, and the second side of the capacitor 5 and the second side of the substrate 1 are located on the same side.

[0048] Capacitor 5 may include two electrode plates and a dielectric between the two electrode plates. The electrode plates are used to accumulate charges. The material of the electrode plates may include one or more combinations of polysilicon and metals (e.g., copper, titanium, etc.). The dielectric between the two electrode plates may hinder the movement of charges, causing the charges to accumulate on the electrode plates. The material of the dielectric may include silicon dioxide, etc. The capacitance value of capacitor 5 may be set according to the requirements of the actual application.

[0049] In this embodiment, a second groove 12 is provided on the top of the substrate 1, and a capacitor 5 is provided in the second groove 12. The capacitor 5 has a capacitor effect. The capacitor 5 is connected to the power supply line of the second chip 7, which can reduce the impedance of the power supply line of the second chip 7, improve the stability and reliability of the power supply line, solve the power supply integrity problem of the second chip 7, ensure the normal operation of the high-speed communication interface in the second chip 7, and realize high-speed and stable transmission of data. Moreover, the present embodiment reduces the impedance of the power supply line by providing the capacitor 5, and there is no need to optimize the power supply line and through-hole layout of the package, thereby reducing the difficulty of package design. Moreover, the capacitor 5 is provided in the second groove 12 on the side of the substrate 1 close to the second chip 7, that is, the capacitor 5 is provided close to the second chip 7, so that the wiring path between the capacitor 5 and the second chip 7 is reduced, the wiring parasitic is reduced, and the optimization effect on the power supply is improved. In addition, the first chip 2 and the capacitor 5 are both located in the groove of the substrate 1, saving the space of the chip packaging structure and improving the system integration.

[0050] In some embodiments, the chip packaging structure further includes a connecting wire 6, the connecting wire 6 is located between the substrate 1 and the second chip 7, and the second chip 7 is electrically connected to the through-hole structure 4 through the connecting wire 6. Figure 1 As shown, the connecting wire 6 covers the top of the through-hole structure 4 and is connected to the top of the through-hole structure 4, and the second chip 7 is electrically connected to the connecting wire 6, so that the second chip 7 is electrically connected to the through-hole structure 4 through the connecting wire 6. The material of the connecting wire 6 may include metal (such as copper) and the like.

[0051] The power supply line includes a line that transmits power to the second chip 7 through the metal interconnection layer 3, the through-hole structure 4 and the connecting line 6, and the capacitor 5 is electrically connected to the power supply line through the connecting line 6. The power supply line includes a line segment that passes through the metal interconnection layer 3, the through-hole structure 4 and the connecting line 6, that is, an external power supply can supply power to the second chip 7 through the metal interconnection layer 3, the through-hole structure 4 and the connecting line 6. The connecting line 6 also covers the top of the capacitor 5 and is connected to the capacitor 5, so that the capacitor 5 is electrically connected to the power supply line through the connecting line 6.

[0052] In some embodiments, the chip packaging structure further includes a first welding portion 8, which is located on a side of the metal interconnection layer 3 away from the substrate 1 and is electrically connected to the metal interconnection layer 3. Figure 1As shown, the chip packaging structure may include a plurality of first welding portions 8. The plurality of first welding portions 8 are spaced laterally below the metal interconnect layer 3. Each first welding portion 8 is electrically connected to an interconnection trace 32 in the metal interconnect layer 3. Different first welding portions 8 may be connected to different external devices, so that different external devices may transmit signals and data with the first chip 2 or the second chip 7. The first welding portion 8 may include a BGA (Ball Grid Array).

[0053] The power supply line includes a line that transmits power to the second chip 7 through the first welding portion 8, the metal interconnection layer 3, the through-hole structure 4 and the connecting line 6. The power supply line includes a line segment passing through the first welding portion 8, the metal interconnection layer 3, the through-hole structure 4 and the connecting line 6, that is, the external power supply can supply power to the second chip 7 through the first welding portion 8, the metal interconnection layer 3, the through-hole structure 4 and the connecting line 6. In some embodiments, the external power supply can be connected to the power supply line through the first welding portion 8.

[0054] In some embodiments, the chip packaging structure further includes a second soldering portion 9, which is located between the connecting wire 6 and the second chip 7, and the second chip 7 is electrically connected to the connecting wire 6 through the second soldering portion 9. Figure 1 As shown, the second soldering portion 9 is connected to the second chip 7 and the connecting wire 6 respectively, so that the second chip 7 can be electrically connected to the through-hole structure 4 through the second soldering portion 9 and the connecting wire 6. The second soldering portion 9 may include a BGA.

[0055] The power supply line includes a line that transmits power to the second chip 7 through the first welding part 8, the metal interconnection layer 3, the through-hole structure 4, the connecting line 6 and the second welding part 9. The power supply line includes a line segment passing through the first welding part 8, the metal interconnection layer 3, the through-hole structure 4, the connecting line 6 and the second welding part 9, that is, the external power supply can supply power to the second chip 7 through the first welding part 8, the metal interconnection layer 3, the through-hole structure 4, the connecting line 6 and the second welding part 9.

[0056] In some embodiments, the capacitor 5 is disposed close to the power supply line. The distance between the capacitor 5 and the power supply line of the second chip 7 is close, that is, the wiring path between the capacitor 5 and the power supply line of the second chip 7 is small, and the wiring parasitics are low, which further improves the optimization effect of the related power supply of the high-speed communication interface of the second chip 7.

[0057] In some embodiments, the capacitor 5 is disposed close to the through-hole structure 4 in the power supply line. The chip packaging structure may include a plurality of through-hole structures 4, and the plurality of through-hole structures 4 may be located on opposite sides of the first chip 2. Figure 1As shown, at least one through-hole structure 4 is respectively provided on the left and right sides of the first chip 2 in the horizontal direction. The plurality of through-hole structures 4 include a through-hole structure 4 in the power supply line. The capacitor 5 is laterally spaced apart from the through-hole structure 4 in the substrate 1. The capacitor 5 can be laterally spaced apart between the through-hole structure 4 in the power supply line and the first chip 2 to avoid increasing the lateral width of the chip packaging structure.

[0058] Capacitor 5 is arranged close to the through-hole structure 4 in the power line, so that capacitor 5 is arranged close to the power line, shortening the distance between capacitor 5 and the power line of the second chip 7, further reducing the parasitic capacitance of the power line, further reducing the impedance of the power line of the high-speed communication interface, and further improving the effect of power optimization.

[0059] In some embodiments, the capacitor 5 includes a deep trench capacitor. The deep trench capacitor can be formed by etching a second groove 12 in the substrate 1 and filling the second groove 12 with a material. In this embodiment, the deep trench capacitor is integrated into the substrate 1, and no other passive capacitor is required, which can reduce the number of materials and costs, and there is no need to customize the capacitor for the second chip 7, further reducing costs.

[0060] In some embodiments, the substrate 1 includes a silicon substrate or a glass substrate. The substrate 1 is used to protect the first chip 2 and serves as a carrier of the through-hole structure 4 and the capacitor 5. Circuit traces are set on the top and bottom of the substrate 1 along the longitudinal direction. When the substrate 1 is a silicon substrate, the through-hole structure 4 is TSV (Through silicon via). Compared with the related art using molding compound as the material of the substrate 1, the present embodiment uses silicon or glass as the material of the substrate 1, which helps to improve the process accuracy of the capacitor 5 (the accuracy can reach hundreds of nanometers).

[0061] In some embodiments, the first chip 2 includes a processing chip. The processing chip is used for data calculation and signal processing of the system. The processing chip may include a logic (Logic, programmable logic device) chip, etc.

[0062] In some embodiments, the second chip 7 includes a memory chip. The memory chip is used for storing and reading data of the system. The memory chip may include a DRAM (Dynamic Random Access Memory) chip, etc.

[0063] For example, in the chip packaging structure of a smartphone, the first chip 2 is a logic chip, the second chip 7 is a DRAM chip, and the high-speed communication interface (i.e., the memory read interface of the DRAM chip) adopts the LPDDR5 / 5X (a memory read interface standard established by JEDEC) protocol. The relevant power supplies of the LPDDR interface include VDDQ (powering the input and output circuits) and VDD1 (powering the core circuits of the memory). According to the requirements of the JEDEC standard, when the communication speed is increased to 8533MHz, the PDN (Power Distribution Network) impedance requirements for VDD2H (powering the core circuits of the memory) and VDDQ are 40mOhm@10MHz and 80mOhm@20MHz, respectively, which places high demands on power integrity.

[0064] In order to solve the power integrity problem of the LPDDR5 / 5X interface, to ensure the normal operation of the LPDDR5 / 5X interface, to maintain the data transmission speed, and to make products that better meet market demand, this embodiment sets a capacitor 5 in the second groove 12 on the top of the substrate 1, and electrically connects the capacitor 5 to the power line of the LPDDR5 / 5X interface of the DRAM chip by connecting the wiring 6, and uses the capacitance effect of the capacitor 5 to reduce the PDN impedance of VDDQ and VDD1 to solve the power integrity problem of the LPDDR5 / 5X interface of the DRAM chip, ensure the normal operation of the LPDDR5 / 5X interface, and realize the normal transmission of data at a speed of 8533MHz. Moreover, the capacitor 5 is located in the second groove 12 on the side of the substrate 1 close to the DRAM chip, shortening the wiring path between the capacitor 5 and the DRAM chip, reducing wiring parasitics, and improving the power optimization effect of the capacitor 5 on the LPDDR5 / 5X interface of the DRAM chip. Moreover, capacitor 5 may include deep trench capacitors. Deep trench capacitors are applied to the power routing of the LPDDR5 / 5X interface without the introduction of other passive capacitors, which can reduce the number and cost of packaging materials and does not require customization of the DRAM chip or capacitor 5, which can further reduce the process cost. The deep trench capacitors have small parasitic capacitance and can reduce the impedance of the power routing with a smaller capacitance value, further improving the optimization of the related power supply of the LPDDR5 / 5X interface of the DRAM chip. The deep trench capacitors are applied to the power network of the LPDDR5 / 5X interface, which expands the application field of the deep trench capacitors.

[0065] The chip types of the first chip 2 and the second chip 7 are not specifically limited. This embodiment can be applied not only to the chip packaging structure of DRAM chips and logic chips to optimize the power supply of LPDDR5 / 5X interfaces, but also to the chip packaging structure of other types of chips to optimize the power supply of other high-speed communication interfaces.

[0066] In summary, according to the chip packaging structure provided by the embodiment of the present application, by setting the second groove 12 on the top of the substrate 1, the capacitor 5 is set in the second groove 12, and the capacitor 5 is electrically connected to the power supply line of the high-speed communication interface of the second chip 7 through the connecting line 6. Through the capacitance effect of the capacitor 5, the impedance of the power supply line of the second chip 7 is reduced, the power integrity problem of the second chip 7 is solved, the normal operation of the high-speed communication interface is ensured, and the high-speed transmission of data is realized. Moreover, the present embodiment reduces the impedance of the power supply line by setting the capacitor 5, and there is no need to optimize the power supply line and through-hole layout of the package, thereby reducing the difficulty of package design. Moreover, the capacitor 5 is arranged in the second groove 12 of the substrate 1, which does not affect the resources of the first welding part 8 and the second welding part 9 of the first chip 2 and the second chip 7, and saves the space of the chip packaging structure. The capacitor 5 is arranged on one side close to the second chip 7, and the wiring path between the capacitor 5 and the second chip 7 is reduced, and the wiring parasitics are reduced, further improving the optimization effect of the power supply. When the capacitor 5 is a deep groove capacitor, the capacitor 5 is integrated in the substrate 1, and there is no need to introduce other passive capacitors, thereby reducing the number of materials and process costs.

[0067] Accordingly, an embodiment of the present application further provides an electronic device, including an external power supply and a chip packaging structure, wherein the external power supply is connected to a power supply line in the chip packaging structure. The chip packaging structure may be the chip packaging structure in the above embodiment, which will not be described in detail here.

[0068] The external power source may be connected to the first soldering portion 8 in the chip packaging structure, so that the external power source is connected to the power supply wiring of the second chip 7 through the first soldering portion 8. The external power source may supply power to the second chip 7 through the power supply wiring.

[0069] It should be noted that the first welding portion 8 in the chip packaging structure can also be connected to other external devices, so that the external devices can transmit signals and data with the first chip 2 and the second chip 7 in the chip packaging structure.

[0070] In some embodiments, the electronic device may include a smart phone, and the chip packaging structure in the above embodiments may be a packaging structure of a processor chip in the smart phone.

[0071] In some embodiments, the electronic device may also include computers (such as tablet computers, desktop computers, and laptop computers, etc.) and automotive electronic devices, etc., which are not limited here.

[0072] In summary, according to the electronic device provided by the embodiment of the present application, a capacitor 5 can be arranged in the second groove 12 of the chip packaging structure, and the capacitor 5 is electrically connected to the power supply line of the second chip 7 through the connecting line 6. The capacitor 5 has a capacitor effect, and the capacitor 5 is connected to the power supply line of the second chip 7. The capacitor 5 reduces the impedance of the power supply line related to the second chip 7, improves the stability and reliability of the power supply line, solves the power supply integrity problem of the second chip 7, ensures the normal operation of the high-speed communication interface, and realizes high-speed and stable transmission of data. Moreover, the present embodiment reduces the impedance of the power supply line by arranging the capacitor 5, and there is no need to optimize the power supply line and the through-hole layout of the package, thereby reducing the difficulty of package design. The capacitor 5 is arranged in the second groove 12 on the side of the substrate 1 close to the second chip 7, that is, the capacitor 5 is arranged close to the second chip 7, so that the wiring path between the capacitor 5 and the second chip 7 is reduced, the wiring parasitic is reduced, and the optimization effect on the power supply is further improved, and the welding part resources of the first chip 2 and the second chip 7 are not affected. In addition, the first chip 2 and the capacitor 5 of the chip packaging structure are both located in the groove of the substrate 1, saving the space of the chip packaging structure and improving the system integration of the electronic device.

[0073] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0074] In the description of the present application, “plurality” means two or more.

[0075] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0076] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: A substrate having a first side and a second side arranged opposite to each other, wherein the first side of the substrate has a first groove, and the second side of the substrate has a second groove; A first chip, located in the first groove; a metal interconnection layer, located on the first side of the substrate and electrically connected to the first chip; A through-hole structure, penetrating the substrate and electrically connected to the metal interconnection layer; A second chip is located on the second side of the substrate and is electrically connected to the through-hole structure; The capacitor is located in the second groove and is electrically connected to the power supply wiring of the second chip, wherein the power supply wiring includes a wiring that transmits power to the second chip through the metal interconnection layer and the through-hole structure.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes: A connecting line is located between the substrate and the second chip, and the second chip is electrically connected to the through-hole structure through the connecting line; the power line includes a line that transmits power to the second chip through the metal interconnection layer, the through-hole structure and the connecting line, and the capacitor is electrically connected to the power line through the connecting line.

3. The chip packaging structure according to claim 2, characterized in that: The chip packaging structure further includes: The first welding portion is located on a side of the metal interconnect layer away from the substrate and is electrically connected to the metal interconnect layer; the power supply line includes a line that transmits power to the second chip through the first welding portion, the metal interconnect layer, the through-hole structure and the connecting line.

4. The chip packaging structure according to claim 3, characterized in that: The chip packaging structure further includes: A second welding portion is located between the connecting wire and the second chip, and the second chip is electrically connected to the connecting wire through the second welding portion; the power supply wire includes a wire that transmits power to the second chip through the first welding portion, the metal interconnection layer, the through-hole structure, the connecting wire and the second welding portion.

5. The chip packaging structure according to claim 1, characterized in that: The capacitor is arranged close to the power supply line.

6. The chip packaging structure according to claim 5, characterized in that: The capacitor is disposed close to the through-hole structure in the power supply line.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The capacitor comprises a deep trench capacitor.

8. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The substrate includes a silicon substrate or a glass substrate.

9. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The first chip includes a processing chip, and the second chip includes a memory chip.

10. An electronic device, characterized in that: It comprises an external power supply and a chip packaging structure as claimed in any one of claims 1 to 9, wherein the external power supply is connected to a power supply line in the chip packaging structure.

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