A board-level packaging structure and packaging method, and a board-level packaging system
By using a large-area square panel design and high-density interconnect technology, the performance limitations of SoW systems have been solved, achieving high computing power integration and high-density interconnect, thereby increasing chip capacity and system performance.
Patent Information
- Application Number
- CN202411896277.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2044-12-20
AI Technical Summary
The overall performance of a single SoW system is limited by wafer size, and existing technologies cannot effectively improve chip capacity and system performance.
It adopts a large-area square panel design, including bridging chips, molding layer, rewiring layer, chip computing layer and connection module. High-density interconnection is achieved through multiple bridging chips, and the glass panel is used to improve structural reliability and eliminate the reliance on fine circuit structure.
It significantly improves chip capacity, area utilization, and I/O density, achieving high computing power integration, solving the problem of limited performance of a single SoW system, and realizing high-density interconnection.
Smart Images
Figure CN119725319B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a board-level packaging structure and packaging method, and a board-level packaging system. BACKGROUND
[0002] SoW (System on wafer) is to integrate a certain number of computing chips onto a whole wafer as a whole to form a HPC (High Performance Computing) chip system.
[0003] SoW is to reconfigure computing chips into a wafer by using FO technology with a glass carrier as a carrier, to complete interconnection between chips through plastic packaging and re-wiring, to peel off the carrier, and to form the whole SoW system by interconnecting power devices with computing chips in a flip-chip manner on the reconfigured wafer.
[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.
[0005] In view of the above problems, it is necessary to provide a board-level packaging structure and packaging method, and a board-level packaging system which are reasonable in design and effective in solving the above problems. SUMMARY
[0006] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provide a board-level packaging structure and packaging method, and a board-level packaging system.
[0007] An aspect of the embodiment of the present disclosure provides a board-level packaging structure, comprising:
[0008] a square panel;
[0009] a plurality of bridge chips arranged on the surface of the square panel;
[0010] a plastic packaging layer arranged on the surface of the square panel and wrapping the plurality of bridge chips;
[0011] a re-wiring layer arranged on the surface of the plastic packaging layer away from the square panel and the bump surface of the bridge chip, and electrically connected with the bridge chip;
[0012] a chip operation layer and a connection module, both arranged on the re-wiring layer and electrically connected with the re-wiring layer.
[0013] Optionally, a plurality of data relay chips are arranged on the surface of the square panel and wrapped in the plastic packaging layer.
[0014] Optionally, the square panel adopts a glass panel.
[0015] Optionally, the connection module comprises a plurality of connectors arranged on the rewiring layer and cables arranged on the connectors.
[0016] Optionally, the connection module further comprises a plurality of photoelectric conversion chips arranged on the rewiring layer and optical fibers arranged on the photoelectric conversion chips.
[0017] Another aspect of the embodiments of the present disclosure provides a board-level packaging method, the packaging method comprising:
[0018] providing a square panel;
[0019] mounting a plurality of bridge chips on a surface of the square panel;
[0020] forming a plastic encapsulation layer wrapping the plurality of bridge chips on the surface of the square panel, and thinning the plastic encapsulation layer to expose bumps of the bridge chips;
[0021] forming a rewiring layer on a surface of the plastic encapsulation layer away from the square panel and on surfaces of the bumps;
[0022] mounting a chip operation layer and a connection module on the rewiring layer.
[0023] Optionally, when the plurality of bridge chips are mounted on the surface of the square panel, the method further comprises:
[0024] mounting a plurality of data relay chips on the surface of the square panel.
[0025] Optionally, mounting the connection module on the rewiring layer comprises:
[0026] mounting a plurality of connectors provided with cables on the rewiring layer; or,
[0027] mounting a plurality of photoelectric conversion chips provided with optical fibers on the rewiring layer.
[0028] Optionally, the square panel is a glass panel.
[0029] Another aspect of the embodiments of the present disclosure provides a board-level packaging system comprising at least one board-level packaging structure as described above; wherein,
[0030] when the board-level packaging system comprises a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the connection module.
[0031] The plate-level packaging structure, the plate-level packaging method and the plate-level packaging system of the embodiments of the present disclosure each adopt a large-area square panel, significantly improve the chip capacity, area utilization rate and I / O density, significantly improve the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high-computing power integration; the chip computing layer realizes high-density interconnection with the aid of multiple bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL. BRIEF DESCRIPTION OF DRAWINGS
[0032] Figure 1 A cross-sectional view of a plate-level packaging structure according to an embodiment of the present disclosure;
[0033] Figure 2 A cross-sectional view of a plate-level packaging structure according to another embodiment of the present disclosure;
[0034] Figure 3 A cross-sectional view of a plate-level packaging structure according to another embodiment of the present disclosure;
[0035] Figure 4 A cross-sectional view of a plate-level packaging structure according to another embodiment of the present disclosure;
[0036] Figure 5 A plan view of a plate-level packaging structure according to another embodiment of the present disclosure;
[0037] Figure 6 A flowchart of a plate-level packaging method according to another embodiment of the present disclosure;
[0038] Figure 7 FIG. 12 is a process diagram of a plate-level packaging method according to an embodiment of the present disclosure;
[0039] Figure 13 A diagram of a plate-level packaging structure according to another embodiment of the present disclosure;
[0040] Figure 14 A cross-sectional view of a plate-level packaging structure according to another embodiment of the present disclosure;
[0041] Figure 15 A cross-sectional view of a plate-level packaging structure according to another embodiment of the present disclosure;
[0042] Figure 16 A plan view of a plate-level packaging system according to another embodiment of the present disclosure. DETAILED DESCRIPTION
[0043] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.
[0044] As shown in Figures 1 to 5 , an aspect of the embodiments of the present disclosure provides a board-level packaging structure 100, comprising a square panel 22, a plurality of bridge chips 24, a plastic packaging layer 26, a rewiring layer, a chip operation layer 32 and a connection module.
[0045] The plurality of bridge chips 24 are arranged on the surface of the square panel 22. Specifically, the non-functional surfaces of the plurality of bridge chips 24 are arranged on the surface of the square panel 22. Among them, the plurality of bridge chips 24 are arranged in a matrix, and the number and distribution method of the plurality of bridge chips 24 are not specifically limited in the embodiments, and can be selected according to actual needs.
[0046] The plastic packaging layer 26 is arranged on the surface of the square panel 22 and wraps the plurality of bridge chips 24, thereby protecting the plurality of bridge chips 24.
[0047] The rewiring layer is arranged on the surface of the plastic packaging layer 26 away from the square panel 22 and the bump surface of the bridge chip 24, and is electrically connected with the bridge chip 24.
[0048] The chip operation layer 32 and the connection module are both arranged on the rewiring layer and are electrically connected with the rewiring layer. Specifically, in the embodiments, as shown in Figures 1 to 5 , the chip operation layer 32 is arranged in the central region of the rewiring layer, and the connection module is arranged in the edge region of the rewiring layer.
[0049] The board-level packaging structure of the embodiments of the present disclosure uses a large-area square panel for each board-level packaging structure, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high-computing power integration; The chip operation layer realizes high-density interconnection with the aid of the plurality of bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL.
[0050] For example, as shown in Figures 1 to 4 , in the embodiments, the rewiring layer comprises a dielectric layer 28 and a metal layer 30. The dielectric layer 28 is arranged on the surface of the plastic packaging layer 26 away from the square panel 22 and the bump surface of the bridge chip 24. The dielectric layer 28 is provided with a plurality of openings, and the metal layer 30 is arranged in each opening. The metal layer 30 is electrically connected with the bridge chip 24.
[0051] For example, as shown in Figure 3 and Figure 4As shown in FIG. 1, in an embodiment, the board-level package structure further comprises a plurality of data relay chips 42 disposed on the surface of the square panel 22 and wrapped in the plastic encapsulation layer 26. That is, the plurality of bridge chips 24 and the plurality of data relay chips 42 are both disposed on the surface of the square panel 22.
[0052] In the embodiment, the board-level package structure can improve the data transmission rate by disposing the plurality of data relay chips.
[0053] Exemplarily, in the embodiment, the square panel 22 is a glass panel. In the prior art, the carrier board is stripped in the packaging process, and the final package structure does not contain the carrier board. However, the board-level package structure of the embodiment of the present disclosure retains the square glass panel, and effectively controls the warping of the board-level package structure by using the rigidity of the glass panel, solves the problem of mismatching of large-area EMC and chip CTE, and improves the reliability of the board-level package structure.
[0054] Exemplarily, as shown in FIG. 2 and FIG. 3, Figure 1 and Figure 3 in an embodiment, the connection module comprises a plurality of connectors 34 disposed on the redistribution layer and cables 36 disposed on the connectors 34.
[0055] Specifically, as shown in FIG. 2 and FIG. 3, Figure 5 the plurality of connectors 34 are disposed on the redistribution layer of the edge region of the square panel 22, and each connector 34 is provided with a cable 36.
[0056] Exemplarily, as shown in FIG. 2 and FIG. 3, Figure 2 and Figure 4 in another embodiment, the connection module further comprises a plurality of optoelectronic conversion chips 38 disposed on the redistribution layer and optical fibers 40 disposed on the optoelectronic conversion chips 38.
[0057] Specifically, as shown in FIG. 2 and FIG. 3, Figure 5 the plurality of optoelectronic conversion chips 38 are disposed on the redistribution layer of the edge region of the square panel 22, and each connector 34 is provided with a cable 36.
[0058] Exemplarily, the chip operation layer 32 can only comprise a plurality of computing chips, or the chip operation layer 32 can comprise a plurality of computing chips and a plurality of storage chips. Of course, the chip operation layer 32 can also comprise other types of chips. The chips in the chip operation layer 32 are electrically interconnected through the redistribution layer and the bridge chip 24.
[0059] In the embodiment, according to the area of the square panel, the chip operation layer 32 is distributed in a matrix, which can significantly improve the chip capacity, area utilization rate and I / O density of the entire package structure.
[0060] It should be noted that the type and number of the chip operation layer 32 are not specifically limited, and can be selected according to actual needs.
[0061] As shown in Figure 6 Another aspect of the embodiment of the present disclosure provides a board-level packaging method S100, which comprises the following steps:
[0062] S110, providing a square panel.
[0063] As shown in Figure 7 A square panel 22 is provided. In this embodiment, the square panel 22 is preferably a glass panel.
[0064] The board-level packaging structure of the embodiment of the present disclosure retains the square glass panel, effectively controls the warping of the board-level packaging structure by the rigidity of the glass panel, solves the problem of mismatch between large-area EMC and chip CTE, and improves the reliability of the board-level packaging structure.
[0065] S120, mounting a plurality of bridge chips on the surface of the square panel.
[0066] As shown in Figure 7 The non-functional surfaces of a plurality of bridge chips 24 are mounted and fixed on the surface of the square panel 22. The plurality of bridge chips 24 are arranged in a matrix. The number and distribution of the plurality of bridge chips 24 are not specifically limited in this embodiment, and can be selected according to actual needs.
[0067] Exemplarily, when the plurality of bridge chips 24 are mounted on the surface of the square panel 22, the method S100 further comprises the following steps:
[0068] As shown in Figure 13 A plurality of data relay chips 42 are mounted on the surface of the square panel 22. In this embodiment, the plurality of data relay chips 42 and the plurality of bridge chips 24 are both mounted on the surface of the square panel 22, and the data transmission rate can be improved by the data relay chips 42.
[0069] As shown in Figure 14 and Figure 15 The structure diagram of a board-level packaging structure 100 obtained by packaging after mounting the bridge chips 24 and the data relay chips 42 on the square panel 22.
[0070] S130, forming a plastic packaging layer wrapping the plurality of bridge chips on the surface of the square panel, and thinning the plastic packaging layer to expose the bumps of the bridge chips.
[0071] As shown in Figure 8As shown, a molding compound 26 is formed on the side of the square panel 22 facing the bridging chip 24. The molding compound 26 encapsulates multiple bridging chips 24 and protects the bridging chips 24.
[0072] like Figure 9 As shown, the molding layer 26 is thinned on the side away from the square panel 22 using processes such as grinding, so as to expose the bumps (not shown in the figure) on the functional surface of the bridging chip 24.
[0073] S140. A redistribution layer is formed on the surface of the molding layer opposite to the square panel and on the surface of the bump.
[0074] like Figure 10 As shown, firstly, a dielectric layer 28 is formed on the surface of the molding layer 26 opposite to the square panel 22 and on the bump surface of the functional surface of the bridging chip 24.
[0075] Then, the dielectric layer 28 is patterned using photolithography and etching processes to form multiple openings on the dielectric layer 28.
[0076] Next, a metal layer 30 is formed at the opening through processes such as electroplating or sputtering, wherein the metal layer 30 is electrically connected to the bridging chip 24.
[0077] S150. The chip computing layer and the connection module are both mounted on the rewiring layer.
[0078] like Figure 11 , Figure 12 , Figure 14 and Figure 15 As shown, in this embodiment, the chip computing layer 32 is mounted on the central area of the redistribution layer, and the connection module is mounted on the edge area of the redistribution layer to form a board-level package structure 100.
[0079] like Figure 11 and Figure 14 As shown, in one embodiment, mounting the connection module on the edge region of the redistribution layer includes:
[0080] Multiple connectors 34, each equipped with a cable 36, are mounted on the edge area of the redistribution layer. In other words, multiple connectors 34 are distributed on the edge area of the square panel 22.
[0081] like Figure 12 and Figure 15 As shown, in another embodiment, mounting the connection module on the edge region of the redistribution layer further includes:
[0082] Multiple photoelectric conversion chips 38, each equipped with an optical fiber 40, are mounted on the edge area of the redistribution layer. In other words, multiple photoelectric conversion chips 38 are distributed on the edge area of the square panel 22.
[0083] It should be noted that the specific type of the connection module is not specifically limited, and can be selected according to actual needs.
[0084] The board-level packaging method of the embodiment of the present disclosure comprises: providing a square panel; mounting a plurality of bridge chips on the surface of the square panel; forming a plastic packaging layer wrapping the plurality of bridge chips on the surface of the square panel, and thinning the plastic packaging layer to expose the bumps of the bridge chips; forming a redistribution layer on the surface of the plastic packaging layer away from the surface of the square panel and the surface of the bumps; mounting the chip computing layer and the connection module on the redistribution layer; the board-level packaging structure formed in the method adopts a large-area square panel, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration; the chip computing layer realizes high-density interconnection with the aid of the plurality of bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL.
[0085] As shown in Figure 16 Another aspect of the embodiment of the present disclosure provides a board-level packaging system A comprising at least one board-level packaging structure 100 described above. Wherein the specific structural features of the board-level packaging structure 100 have been described in detail above, and will not be repeated here.
[0086] Wherein when the board-level packaging system A comprises a plurality of board-level packaging structures 100, the plurality of board-level packaging structures 100 are electrically connected through the connection module.
[0087] In an embodiment, the plurality of board-level packaging structures 100 can be electrically connected through the cable 36 of the connector 34, forming Figure 16 the board-level packaging system A shown in the figure.
[0088] In another embodiment, the plurality of board-level packaging structures A can be electrically connected through the optical fiber 40 of the optoelectronic conversion chip 38, forming Figure 16 the board-level packaging system A shown in the figure.
[0089] It should be noted that in the present embodiment, the electrical connection mode between the plurality of board-level packaging structures 100 is not specifically limited, and can be selected according to actual needs.
[0090] It should be further noted that the number of board-level packaging structures 100 in the board-level packaging system A is not specifically required, and can be selected according to the size of the board-level packaging structure.
[0091] The board-level packaging system of the embodiments of the present disclosure comprises at least one board-level packaging structure as described above, the board-level packaging structure adopts a large-area square panel, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration; the chip computing layer realizes high-density interconnection with the aid of multiple bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL.
[0092] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered as the protection scope of the embodiments of the present disclosure.
Claims
1. A board-level packaging structure, characterized in that, The package structure comprises: a square panel; a plurality of bridge chips arranged on the surface of the square panel; a plastic encapsulation layer arranged on the surface of the square panel and wrapping the plurality of bridge chips; a rewiring layer arranged on the surface of the plastic encapsulation layer away from the square panel and the bump surface of the bridge chips and electrically connected with the bridge chips; a chip operation layer and a connection module, both arranged on and electrically connected with the rewiring layer; wherein the package structure further comprises a plurality of data relay chips arranged on the surface of the square panel and wrapped by the plastic encapsulation layer; the connection module comprises a plurality of connectors arranged on the rewiring layer and cables arranged on the connectors; and / or, the connection module further comprises a plurality of photoelectric conversion chips arranged on the rewiring layer and optical fibers arranged on the photoelectric conversion chips.
2. The package-on-board structure of claim 1, wherein, The square panel is a glass panel.
3. The package-on-board structure of claim 1, wherein, The chip operation layer is arranged in the central region of the rewiring layer, and the connection module is arranged in the edge region of the rewiring layer.
4. The package-on-package structure of claim 1, wherein, The chip operation layer comprises a plurality of computing chips; or, the chip operation layer comprises a plurality of computing chips and a plurality of storage chips.
5. The package-on-board structure of claim 1, wherein, The rewiring layer comprises a dielectric layer and a metal layer; The dielectric layer is arranged on the surface of the plastic encapsulation layer away from the square panel and the bump surface of the bridge chips; The dielectric layer is provided with a plurality of openings, and the metal layer is arranged in each opening and electrically connected with the bridge chips.
6. A method of packaging a board, characterized by, The packaging method comprises: providing a square panel; arranging a plurality of bridge chips on the surface of the square panel; forming a plastic encapsulation layer on the surface of the square panel to wrap the plurality of bridge chips, and thinning the plastic encapsulation layer to expose the bumps of the bridge chips; forming a rewiring layer on the surface of the plastic encapsulation layer away from the square panel and the surface of the bumps; arranging a chip operation layer and a connection module on the rewiring layer; wherein when the plurality of bridge chips are arranged on the surface of the square panel, the method further comprises arranging a plurality of data relay chips on the surface of the square panel; 7. The method of claim 6, wherein, arranging the connection module on the rewiring layer comprises arranging a plurality of connectors provided with cables on the rewiring layer; and / or, arranging a plurality of photoelectric conversion chips provided with optical fibers on the rewiring layer.
8. The method of claim 6, wherein, The square panel is a glass panel. Arranging the chip operation layer and the connection module on the rewiring layer further comprises:
9. The method of claim 6, wherein, arranging the chip operation layer in the central region of the rewiring layer and arranging the connection module in the edge region of the rewiring layer. Forming the rewiring layer on the surface of the plastic encapsulation layer away from the square panel and the surface of the bumps comprises: applying a dielectric layer on the surface of the plastic encapsulation layer away from the square panel and the bump surface of the functional surface of the bridge chips; patterning the dielectric layer through photolithography and etching processes to form a plurality of openings on the dielectric layer; 10. A system for a board level package, comprising: forming a metal layer on the openings through electroplating or sputtering processes, wherein the metal layer is electrically connected with the bridge chips. The package structure comprises at least one of the package structures according to any one of claims 1 to 5. When the board-level packaging system comprises a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the connection module.
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