Cascade power electronic device pulse width modulation wave generation method and device
By using serial processing on FPGAs to generate pulse width modulation waves, the problem of excessive FPGA resource occupation is solved, and support for any number of power modules is achieved, cost reduction and unified design.
Patent Information
- Application Number
- CN202411870744.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-03-28
AI Technical Summary
When existing FPGAs are used for pulse width modulation in cascaded power electronic devices, they consume too much resources, resulting in the inability to support the application of a large number of power modules, resulting in resource tightness.
The pulse width modulation wave is generated by serial processing. By implementing the pulse width modulation module and register on the FPGA, the parameters of each power module are processed by register cyclic right shift method, and the pulse width modulation waves of each power module are generated and updated one by one.
It effectively reduces the utilization rate of FPGA resources, reduces the resources occupied by pulse width modulation, realizes the support of any number of pulse width modulation functions on existing FPGAs, reduces the material cost of the project, and unifies the pulse width modulation design of different projects.
Smart Images
Figure CN119727324A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of pulse width modulation, and in particular relates to a method and a device for generating pulse width modulation waves of a cascade power electronic device. Background Art
[0002] Flexible direct current (Voltage Source Converter-High Voltage Direct Current, VSC-HVDC) is a high-voltage direct current transmission technology based on voltage source converters. It uses fully controlled devices such as IGBT as core power devices. This transmission method has the advantages of fast response speed, good controllability, flexible operation mode, power supply to passive networks, no commutation failure, and easy to form a multi-terminal DC system. Power electronic devices are important equipment in flexible direct current transmission systems. Pulse-Width Modulation (PWM) is a very common modulation control method in power electronic devices. It adjusts the voltage and frequency by modulating the width of a series of pulses. Specifically, PWM adjusts the voltage and frequency by changing the proportion of the on-time to the total time, that is, the duty cycle. Usually, each power module requires a corresponding pulse width modulation module for control. In power electronic devices, multiple power modules are cascaded to form a corresponding circuit. The number of cascaded modules varies depending on the specific project.
[0003] At present, the pulse width modulation modules are generated in parallel and in real time in the FPGA. The number of power modules in the power electronic device corresponds to the number of pulse width modulation modules running in parallel in the FPGA. Each pulse width modulation module runs in parallel, and the corresponding pulse width modulation module generates the modulation wave signal of the corresponding power module in parallel and in real time (such as Figure 1 As shown in Figure 1). In the pulse width modulation module, the module parameters of each power module input include the modulation wave and module cascade sequence required for the corresponding PWM modulation. The output power module modulation wave is the pulse width modulation waveform corresponding to the power module, which is directly output to the power module. The power module adjusts the on and off state of its internal switching device (such as IGBT) according to the waveform and parameters of the modulation wave, thereby realizing the conversion and control of the input electric energy.
[0004] In this solution, the number of PWM modules is determined by the number of power modules N. When the number of power modules is small, the number of PWM modules is small and will not affect the use of FPGA resources. However, when the number of modules is particularly large, the number of corresponding PWM modules will be large, and the number of PWM modules in the FPGA will also increase significantly, so the occupied FPGA resources will be considerable, which will lead to a key problem: the existing FPGA may not provide enough resources to implement PWM. Summary of the invention
[0005] The present invention provides a method and device for generating pulse width modulation waves of a cascade power electronic device, and proposes a universal solution to the problem that pulse width modulation occupies a large amount of resources in FPGA and causes FPGA resource shortage when a large number of power modules are used.
[0006] In order to achieve the above object, the present invention adopts the following technical solution: In a first aspect, the present invention provides a method for generating a pulse width modulation wave of a cascade power electronic device, wherein a same pulse width modulation module generates pulse width modulation waves of each power module in sequence according to the module parameters of each power module and the number of the power modules, thereby obtaining a pulse width modulation wave of each power module in the entire cascade power electronic device; when generating the pulse width modulation wave of each power module, the carrier information of the power module is loaded into the pulse width modulation module, the carrier is updated, a pulse width modulation wave is generated based on the modulation wave and the carrier, and the updated carrier and pulse width modulation wave are saved.
[0007] Further, the following steps are included: Step 1: Number all power modules, and initialize the phase angle, carrier wave and modulation wave of each power module; i=1; i is the number of the power module; Step 2: Move the module parameters of i power modules into the pulse width modulation module, wherein the module parameters include modulation wave, carrier wave, module number and phase angle; Step 3, updating the phase angle of the i-th power module; the pulse width modulation module updates the carrier of the i-th power module based on the module parameters of the i-th power module, and generates a pulse width modulation wave of the i-th power module through the carrier; Step 4, save the pulse width modulation wave and the updated phase angle and carrier of the i-th power module; Step 5, determine the size relationship between i and N, where N is the total number of all power modules in the entire cascade power electronic device; if i<N, add 1 to the value of i and jump to step 2; if i is equal to N, execute step 6; Step 6: Set i=1 and return to step 2.
[0008] Furthermore, in step 2, the module parameters of the i-th power module are moved into the pulse width modulation module by using a register circular right shift method.
[0009] Furthermore, in step 2, moving the module parameters of the i-th power module into the pulse width modulation module includes: Each power module has a bit width of 16 bits, and N×16-bit registers are used to store the module parameters of all power modules. The PWM module only processes the lowest 16 bits of information each time. After processing the lower 16 bits each time, the register is cyclically shifted right by 16 bits, and the PWM module processes the lowest 16 bits of information again.
[0010] Furthermore, in step 3, the phase angle of the i-th power module is updated by superimposing a constant on the input phase angle, which returns to zero after being superimposed to 360 degrees.
[0011] Furthermore, in step 3, the pulse width modulation module updates the carrier of the i-th power module based on the module parameters of the i-th power module, and generating the pulse width modulation wave of the i-th power module through the carrier includes: Calculating the amplitude of the corresponding carrier according to the updated phase angle, and updating the carrier of the i-th power module based on the amplitude; The modulation wave of the i-th power module is obtained, and the updated carrier wave is compared with the current modulation wave signal of the i-th power module to generate a pulse width modulation wave.
[0012] In a second aspect, the present invention provides a cascade power electronic device pulse width modulation wave generating device, including a pulse width modulation module and a register; the pulse width modulation module and the register are both implemented on an FPGA, an EPLD or a CPLD; A pulse width modulation module is used to call the module parameters stored in the lowest bit of the register, and generate pulse width modulation based on the module parameters and update the carrier and phase angle; and send the updated carrier and phase angle to the register, and send the new pulse width modulation wave to the corresponding power module; The register is used to store the module parameters of all power modules and to move the module parameters of the power modules to the lowest bit in sequence according to the numbers of the power modules.
[0013] Furthermore, the bit width of the register is N×16 bits, and the bit width of each power module occupies 16 bits. The module parameters include the current modulation wave, current carrier and module serial number of each power module. In the initial state, the lower 16 bits of the register store the module parameters of the first power module, and the second 16 bits to the left store the parameters of the second power module, and so on. The highest 16 bits store the parameters of the Nth power module.
[0014] Furthermore, the pulse width modulation module generates a carrier wave, a phase angle and a pulse width modulation wave by the following steps: A constant is added to the input phase angle until it returns to zero after 360 degrees. Calculating the amplitude of the carrier according to the updated phase angle, and generating the carrier according to the amplitude; The generated carrier wave is compared with the input modulation wave to generate a pulse width modulated wave.
[0015] Further, the step of sequentially moving the module parameters of the power modules to the lowest bit according to the numbers of the power modules includes: In the initial state, the lower 16 bits of the register store the parameters of the first power module, the second 16 bits to the left store the parameters of the second power module, and so on, the highest 16 bits store the parameters of the Nth power module; When the module parameters stored in the lowest 16 bits are called by the PWM module, the register is cyclically shifted right by 16 bits.
[0016] Compared with the prior art, the present invention has at least the following beneficial technical effects: The pulse width modulation module of the present invention sequentially processes in series to generate modulation waves, solves the problem of pulse width modulation occupying resources, reduces the utilization rate of FPGA resources, compresses the resources occupied by pulse width modulation to a minimum, can realize any number of pulse width modulation functions on the current FPGA, can use relatively low-cost and small-capacity FPGA, and reduce the material cost of the project. At the same time, the pulse width modulation module is sequentially processed in series, and various distinctions will not be made in the design due to the information of the number of power modules, resulting in different designs for different projects. Different projects of the present invention can adopt a unified pulse width modulation design module, and there will be no differences in pulse width modulation design due to different numbers of power modules, and the pulse width modulation design schemes of different projects can be unified; in short, the present invention does not require large-capacity and high-cost selection on FPGA devices, nor does it require different designs for different projects, and all pulse width modulation designs are unified, which is convenient for platform design.
[0017] Furthermore, by adopting the register circular right shift method, data is circularly moved inside the register without the need for additional data copy operations, thereby improving the efficiency of data processing, realizing the periodic cyclic operation processing of pulse width modulation for each power module, simplifying the design difficulty, and reducing the utilization rate of FPGA resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a schematic diagram of the parallel operation scheme of each pulse width modulation module; Figure 2 A schematic diagram of the serial operation method provided by the present invention; Figure 3 Schematic diagram of right cyclic displacement. DETAILED DESCRIPTION
[0019] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
[0020] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0021] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be another element centered thereon. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be another element centered thereon at the same time. The terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc. used herein indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0023] The present invention mainly solves the problem that pulse width modulation occupies a large amount of resources in FPGA, compresses the resources occupied by pulse width modulation to a minimum, can realize any number of pulse width modulation functions on the current FPGA, and can also unify the design of all power transmission and transformation projects.
[0024] The solution proposed by the present invention is essentially to change the pulse width modulation control unit from a parallel scheme to a serial scheme, that is, only the pulse width modulation of one power module is operated each time.
[0025] like Figure 2 As shown, for a system with N power modules, there is only one pulse width modulation module in the system. The modulation wave of the first power module is processed first, and then the modulation wave of the second power module is processed, and then the modulation wave of the third power module 3 is processed. The processing is carried out in sequence until the modulation wave of the Nth power module. At this time, it returns to run the modulation wave of the first power module again, and the processing is cyclically carried out in sequence.
[0026] In this solution, the power module saves the module parameters, which include the current modulation wave, current carrier, module serial number and other information of each power module. The pulse width modulation module completes the carrier information update and pulse width modulation wave generation of the corresponding module. Compared with the existing technical solutions, the power modules need to save their own carrier information. After the PWM module is completed, the updated carrier information is saved for the next pulse width modulation module to perform calculation processing.
[0027] Each time the corresponding power module pulse width modulation wave is processed and generated, the corresponding carrier information is loaded into the pulse width modulation module, and then the pulse width modulation wave of the corresponding power module is compared with its updated carrier to generate a new pulse width modulation wave. After that, the corresponding power module saves its updated carrier information for use when the pulse width modulation module is operated next time. Then the pulse width modulation wave of the next power module is processed in a loop, and the processing is cyclically processed in sequence to generate the pulse width modulation waveform of the entire cascade system.
[0028] The pulse width modulation function is implemented using FPGA, including operations such as carrier generation, PWM wave generation, and maintenance of the phase relationship between cascaded power modules.
[0029] The following are specific embodiments. It should be noted that these embodiments are preferred examples of the present invention and are used for those skilled in the art to understand the present invention, but the present invention is not limited to these embodiments.
[0030] Example 1 Reference Figure 2 and Figure 3 This embodiment provides a method for generating a pulse width modulation wave of a cascade power electronic device, comprising the following steps: Step 1: Number all power modules and initialize the phase angle and carrier information of each power module; Step 2: Initialize the modulation wave information corresponding to each power module; Step 3: Move the module parameters of the first power module into the pulse width modulation module, where the pulse width modulation module is a program loaded on the FPGA; the module parameters include modulation wave, carrier wave, module number and phase angle; Step 4: Update the phase angle of the first power module. The pulse width modulation module generates a PWM carrier based on the updated phase angle. The pulse width modulation wave of the first power module is generated by the PWM carrier and the input current modulation wave of the first power module, including the following steps: First, the 16-bit power module parameters are input to the carrier generation module. The carrier generation module updates the phase angle of the first power module and calculates the amplitude of the corresponding carrier according to the updated phase angle. The modulation wave generation module updates the carrier information based on the amplitude, compares the updated carrier and the current modulation wave of the first power module, and generates a new pulse width modulation wave.
[0031] The method for updating the phase angle is to add a fixed constant in the carrier generation module until it returns to zero at 360 degrees.
[0032] Step 6, the first power module saves the phase angle, carrier information and pulse width modulation wave of the first power module updated by PWM; Step 7: Move the module parameters of the second power module into the pulse width modulation module; Step 8: The pulse width modulation module operates to generate a pulse width modulation wave of the second power module, and the generation method is the same as the method of operating to generate the pulse width modulation wave of the first power module; Step 9, the second power module saves the phase angle, carrier information and pulse width modulation wave of the second power module updated by PWM; Step 10: According to the serial numbering sequence of each power module, the calculation is performed sequentially to the Nth power module to generate a pulse width modulation wave of the Nth power module; Step 11: Return to step 3 and continue processing.
[0033] For example, if a 100MHz system clock is used with a period of 10ns, each carrier update is completed in a clock period of 10ns. If 200 power modules are calculated in series, it only takes 2us to complete. The time is completely less than the update speed of the modulated pulse signal, which meets the use requirements.
[0034] In some embodiments, a shift operation is used on the FPGA to implement a cyclic processing mode of N power modules, which is relatively resource-saving and easy to implement. The specific implementation method is as follows: There are four power modules, each of which has a bit width of 16 bits. At this time, a 64-bit wide register is used to save the carrier information and corresponding sequence number of all power modules. The register is a piece of code loaded on the FPGA.
[0035] The PWM pulse width modulation module only processes the lowest 16 bits of information each time. After processing the lower 16 bits each time, the register is cyclically shifted right by 16 bits, and the PWM pulse width modulation module processes the lowest 16 bits of information again. Through continuous cyclic shifting, the pulse width modulation function of processing N power modules in sequence is completed, which also saves other operations and FPGA resources.
[0036] The PWM pulse width modulation module updates the lower 16 bits of carrier information each time, and uses this information to update the pulse width modulation wave of the corresponding power module, and transmits this modulation wave to the corresponding power module.
[0037] Example 2 This embodiment provides a cascade power electronic device pulse width modulation wave generating device, including a PWM pulse width modulation module and a register; the PWM pulse width modulation module and the register are both implemented on an FPGA, an EPLD or a CPLD; PWM pulse width modulation module, used to call the module parameters of the power module stored in the lowest 16 bits of the register, generate a new carrier, phase angle and pulse width modulation wave based on the module parameters, send the new carrier, phase angle and pulse width modulation wave to the register, and send the new pulse width modulation wave to the corresponding power module; The PWM pulse width modulation module includes a carrier generation module and a modulation wave generation module.
[0038] The register is used to store the module parameters of all power modules. The bit width of the register is N×16 bits, and the bit width of each power module occupies 16 bits. The module parameters include the current modulation wave, current carrier, phase angle and module serial number of each power module. In the initial state, the lowest 16 bits of the register store the module parameters of the first power module, and the second 16 bits to the left store the parameters of the second power module, and so on. The highest 16 bits store the parameters of the Nth power module.
[0039] When the module parameters stored in the lowest 16 bits are called by the PWM module, the register is cyclically shifted right by 16 bits.
[0040] Example 3 This embodiment provides another cascade power electronic device pulse width modulation wave generating device, including a PWM pulse width modulation module and a register; the PWM pulse width modulation module and the register are both implemented on an FPGA, EPLD or CPLD to implement pulse width modulation operations, and a serial processing method is used to implement a modulation wave controlled by multiple power modules.
[0041] Example 4 This embodiment provides another pulse width modulation wave generating device for a cascade power electronic device, including a PWM pulse width modulation module and a register; the PWM pulse width modulation module and the register are integrated on an FPGA, EPLD or CPLD to implement pulse width modulation operations, and a serial processing method is used to realize the modulation wave controlled by multiple power modules.
[0042] The term "consisting of" describing a combination shall include the identified elements, ingredients, parts or steps and other elements, ingredients, parts or steps that do not substantially affect the basic novel characteristics of the combination. The use of the terms "comprising" or "including" to describe a combination of elements, ingredients, parts or steps herein also contemplates embodiments that consist essentially of these elements, ingredients, parts or steps. By using the term "may", it is intended to illustrate that any of the attributes described that "may" be included are optional.
[0043] Multiple elements, ingredients, parts or steps can be provided by a single integrated element, ingredient, part or step. Alternatively, a single integrated element, ingredient, part or step can be divided into separate multiple elements, ingredients, parts or steps. The disclosure "one" or "an" used to describe an element, ingredient, part or step is not intended to exclude other elements, ingredients, parts or steps.
[0044] The above description is intended to be illustrative and not limiting. Many embodiments and many applications beyond the examples provided will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of the present teachings should not be determined with reference to the above description, but rather with reference to the foregoing claims and the full scope of equivalents to which such claims are entitled. For the purpose of comprehensiveness, all articles and references, including disclosures of patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended to be a waiver of such subject matter, nor should it be considered that the applicant has not considered such subject matter to be part of the disclosed inventive subject matter.
Claims
1. A method for generating pulse width modulation waves of a cascade power electronic device, characterized in that: The same pulse width modulation module generates pulse width modulation waves of each power module in sequence according to the module parameters of each power module and the numbers of the power modules, thereby obtaining pulse width modulation waves of each power module in the entire cascade power electronic device; When generating the pulse width modulation wave of each power module, the carrier information of the power module is loaded into the pulse width modulation module, the carrier is updated, the pulse width modulation wave is generated based on the modulation wave and the carrier, and the updated carrier and pulse width modulation wave are saved.
2. A method for generating pulse width modulation waves of a cascade power electronic device according to claim 1, characterized in that: The following steps are involved: Step 1: Number all power modules, and initialize the phase angle, carrier wave and modulation wave of each power module; i=1; i is the number of the power module; Step 2: Move the module parameters of i power modules into the pulse width modulation module, wherein the module parameters include modulation wave, carrier wave, module number and phase angle; Step 3: Update the phase angle of the i-th power module; The pulse width modulation module updates the carrier wave of the i-th power module based on the module parameters of the i-th power module, and generates a pulse width modulation wave of the i-th power module through the carrier wave; Step 4, save the pulse width modulation wave and the updated phase angle and carrier of the i-th power module; Step 5, determining the magnitude relationship between i and N, where N is the total number of all power modules in the entire cascade power electronic device; If i<N, add 1 to the value of i and jump to step 2; If i is equal to N, go to step 6; Step 6: Set i=1 and return to step 2.
3. A method for generating pulse width modulation waves of a cascade power electronic device according to claim 1, characterized in that: In the step 2, the module parameters of the i-th power module are moved into the pulse width modulation module by using a register circular right shift method.
4. A method for generating pulse width modulation waves of a cascade power electronic device according to claim 2 or 3, characterized in that: In the step 2, moving the module parameters of the i-th power module into the pulse width modulation module comprises: Each power module has a bit width of 16 bits, and N×16-bit registers are used to store the module parameters of all power modules. The PWM module only processes the lowest 16 bits of information each time. After processing the lower 16 bits each time, the register is cyclically shifted right by 16 bits, and the PWM module processes the lowest 16 bits of information again.
5. A method for generating pulse width modulation waves of a cascade power electronic device according to claim 1, characterized in that: In step 3, the phase angle of the i-th power module is updated by superimposing a constant on the input phase angle, and restoring to zero after the superposition reaches 360 degrees.
6. A method for generating pulse width modulation waves of a cascade power electronic device according to claim 1, characterized in that: In step 3, the pulse width modulation module updates the carrier of the i-th power module based on the module parameters of the i-th power module, and generating the pulse width modulation wave of the i-th power module through the carrier includes: Calculating the amplitude of the corresponding carrier according to the updated phase angle, and updating the carrier of the i-th power module based on the amplitude; The modulation wave of the i-th power module is obtained, and the updated carrier wave is compared with the current modulation wave signal of the i-th power module to generate a pulse width modulation wave.
7. A pulse width modulation wave generating device for a cascade power electronic device, characterized in that: It includes a pulse width modulation module and a register; the pulse width modulation module and the register are both implemented on FPGA, EPLD or CPLD; A pulse width modulation module is used to call the module parameters stored in the lowest bit of the register, and generate pulse width modulation based on the module parameters and update the carrier and phase angle; and send the updated carrier and phase angle to the register, and send the new pulse width modulation wave to the corresponding power module; The register is used to store the module parameters of all power modules and to move the module parameters of the power modules to the lowest bit in sequence according to the numbers of the power modules.
8. A pulse width modulation wave generating device for a cascade power electronic device according to claim 7, characterized in that: The bit width of the register is N×16 bits, and the bit width of each power module occupies 16 bits. The module parameters include the current modulation wave, current carrier and module serial number of each power module. In the initial state, the lower 16 bits of the register store the module parameters of the first power module, and the second 16 bits to the left store the parameters of the second power module, and so on. The highest 16 bits store the parameters of the Nth power module.
9. A pulse width modulation wave generating device for a cascade power electronic device according to claim 7, characterized in that: The pulse width modulation module generates a carrier wave, a phase angle and a pulse width modulation wave by the following steps: A constant is added to the input phase angle until it returns to zero after 360 degrees. Calculating the amplitude of the carrier according to the updated phase angle, and generating the carrier according to the amplitude; The generated carrier wave is compared with the input modulation wave to generate a pulse width modulated wave.
10. A pulse width modulation wave generating device for a cascade power electronic device according to claim 7, characterized in that: The step of sequentially moving the module parameters of the power modules to the lowest bit according to the numbers of the power modules comprises: In the initial state, the lower 16 bits of the register store the parameters of the first power module, the second 16 bits to the left store the parameters of the second power module, and so on, the highest 16 bits store the parameters of the Nth power module; When the module parameters stored in the lowest 16 bits are called by the PWM module, the register is cyclically shifted right by 16 bits.