Resonant gate drive circuit, circuit system and electronic equipment

Abstract

The invention provides a resonant gate drive circuit, a circuit system and electronic equipment, which are used for driving a power tube, a source electrode of the power tube is connected with a ground end, a drain electrode of the power tube is connected with power supply voltage, and the resonant gate drive circuit comprises a drive module and a resonant inductor, a first end and a second end of the resonant inductor are respectively coupled to a first output end and a second output end of the driving module, the driving module is further respectively coupled to a driving power supply end and a driving ground end, and the driving module and the resonant inductor are jointly used for driving a power tube; the anti-voltage clamping module is coupled between the driving power supply end and the driving ground end, and the anti-voltage clamping module is used for preventing the grid voltage of the power tube from being clamped by the driving power supply end in the process of turning on the power tube and / or preventing the grid voltage of the power tube from being clamped by the driving ground end in the process of turning off the power tube. Therefore, the dynamic range of the grid voltage of the power tube is enlarged, and the driving capability of the driving module and the resonant inductor to the power tube is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a resonant gate drive circuit, a circuit system and an electronic device. Background Art

[0002] Switching power supplies are developing in the direction of high frequency and miniaturization, but as the switching frequency increases to above 300kHz, the loss of gate drive becomes non-negligible, which has a huge impact on the overall loss and efficiency of the circuit. If a traditional gate driver is used, there will be a large amount of energy loss in the gate drive process, which will also increase the power required for the auxiliary power module, and have higher requirements for the heat dissipation and occupied area of ​​the circuit, which is not conducive to improving the power density of the circuit.

[0003] In order to reduce the gate drive loss of high-frequency circuits, a resonant gate drive circuit was proposed in the 1990s. The resonant gate drive structure adds inductance to form an LC resonant cavity with the gate parasitic capacitance of the driven power MOSFET, so that the energy released when the MOS tube is turned off can be returned to the power supply, realizing energy recovery.

[0004] However, the existing resonant gate drive circuit has the problem of limited driving capability during the process of driving the power tube. Summary of the invention

[0005] Embodiments of the present invention provide a driving circuit, a circuit system and an electronic device to solve the problem that the ability of existing resonant gate driving circuits to drive power tubes is limited.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a resonant gate drive circuit for driving a power tube, wherein the source of the power tube is connected to the ground terminal, and the drain of the power tube is connected to the power supply voltage. The resonant gate drive circuit comprises:

[0007] A driving module and a resonant inductor, wherein the first end of the resonant inductor is coupled to the first output end of the driving module, the second end of the resonant inductor is respectively coupled to the gate of the power tube and the second output end of the driving module, the driving module is also respectively coupled to the driving power supply end and the driving ground end, and the driving module and the resonant inductor are used together to drive the power tube;

[0008] An anti-voltage clamping module is coupled between the driving power supply terminal and the driving ground terminal. The anti-voltage clamping module is used to prevent the gate voltage of the power tube from being clamped by the driving power supply terminal during the process of turning on the power tube, and / or to prevent the gate voltage of the power tube from being clamped by the driving ground terminal during the process of turning off the power tube.

[0009] Optionally, the anti-voltage clamping module includes: a first anti-voltage clamping unit, and the first anti-voltage clamping unit is used to prevent the gate voltage of the power tube from being clamped by the driving power supply terminal during the process of turning on the power tube.

[0010] Optionally, the first anti-voltage clamping unit includes a first diode, an anode of the first diode is coupled to the driving power supply end, and a cathode of the first diode is coupled to the second end of the resonant inductor.

[0011] Optionally, the first anti-voltage clamping unit includes a first anti-clamping MOS tube, the source of the first anti-clamping MOS tube is coupled to the driving power supply end, the drain of the first anti-clamping MOS tube is coupled to the second end of the resonant inductor, the gate of the first anti-clamping MOS tube is connected to its own source, the positive electrode of the body diode of the first anti-clamping MOS tube is coupled to the driving power supply end, and the negative electrode of the body diode of the first anti-clamping MOS tube is coupled to the second end of the resonant inductor.

[0012] Optionally, the anti-voltage clamping module includes: a second anti-voltage clamping unit, and the second anti-voltage clamping unit is used to prevent the gate voltage of the power tube from being clamped by the driving ground terminal during the process of shutting down the power tube.

[0013] Optionally, the second anti-voltage clamping unit includes a second diode, an anode of the second diode is coupled to the second end of the resonant inductor, and a cathode of the second diode is coupled to the driving ground end.

[0014] Optionally, the second anti-voltage clamping unit includes a second anti-clamping MOS tube, the source of the second anti-clamping MOS tube is coupled to the second end of the resonant inductor, the drain of the second anti-clamping MOS tube is coupled to the driving ground end, the gate of the second anti-clamping MOS tube is connected to its own source, the positive electrode of the body diode of the second anti-clamping MOS tube is coupled to the second end of the resonant inductor, and the negative electrode of the body diode of the second anti-clamping MOS tube is coupled to the driving ground end.

[0015] Optionally, the driving module includes:

[0016] A first driving NMOS tube, a second driving NMOS tube, a first driving PMOS tube and a second driving PMOS tube MP2 tube, the source of the first driving PMOS tube and the source of the second driving PMOS tube MP2 tube are both connected to the driving power supply end, the drain of the first driving PMOS tube and the drain of the first driving NMOS tube are both coupled to the first end of the resonant inductor as the first output end of the driving module, the drain of the second driving PMOS tube MP2 tube and the drain of the second driving NMOS tube are both coupled to the second end of the resonant inductor as the second output end of the driving module, and the source of the first driving NMOS tube and the source of the second driving NMOS tube are both coupled to the driving ground end;

[0017] A signal control unit is used to output a driving signal group to the gate of the first driving NMOS tube, the gate of the second driving NMOS tube, the gate of the first driving PMOS tube and the gate of the second driving PMOS tube MP2, by controlling the on and off of each of the first driving NMOS tube, the second driving NMOS tube, the first driving PMOS tube and the second driving PMOS tube MP2.

[0018] Optionally, the driving signal group includes a first driving signal, a second driving signal, a third driving signal and a fourth driving signal, the first driving signal is output to the gate of the first driving PMOS tube, the second driving signal is output to the gate of the second driving PMOS tube MP2 tube, the third driving signal is output to the gate of the first driving NMOS tube, and the fourth driving signal is output to the gate of the second driving NMOS tube;

[0019] In the conduction pre-charging stage of the resonant inductor, the first drive signal is at a low level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a high level;

[0020] In the start-up phase of the power tube, the first drive signal is at a high level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a low level;

[0021] In the gate energy recovery stage and the conduction stage of the power tube, the first drive signal is at a high level, the second drive signal is at a low level, the third drive signal is at a low level, and the fourth drive signal is at a low level;

[0022] In the shutdown pre-charging stage of the resonant inductor, the first drive signal is at a high level, the second drive signal is at a low level, the third drive signal is at a high level, and the fourth drive signal is at a low level;

[0023] In the shutdown phase of the power tube, the first drive signal is at a high level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a low level;

[0024] In the gate energy supplementation stage and disconnection stage of the power tube, the first drive signal is at a high level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a high level.

[0025] The technical solution of the present invention also provides a circuit system, including the resonant gate drive circuit.

[0026] The technical solution of the present invention further provides an electronic device, comprising the circuit system.

[0027] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0028] The resonant gate drive circuit provided by the technical solution of the present invention prevents the gate voltage of the power tube from being clamped by the driving power supply end during the power tube startup process, and / or prevents the gate voltage of the power tube from being clamped by the driving ground end during the shutdown process through an anti-voltage clamping module, thereby increasing the dynamic range of the gate voltage of the power tube, and further improving the driving capability of the driving module and the resonant inductor for the power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a circuit structure schematic diagram of an embodiment of a resonant gate drive circuit;

[0030] Figure 2 yes Figure 1 Waveform diagram of various parameters of the illustrated embodiment during operation;

[0031] Figure 3 A schematic diagram of a circuit structure of a resonant gate drive circuit provided in an embodiment of the present invention Figure 1 ;

[0032] Figure 4 A schematic diagram of a circuit structure of a resonant gate drive circuit provided in an embodiment of the present invention Figure 2 ;

[0033] Figure 5(a) to Figure 5(h) They are Figure 4 Circuit control diagram corresponding to different working stages of the embodiment shown;

[0034] Figure 6 for Figure 4 Waveform diagrams of various parameters of the illustrated embodiment at different working stages;

[0035] Figure 7A schematic diagram of a circuit structure of a resonant gate drive circuit provided in an embodiment of the present invention Figure 3 . DETAILED DESCRIPTION

[0036] As described in the background art, the existing resonant gate drive circuit has a problem of limited driving capability during the process of driving the power tube, which will be described below in conjunction with the accompanying drawings.

[0037] in, Figure 1 It is a circuit structure diagram of an embodiment of a resonant gate drive circuit. Figure 2 yes Figure 1 The waveform diagram of each parameter of the embodiment shown in the working process.

[0038] Please refer to Figure 1 This embodiment includes: a complementary driving PMOS tube mp1 and a driving NMOS tube mn1, an inductor L1 as a basic resonant element, and two diodes d1 and d2 for clamping a gate voltage vg and recovering driving energy; the source of the driving PMOS tube mpl is connected to a driving power supply voltage Vdd, the drain of the driving PMOS tube mp1 is respectively connected to the first end of the inductor L1 and the drain of the driving NMOS tube mn1, the source of the driving NMOS tube mn1 is connected to a driving ground terminal Vsw, the gates of the driving PMOS tube mp1 and the driving NMOS tube mn1 are respectively connected to control signals to control their respective on and off, the second end of the inductor L1 is respectively connected to the gate of the power tube Ma, the anode of the diode d1 and the cathode of the diode d2, the cathode of the diode d1 is connected to the driving power supply voltage Vdd, and the anode of the diode d2 is connected to the driving ground terminal Vsw.

[0039] The above embodiment has the following working process for turning on the power tube Ma:

[0040] Please refer to Figure 1 and Figure 2 , starting from t1, the power tube Ma enters the start-up stage, the gate of the driving PMOS tube mp1 is connected to a low level and turned on, so the drain voltage of the driving PMOS tube mp1 is pulled up to the driving power supply voltage Vdd. The inductor current flowing through the inductor L1 and the gate voltage vg of the power tube Ma both begin to rise. Until time t2, the inductor current reaches a peak value, and the gate voltage vg of the power tube Ma is pushed up to the driving power supply voltage Vdd by the inductor current to turn on the power tube Ma.

[0041] From t2 to t3, the gate voltage vg of the power tube Ma is clamped at the driving power supply voltage Vdd by the diode d1, and the inductor current flows from the driving power supply voltage Vdd along the driving PMOS tube mp1 to the inductor L1 to the diode d1 and finally back to the driving power supply voltage Vdd. Therefore, under ideal conditions, the inductor current remains unchanged.

[0042] At time t3, the gate energy recovery of the power tube Ma starts, the gate of the driving PMOS tube mp1 is connected to a high level and is turned off, and the body diode of the driving NMOS tube mn1 is turned on, so that the inductor current continues to flow along the path from the body diode of the driving NMOS tube mn1 to the inductor L1 to the diode d1, so that when there is a constant voltage at both ends of the inductor L1, that is, the driving power supply voltage Vdd, the inductor current decreases linearly. Until time t4, the inductor current decreases to zero to complete the gate energy recovery of the power tube Ma.

[0043] An ideal resonant gate drive circuit can make the gate voltage vg of the power tube Ma higher than the driving power supply voltage Vdd during the process of turning on the power tube Ma, thereby compensating for the influence of the gate parasitic resistance Rg and the source parasitic inductance Ls of the power tube Ma on the gate voltage vg. However, the problem existing in the process of turning on the power tube Ma in the above embodiment is that: from time t1 to t2, when the gate voltage vg of the power tube Ma rises to the turn-on voltage of the diode d1, the gate voltage vg of the power tube Ma will be clamped by the driving power supply voltage Vdd due to the conduction of the diode d1, resulting in the gate voltage vg being unable to continue to rise, thereby limiting the ability of the resonant gate drive circuit to turn on the power tube Ma, and further slowing down the turn-on rate of the power tube Ma.

[0044] In the above embodiment, when the gate voltage vg of the power tube Ma drops to the conduction voltage of the diode d2, the gate voltage vg of the power tube Ma will be clamped by the driving ground terminal Vsw due to the conduction of the diode d2, causing the gate voltage vg to be unable to continue to drop, thereby limiting the ability of the resonant gate drive circuit to shut down the power tube Ma, thereby slowing down the shutdown rate of the power tube Ma.

[0045] In view of this, an embodiment of the present invention provides a new resonant gate driving circuit for driving a power tube, wherein the source of the power tube is connected to the ground terminal, and the drain of the power tube is connected to the power supply voltage.

[0046] Figure 3 A schematic diagram of a circuit structure of a resonant gate drive circuit provided in an embodiment of the present invention Figure 1 .

[0047] Please refer to Figure 3 , the resonant gate drive circuit provided by the embodiment of the present invention includes:

[0048] A driving module 10 and a resonant inductor Lr, wherein a first end of the resonant inductor Lr is coupled to a first output end of the driving module 10, and a second end of the resonant inductor Lr is respectively coupled to a gate of the power tube Ma and a second output end of the driving module 10, and the driving module 10 is also respectively coupled to a driving power supply end VDD and a driving power supply end VSW, and the driving module 10 and the resonant inductor Lr are jointly used to drive the power tube Ma;

[0049] The anti-voltage clamping module 20 is coupled between the driving power supply terminal VDD and the driving power supply terminal VSW. The anti-voltage clamping module 20 is used to prevent the gate voltage VG of the power tube Ma from being clamped by the driving power supply terminal VDD during the process of turning on the power tube Ma, and / or to prevent the gate voltage VG of the power tube Ma from being clamped by the driving power supply terminal VSW during the process of turning off the power tube Ma.

[0050] Since the voltage-prevention clamping module 20 prevents the gate voltage VG of the power tube Ma from being clamped by the driving power supply terminal VDD during the process of turning on the power tube Ma, and / or prevents the gate voltage VG of the power tube Ma from being clamped by the driving power supply terminal VSW during the process of turning off the power tube Ma, during the process of turning on and off the power tube Ma, the gate voltage VG of the power tube Ma can rise to a voltage greater than the voltage at the driving power supply terminal VDD, and / or drop to a voltage less than the voltage at the driving power supply terminal VSW, thereby increasing the dynamic range of the gate voltage VG, and further improving the driving capability of the driving module 10 and the resonant inductor Lr to the power tube Ma.

[0051] In order to make the above-mentioned purposes, features and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0052] Figure 4 A schematic diagram of a circuit structure of a resonant gate drive circuit provided in an embodiment of the present invention Figure 2 . Figure 5(a) to Figure 5(h) They are Figure 4 The circuit control diagram corresponding to the embodiment shown in different working stages. Figure 6 for Figure 4 The waveform diagrams of various parameters of the illustrated embodiment at different working stages.

[0053] Please refer to Figure 4 In one embodiment, the driving module 10 includes:

[0054] A first driving NMOS transistor MN1, a second driving NMOS transistor MN2, a first driving PMOS transistor MP1 and a second driving PMOS transistor MP2, the source of the first driving PMOS transistor MP1 and the source of the second driving PMOS transistor MP2 are both connected to the driving power supply terminal VDD, the drain of the first driving PMOS transistor MP1 and the drain of the first driving NMOS transistor MN1 are both coupled to the first end of the resonant inductor Lr as the first output end of the driving module 10, the drain of the second driving PMOS transistor MP2 and the drain of the second driving NMOS transistor MN2 are both coupled to the second end of the resonant inductor Lr as the second output end of the driving module 10, and the source of the first driving NMOS transistor MN1 and the source of the second driving NMOS transistor MN2 are both coupled to the driving power supply terminal VSW;

[0055] The signal control unit 11 is used to output a driving signal group to the gate of the first driving NMOS transistor MN1, the gate of the second driving NMOS transistor MN2, the gate of the first driving PMOS transistor MP1 and the gate of the second driving PMOS transistor MP2, and control the on and off of the first driving NMOS transistor MN1, the second driving NMOS transistor MN2, the first driving PMOS transistor MP1 and the second driving PMOS transistor MP2. The driving signal group includes a first driving signal V1, a second driving signal V2, a third driving signal V3 and a fourth driving signal V4, wherein the first driving signal V1 is output to the gate of the first driving PMOS transistor MP1, the second driving signal V2 is output to the gate of the second driving PMOS transistor MP2, the third driving signal V3 is output to the gate of the first driving NMOS transistor MN1, and the fourth driving signal V4 is output to the gate of the second driving NMOS transistor MN2.

[0056] The voltage-proof clamping module 20 includes:

[0057] The first voltage-proof clamping unit 21 is used to prevent the gate voltage VG of the power tube Ma from being clamped by the driving power supply terminal VDD during the process of turning on the power tube Ma. The first voltage-proof clamping unit 21 is specifically a first diode D1, the anode of the first diode D1 is coupled to the drain of the second driving PMOS tube MP2, and the cathode of the first diode D1 is coupled to the second end of the resonant inductor Lr.

[0058] The second voltage-proof clamping unit 22 is used to prevent the gate voltage VG of the power tube Ma from being clamped by the driving power supply terminal VSW during the process of shutting down the power tube Ma. The second voltage-proof clamping unit 22 is specifically a second diode D2, the anode of the second diode D2 is coupled to the second end of the resonant inductor Lr, and the cathode of the first diode D1 is coupled to the drain of the second driving NMOS tube MN2.

[0059] Please refer to Figure 4 , Figure 6 as well as Figure 5(a) to Figure 5(h) , the working method of the above embodiment is described in detail below:

[0060] Please refer to Figure 4 , Figure 5(a) and Figure 6, the stage from t1 to t2 is the conduction pre-charging stage of the resonant inductor Lr, in which: the first drive signal V1 jumps from a high level to a low level to turn on the first drive PMOS tube MP1. The second drive signal V2 is at a high level to turn off the second drive PMOS tube MP2. The third drive signal V3 is at a low level to turn off the first drive NMOS tube MN1. The fourth drive signal V4 is at a high level to turn on the second drive NMOS tube MN2. Since the first drive PMOS tube MP1 and the second drive NMOS tube MN2 are both turned on, the current flows from the drive power supply terminal VDD through the first drive PMOS tube MP1-the resonant inductor Lr-the second drive NMOS tube MN2 to the drive power supply terminal VSW to turn on the resonant inductor Lr for pre-charging. At time point t2, the inductor current reaches a positive peak value, and the positive peak value formula of the inductor current is as follows:

[0061]

[0062] Wherein, Ipre1 is used to characterize the positive peak value of the inductor current, VDD is used to characterize the voltage of the driving power supply terminal VDD, VSW is used to characterize the voltage of the driving power supply terminal VSW, Vfds is used to characterize the forward conduction voltage of the second diode D2, t pre1 It is used to characterize the conduction pre-charging time, and Lr is used to characterize the inductance value of the resonant inductor Lr.

[0063] In this stage, since the second driving NMOS tube MN2 is turned on, the power tube Ma remains in the off state.

[0064] Please refer to Figure 4 , Figure 5(b) and Figure 6, the stage from t2 to t3 is the start-up stage of the power tube Ma, in which: the first drive signal V1 jumps from low level to high level, the second drive signal V2 still maintains high level, the third drive signal V3 still maintains low level, and the fourth drive signal V4 jumps from high level to low level, so the first drive PMOS tube MP1, the second drive PMOS tube MP2, the first drive NMOS tube MN1 and the second drive NMOS tube MN2 are all turned off. The inductor current flows to the gate of the power tube Ma to charge the gate-source capacitance of the power tube Ma. At this time, the body diode of the first drive NMOS tube MN1 is turned on, so the drain voltage of the first drive NMOS tube MN1 is pulled down to the drive power supply terminal VSW, thereby forming a freewheeling path from the second end of the resonant inductor Lr to the power tube Ma to the drive power supply terminal VSW to the body diode of the first drive NMOS tube MN1 to the first end of the resonant inductor Lr. As the inductor current continuously charges the gate-source capacitor, the gate voltage VG of the power tube Ma continuously rises. The gate voltage VG of the power tube Ma is as follows:

[0065]

[0066] Wherein, VG is used to characterize the gate voltage of the power tube Ma, Vgs is used to characterize the gate-source voltage of the power tube Ma, and I Lr It is used to characterize the inductor current, Ls is used to characterize the source parasitic inductance of the power tube Ma, Rg is used to characterize the gate parasitic resistance of the power tube Ma, and Ids is used to characterize the drain-source current of the power tube Ma.

[0067] Since the unidirectional conduction characteristic of the first diode D1 prevents the body diode of the second driving PMOS tube MP2 from being turned on, it is impossible to construct a connection path from the driving power supply terminal VDD to the second end of the resonant inductor Lr, so that when the gate voltage VG rises to the conduction voltage of the body diode of the second driving PMOS tube MP2, the gate voltage VG will not be clamped by the driving power supply terminal VDD and will continue to increase, thereby increasing the positive dynamic range of the gate voltage VG, and further accelerating the conduction rate of the power tube Ma. Since the gate voltage VG rises and the first end of the resonant inductor Lr is pulled down to the driving power supply terminal VSW, a reverse voltage from the second end to the first end of the resonant inductor Lr is applied to the resonant inductor Lr to continuously reduce the inductor current. Until the inductor current is reduced to zero, the gate voltage VG rises to a positive peak value. In an ideal case, ignoring the loss caused by the parasitic resistance on the charging path, the positive peak voltage of the gate voltage VG is

[0068]

[0069] Among them, Vgpkp is used to characterize the positive peak voltage of the gate voltage VG, and Cgs is used to characterize the gate-source capacitance of the power tube Ma.

[0070] When the power tube Ma and the resonant inductor Lr are both fixed, the positive peak value of the inductor current is adjusted by adjusting the on-time pre-charging time, thereby limiting the positive peak voltage of the gate voltage VG to within the rated voltage range of the power tube Ma.

[0071] Please refer to Figure 4 , Figure 5(c) and Figure 6 , the stage from t3 to t4 is the gate drive energy recovery of the power tube Ma. In this stage: the first drive signal V1 maintains a high level, the second drive signal V2 jumps from a high level to a low level, the third drive signal V3 and the fourth drive signal V4 both still maintain a low level, so the first drive PMOS tube MP1, the first drive NMOS tube MN1 and the second drive NMOS tube MN2 are all turned off, and the second drive PMOS tube MP2 is turned on. Since the inductor current is zero at the moment t3, and the voltage at the second end of the resonant inductor Lr is greater than the voltage at the first end of the resonant inductor Lr, the polarity of the inductor current reverses and turns on the body diode of the first drive PMOS tube MP1, and the current flows from the gate-source capacitance of the power tube Ma through the body diode of the first drive PMOS tube MP1 to the drive power supply terminal VDD to recover the gate drive energy of the power tube Ma, so the gate voltage VG of the power tube Ma is reduced. Since the second driving PMOS tube MP2 is turned on, when the gate voltage VG drops to the voltage at the driving power supply terminal VDD, the gate voltage VG is clamped by the driving power supply terminal VDD, the inductor current becomes zero again, and this stage ends.

[0072] Please refer to Figure 4 , Figure 5(d) and Figure 6 , the stage from t4 to t5 is the conduction stage of the power tube Ma, in which: the first drive signal V1, the second drive signal V2, the third drive signal V3 and the fourth drive signal V4 all maintain the state of the previous stage, so the first drive PMOS tube MP1, the first drive NMOS tube MN1 and the second drive NMOS tube MN2 are all turned off, and the second drive PMOS tube MP2 is turned on. In this stage, the inductor current is zero, and the gate voltage VG of the power tube Ma is clamped by the drive power supply terminal VDD and remains turned on.

[0073] Please refer to Figure 4 , Figure 5(e) and Figure 6, the stage from t5 to t6 is the shutdown pre-charging stage of the power tube Ma. In this stage: the first drive signal V1 still maintains a high level, the second drive control signal still maintains a low level, the third drive control signal jumps from the low level to a high level, and the fourth drive control signal still maintains a low level, so the first drive PMOS tube MP1 and the second drive NMOS tube MN2 are still turned off, the second drive PMOS tube MP2 is still turned on, and the first drive NMOS tube MN1 is turned on. Since the second drive PMOS tube MP2 and the first drive NMOS tube MN1 are both turned on, the current flows from the drive power supply terminal VDD through the second drive PMOS tube MP2-the resonant inductor Lr-the first drive NMOS tube MN1 to the drive power supply terminal VSW to realize the pre-charging of the inductor. At time point t6, the inductor current reaches a negative peak value, and the negative peak value formula of the inductor current is as follows:

[0074]

[0075] Wherein, Ipre2 is used to characterize the negative peak value of the inductor current, t pre2 Used to characterize the shutdown precharge time.

[0076] In this stage, since the second driving PMOS tube MP2 is turned on, the power tube Ma is kept in the linear region.

[0077] Please refer to Figure 4 , Figure 5(f) and Figure 6 , the stage from t6 to t7 is the turn-off stage of the power tube Ma, in which: the first drive signal V1 still maintains a high level, the second drive signal V2 jumps from a low level to a high level, the third drive signal V3 jumps from a high level to a low level, and the fourth drive signal V4 still maintains a low level, so the first drive PMOS tube MP1 and the second drive NMOS tube MN2 still remain turned off, and the second drive PMOS tube MP2 and the first drive NMOS tube MN1 are turned off. At this time, the body diode of the first drive NMOS tube MN1 is turned on to form a freewheeling path from the gate of the power tube Ma to the resonant inductor Lr to the body diode of the first drive NMOS tube MN1 to the drive power supply terminal VDD, thereby discharging the gate-source capacitance of the power tube Ma to reduce the gate of the power tube Ma.

[0078] Since the unidirectional conduction characteristic of the second diode D2 prevents the body diode of the second driving NMOS from being turned on, it is impossible to construct a connection path from the driving power supply terminal VSW to the second end of the resonant inductor Lr, so that when the gate voltage VG drops to the conduction voltage of the body diode of the second driving NMOS tube MN2, the gate voltage VG will not be clamped by the driving power supply terminal VSW and will continue to drop, thereby increasing the negative dynamic range of the gate voltage VG, thereby accelerating the turn-off rate of the power tube Ma. Since the gate voltage VG drops and the first end of the resonant inductor Lr is pulled up to the driving power supply terminal VDD, the forward voltage from the first end to the second end of the resonant inductor Lr is applied to the resonant inductor Lr to continuously increase the inductor current. Until the inductor current increases to zero, the gate voltage VG drops to a negative peak value. In an ideal case, ignoring the loss caused by the parasitic resistance on the charging path, the negative peak voltage of the gate voltage VG is:

[0079]

[0080] Wherein, Vgpkn is used to represent the negative peak voltage of the gate voltage VG.

[0081] When the power tube Ma and the resonant inductor Lr are both fixed, the negative peak value of the inductor current is adjusted by adjusting the turn-off pre-charging time, thereby limiting the negative peak voltage of the gate voltage VG to within the rated voltage range of the power tube Ma.

[0082] Please refer to Figure 4 , Figure 5(g) and Figure 6, stage t7 to t8: the first drive signal V1 and the second drive signal V2 both maintain a high level, the third drive signal V3 still maintains a low level, and the fourth drive signal V4 jumps from the low level to a high level, so the first drive PMOS tube MP1, the first drive NMOS tube MN1 and the second drive PMOS tube MP2 are all turned off, and the second drive NMOS tube MN2 is turned on. Since the inductor current is zero at the time t7, and the voltage at the first end of the resonant inductor Lr is greater than the voltage at the second end of the resonant inductor Lr, the polarity of the inductor current reverses and the body diode of the first drive NMOS tube MN1 is turned on, and the voltage of the first drive NMOS tube MN1 is pulled down to a level lower than the drive power supply terminal VSW, thereby forming a freewheeling path from the drive power supply terminal VSW to the body diode of the first drive NMOS tube MN1 to the resonant inductor Lr to the gate-source capacitance of the power tube Ma, so as to charge the gate capacitance of the power tube Ma, and the gate voltage VG of the power tube Ma increases from the negative peak. Since the second driving NMOS tube MN2 is turned on, when the gate voltage VG rises to the voltage at the driving power supply terminal VSW, the gate voltage VG is clamped by the driving power supply terminal VSW, the inductor current becomes zero again, and this stage ends.

[0083] Please refer to Figure 4 , Figure 5(h) and Figure 6 , after t8, the power tube Ma is in the disconnected state: the first drive signal V1, the second drive signal V2, the third drive signal V3 and the fourth drive signal V4 all maintain the state of the previous stage, so the first drive PMOS tube MP1, the first drive NMOS tube MN1 and the second drive PMOS tube MP2 are all turned off, and the second drive NMOS tube MN2 is turned on. In this stage, the inductor current is zero, and the gate voltage VG of the power tube Ma is clamped by the drive power supply terminal VSW and remains disconnected.

[0084] It can be seen from the working process of the above embodiment that the LC resonance of this embodiment only occurs in the turn-on stage and the turn-off stage of the power tube. In the turn-on stage and the turn-off stage of the power tube, the inductor current is equal to zero. Therefore, this embodiment is compatible with the widely used pulse width modulation without limiting the duty cycle. At the same time, because the dynamic range of the gate voltage of the power tube in the present invention is determined by the rated voltage and pre-charge current value of the power tube, and is not limited by the driving voltage terminal. Therefore, the power supply voltage selection of the driving voltage terminal has greater flexibility.

[0085] in, Figure 7 A schematic diagram of a circuit structure of a resonant gate drive circuit provided in an embodiment of the present invention Figure 3

[0086] Please refer to Figure 7 In another embodiment, the specific structure of the driving module and the control flow of the driving module are the same as those in the above embodiment and are not described in detail herein.

[0087] The first diode and the second diode may be replaced by a first anti-clamping MOS transistor MN3 and a second anti-clamping MOS transistor MN4 respectively.

[0088] The source of the first anti-clamp MOS transistor MN3 is coupled to the driving power supply terminal VDD, the drain of the first anti-clamp MOS transistor MN3 is coupled to the second end of the resonant inductor Lr, the gate of the first anti-clamp MOS transistor MN3 is connected to its own source, the anode of the body diode of the first anti-clamp MOS transistor MN3 is coupled to the driving power supply terminal VDD, and the cathode of the body diode of the first anti-clamp MOS transistor MN3 is coupled to the second end of the resonant inductor Lr. When the gate voltage VG is higher than the voltage at the driving power supply terminal VDD, the gate source of the first anti-clamp MOS transistor MN3 is short-circuited, so the first anti-clamp MOS transistor MN3 is in a cut-off state to block the connection between the gate of the power tube Ma and the driving power supply terminal VDD, thereby preventing the gate voltage VG of the power tube Ma from being clamped by the driving power supply terminal VDD. When the gate voltage VG is lower than the voltage at the driving power supply terminal VDD, the body diode of the first anti-clamp MOS transistor MN3 is turned on, so that the first anti-clamp MOS transistor MN3 does not affect the normal operation of the circuit.

[0089] The source of the second anti-clamp MOS transistor MN4 is coupled to the second end of the resonant inductor Lr, the drain of the second anti-clamp MOS transistor MN4 is coupled to the driving ground terminal VSW, the gate of the second anti-clamp MOS transistor MN4 is connected to its own source, the anode of the body diode of the second anti-clamp MOS transistor MN4 is coupled to the second end of the resonant inductor Lr, and the cathode of the body diode of the second anti-clamp MOS transistor MN4 is coupled to the driving ground terminal VSW. When the gate voltage VG is lower than the voltage at the driving ground terminal VSW, the gate source of the second anti-clamp MOS transistor MN4 is short-circuited, so the second anti-clamp MOS transistor MN4 is in a cut-off state to block the connection between the gate of the power tube Ma and the driving ground terminal VSW, thereby preventing the gate voltage VG of the power tube Ma from being clamped by the driving ground terminal VSW. When the gate voltage VG is higher than the voltage at the driving ground terminal VSW, the body diode of the second anti-clamp MOS transistor MN4 is turned on, so that the second anti-clamp MOS transistor MN4 does not affect the normal operation of the circuit.

[0090] In another embodiment, the voltage protection clamping module only includes the first voltage protection clamping unit or the second voltage protection clamping unit, and the first voltage protection clamping unit or the second voltage protection clamping unit both include a diode. The specific structure of the driving module and the control flow of the driving module are the same as those in the above embodiment, and are not described in detail here.

[0091] In this embodiment, since only the first voltage protection clamping unit or the second voltage protection clamping unit is provided, only the positive dynamic range of the gate voltage can be increased or the negative dynamic range of the gate voltage can be increased.

[0092] In summary, the resonant gate drive circuit provided by the embodiment of the present invention prevents the gate voltage of the power tube from being clamped by the driving power supply end during the power tube startup process, and / or prevents the gate voltage of the power tube from being clamped by the driving ground end during the shutdown process through the anti-voltage clamping module, so that in the process of turning on and off the power tube, the gate voltage of the power tube can rise to a voltage greater than the voltage at the driving power supply end, and / or drop to a voltage less than the voltage at the driving ground end, thereby increasing the dynamic range of the gate voltage, and further improving the driving capability of the driving module and the resonant inductor to the power tube.

[0093] An embodiment of the present invention further provides a circuit system, comprising the resonant gate drive circuit.

[0094] An embodiment of the present invention further provides an electronic device, comprising the circuit system.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A resonant gate drive circuit, characterized in that: Used to drive a power tube, the source of the power tube is connected to the ground terminal, the drain of the power tube is connected to the power supply voltage, and the resonant gate drive circuit includes: A driving module and a resonant inductor, wherein the first end of the resonant inductor is coupled to the first output end of the driving module, the second end of the resonant inductor is respectively coupled to the gate of the power tube and the second output end of the driving module, the driving module is also respectively coupled to the driving power supply end and the driving ground end, and the driving module and the resonant inductor are used together to drive the power tube; An anti-voltage clamping module is coupled between the driving power supply terminal and the driving ground terminal. The anti-voltage clamping module is used to prevent the gate voltage of the power tube from being clamped by the driving power supply terminal during the process of turning on the power tube, and / or to prevent the gate voltage of the power tube from being clamped by the driving ground terminal during the process of turning off the power tube.

2. The resonant gate drive circuit according to claim 1, characterized in that: The anti-voltage clamping module includes: a first anti-voltage clamping unit, and the first anti-voltage clamping unit is used to prevent the gate voltage of the power tube from being clamped by the driving power supply terminal during the process of turning on the power tube.

3. The resonant gate drive circuit according to claim 2, characterized in that: The first voltage-prevention clamping unit includes a first diode, an anode of the first diode is coupled to the driving power supply terminal, and a cathode of the first diode is coupled to the second terminal of the resonant inductor.

4. The resonant gate drive circuit according to claim 2, characterized in that: The first anti-voltage clamping unit includes a first anti-clamping MOS tube, a source of the first anti-clamping MOS tube is coupled to the driving power supply end, a drain of the first anti-clamping MOS tube is coupled to the second end of the resonant inductor, a gate of the first anti-clamping MOS tube is connected to its own source, an anode of a body diode of the first anti-clamping MOS tube is coupled to the driving power supply end, and a cathode of the body diode of the first anti-clamping MOS tube is coupled to the second end of the resonant inductor.

5. The resonant gate drive circuit according to any one of claims 1 to 4, characterized in that: The voltage-proof clamping module comprises: a second voltage-proof clamping unit, and the second voltage-proof clamping unit is used to prevent the gate voltage of the power tube from being clamped by the driving ground terminal during the process of shutting down the power tube.

6. The resonant gate drive circuit according to claim 5, characterized in that: The second voltage-preventing clamping unit includes a second diode, an anode of the second diode is coupled to the second end of the resonant inductor, and a cathode of the second diode is coupled to the driving ground end.

7. The resonant gate drive circuit according to claim 5, characterized in that: The second anti-voltage clamping unit includes a second anti-clamping MOS tube, a source of the second anti-clamping MOS tube is coupled to the second end of the resonant inductor, a drain of the second anti-clamping MOS tube is coupled to the driving ground end, a gate of the second anti-clamping MOS tube is connected to its own source, an anode of a body diode of the second anti-clamping MOS tube is coupled to the second end of the resonant inductor, and a cathode of the body diode of the second anti-clamping MOS tube is coupled to the driving ground end.

8. The resonant gate drive circuit according to claim 5, characterized in that: The driving module comprises: A first driving NMOS tube, a second driving NMOS tube, a first driving PMOS tube and a second driving PMOS tube MP2 tube, the source of the first driving PMOS tube and the source of the second driving PMOS tube MP2 tube are both connected to the driving power supply end, the drain of the first driving PMOS tube and the drain of the first driving NMOS tube are both coupled to the first end of the resonant inductor as the first output end of the driving module, the drain of the second driving PMOS tube MP2 tube and the drain of the second driving NMOS tube are both coupled to the second end of the resonant inductor as the second output end of the driving module, and the source of the first driving NMOS tube and the source of the second driving NMOS tube are both coupled to the driving ground end; A signal control unit is used to output a driving signal group to the gate of the first driving NMOS tube, the gate of the second driving NMOS tube, the gate of the first driving PMOS tube and the gate of the second driving PMOS tube MP2, by controlling the on and off of each of the first driving NMOS tube, the second driving NMOS tube, the first driving PMOS tube and the second driving PMOS tube MP2.

9. The resonant gate drive circuit according to claim 8, characterized in that: The driving signal group includes a first driving signal, a second driving signal, a third driving signal and a fourth driving signal, the first driving signal is output to the gate of the first driving PMOS tube, the second driving signal is output to the gate of the second driving PMOS tube MP2 tube, the third driving signal is output to the gate of the first driving NMOS tube, and the fourth driving signal is output to the gate of the second driving NMOS tube; In the conduction pre-charging stage of the resonant inductor, the first drive signal is at a low level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a high level; In the start-up phase of the power tube, the first drive signal is at a high level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a low level; In the gate energy recovery stage and the conduction stage of the power tube, the first drive signal is at a high level, the second drive signal is at a low level, the third drive signal is at a low level, and the fourth drive signal is at a low level; In the shutdown pre-charging stage of the resonant inductor, the first drive signal is at a high level, the second drive signal is at a low level, the third drive signal is at a high level, and the fourth drive signal is at a low level; In the shutdown phase of the power tube, the first drive signal is at a high level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a low level; In the gate energy supplementation stage and disconnection stage of the power tube, the first drive signal is at a high level, the second drive signal is at a high level, the third drive signal is at a low level, and the fourth drive signal is at a high level.

10. A circuit system, characterized in that: A resonant gate drive circuit comprising the resonant gate drive circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that: A circuit system comprising the circuit system of claim 10.

Images