A high-side switch circuit and radio frequency front-end system

Abstract

The embodiment of the present disclosure provides a high-side switch circuit and a radio frequency front-end system, wherein the high-side switch circuit comprises: a first frequency modulation circuit, a first charge pump circuit and a first switch transistor; a first end of the first frequency modulation circuit receives a first initial adjustment signal, a second end of the first frequency modulation circuit is connected with a control end of the first charge pump circuit, a first end of the first charge pump circuit is connected with a gate end of the first switch transistor, a second end of the first charge pump circuit and a second end of the first switch transistor are both connected with an input end of a load circuit, and a first end of the first switch transistor is connected with a first power supply; the first frequency modulation circuit is used for generating a first oscillation clock signal under the control of the first initial adjustment signal; an oscillation frequency of the first oscillation clock signal in a starting state of charging of the first charge pump circuit is greater than oscillation frequencies in other states; and the first charge pump circuit is used for turning on the first switch transistor under the control of the first oscillation clock signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of switching power supply, and relates to, but is not limited to, a high-side switching circuit and a radio frequency front-end system. BACKGROUND

[0002] The metal oxide semiconductor (MOS) high-side switch is widely used in many fields such as automobiles, industries and mobile devices due to its low loss, easy driving, high reliability and ideal switching characteristics.

[0003] In the related art, the opening of the switching transistor is controlled by controlling the charging and discharging of the capacitor in the charge pump circuit; however, the capacitor in the charge pump circuit needs a certain time to charge, so that the opening time of the switching transistor is relatively long, and the response speed of the opening of the switching transistor is reduced. SUMMARY

[0004] Therefore, the present disclosure provides a high-side switching circuit.

[0005] In a first aspect, the present disclosure provides a high-side switching circuit, which comprises:

[0006] a first frequency modulation circuit, a first charge pump circuit and a first switching transistor; a first end of the first frequency modulation circuit receives a first initial adjustment signal, a second end of the first frequency modulation circuit is connected with a control end of the first charge pump circuit, a first end of the first charge pump circuit is connected with a gate end of the first switching transistor, a second end of the first charge pump circuit and a second end of the first switching transistor are both connected with an input end of a load circuit, and a first end of the first switching transistor is connected with a first power supply; wherein:

[0007] The first frequency modulation circuit is configured to generate a first oscillation clock signal under the control of the first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in a starting state of the charging of the first charge pump circuit is greater than the oscillation frequency in other states.

[0008] The first charge pump circuit is configured to adjust the voltage of the gate end thereof according to the voltage feedback of the second end of the first switching transistor under the control of the first oscillation clock signal, so that the difference between the voltage of the gate end of the first switching transistor and the voltage of the second end of the first switching transistor is a preset difference, and the first switching transistor is turned on.

[0009] In some embodiments, the first frequency modulation circuit comprises: a first control circuit and a first oscillator; a first end of the first control circuit receives the first initial adjustment signal, a second end of the first control circuit is connected with a first end of the first oscillator, and a second end of the first oscillator is connected with a control end of the first charge pump circuit; wherein:

[0010] The first control circuit is configured to perform first preprocessing on the first initial adjustment signal to generate a first adjustment signal; the first preprocessing comprises converting the first adjustment signal from a second level state to a first level state and maintaining the first adjustment signal in the first level state for a first preset time when the first initial adjustment signal is converted from the second level state to the first level state.

[0011] The first oscillator is configured to generate the first oscillation clock signal under the control of the first adjustment signal; the oscillation frequency of the first oscillation clock signal when the first adjustment signal is in the first level state is greater than the oscillation frequency of the first oscillation clock signal when the first adjustment signal is in the second level state.

[0012] In some embodiments, the high-side switch circuit further comprises a second frequency modulation circuit, a second charge pump circuit and a second switch transistor; a first end of the second frequency modulation circuit receives a second initial adjustment signal, a second end of the second frequency modulation circuit is connected with a control end of the second charge pump circuit, a first end of the second charge pump circuit is connected with a gate end of the second switch transistor, a second end of the second charge pump circuit and a second end of the second switch transistor are both connected with an input end of the load circuit, and a first end of the second switch transistor is connected with a second power supply; wherein:

[0013] The second frequency modulation circuit is configured to generate a second oscillation clock signal under the control of the second initial adjustment signal; the oscillation frequency of the second oscillation clock signal in a starting state of the second charge pump circuit charging is greater than the oscillation frequency of the second oscillation clock signal in other states.

[0014] The second charge pump circuit is configured to adjust the gate end voltage of the second switch transistor according to the voltage feedback of the second end of the second switch transistor under the control of the second oscillation clock signal, so that the difference between the voltage of the gate end of the second switch transistor and the voltage of the second end of the second switch transistor is a preset difference, to turn on the second switch transistor.

[0015] In some embodiments, the second frequency modulation circuit comprises: a second control circuit and a second oscillator; a first end of the second control circuit receives the second initial adjustment signal, and a second end of the second control circuit is connected with a first end of the second oscillator; a second end of the second oscillator is connected with a control end of the second charge pump circuit; wherein:

[0016] The second control circuit is configured to perform second preprocessing on the second initial adjustment signal to generate a second adjustment signal; and the second preprocessing is to convert the second adjustment signal from the second level state to the first level state and maintain the second adjustment signal in the first level state for a second preset time when the second initial adjustment signal is converted from the second level state to the first level state.

[0017] The second oscillator is configured to generate the second oscillation clock signal under the control of the second adjustment signal; and the oscillation frequency of the second oscillation clock signal when the second adjustment signal is in the first level state is greater than the oscillation frequency of the second oscillation clock signal when the second adjustment signal is in the second level state.

[0018] In some embodiments, the high-side switch circuit further comprises a logic control circuit; a first output terminal of the logic control circuit is connected to the first terminal of the first control circuit, and a second output terminal of the logic control circuit is connected to the first terminal of the second control circuit; wherein:

[0019] The logic control circuit is configured to receive a first adjustment control signal and a second adjustment control signal, and perform logic processing on the first adjustment control signal and the second adjustment control signal to generate the first initial adjustment signal and the second initial adjustment signal; wherein, if the first adjustment control signal and the second adjustment control signal are both in the first level state, the first initial adjustment signal and the second initial adjustment signal are both in the second level state; otherwise, the first initial adjustment signal is the same as the first adjustment control signal, and the second initial adjustment signal is the same as the second adjustment control signal.

[0020] In some embodiments, a first output terminal of the logic control circuit is further coupled to a third terminal of the first charge pump circuit, and a second output terminal of the logic control circuit is further coupled to a third terminal of the second charge pump circuit; wherein:

[0021] The first initial adjustment signal is further configured to control the opening and closing of the first charge pump circuit.

[0022] The second initial adjustment signal is further configured to control the opening and closing of the second charge pump circuit.

[0023] In some embodiments, the high-side switch circuit further comprises a dead-time control circuit, the dead-time control circuit comprising a first delay processing circuit and a second delay processing circuit; a first end of the first delay processing circuit is connected with a first output end of the logic control circuit, a second end of the first delay processing circuit is connected with a third end of the first charge pump circuit, a first end of the second delay processing circuit is connected with a second output end of the logic control circuit, and a second end of the second delay processing circuit is connected with a third end of the second charge pump circuit; wherein:

[0024] The first delay processing circuit is configured to receive the first initial adjustment signal and perform delay logic processing on the first initial adjustment signal to generate a first control signal.

[0025] The second delay processing circuit is configured to receive the second initial adjustment signal and perform delay logic processing on the second initial adjustment signal to generate a second control signal.

[0026] In some embodiments, when the first control signal is in an enabled state, the first charge pump circuit is turned on, and the first switch transistor is turned on; when the second control signal is in an enabled state, the second charge pump circuit is turned on, and the second switch transistor is turned on; when one of the first initial adjustment signal and the second initial adjustment signal changes from the second level state to the first level state, one of the first control signal and the second control signal changes from the second level state to the first level state after a dead-time interval.

[0027] In some embodiments, the logic control circuit comprises a first NOT gate, a second NOT gate, a first AND gate, and a second AND gate.

[0028] A first input end of the first AND gate is configured to receive a first adjustment control signal, a second input end of the first AND gate is connected with an output end of the first NOT gate, and an output end of the first AND gate outputs the first initial adjustment signal; an input end of the first NOT gate is configured to receive a second adjustment control signal.

[0029] A first input end of the second AND gate is connected with an output end of the second NOT gate, a second input end of the second AND gate is configured to receive the second adjustment control signal, and an output end of the second AND gate outputs the second initial adjustment signal; an input end of the second NOT gate is configured to receive the first adjustment control signal.

[0030] In some embodiments, the first delay processing circuit comprises a first delay unit and a third AND gate, and the second delay processing circuit comprises a second delay unit and a fourth AND gate.

[0031] The input end of the first delay unit is configured to receive the first initial adjustment signal, the output end of the first delay unit is connected with the first input end of the third AND gate, the second input end of the third AND gate is configured to receive the first initial adjustment signal, and the output end of the third AND gate outputs the first control signal.

[0032] The input end of the second delay unit is configured to receive the second initial adjustment signal, the output end of the second delay unit is connected with the second input end of the fourth AND gate, the first input end of the fourth AND gate is configured to receive the second initial adjustment signal, and the output end of the fourth AND gate outputs the second control signal.

[0033] In some embodiments, the first switch transistor and the second switch transistor are both NMOS tubes.

[0034] The working mode of the first power supply includes an ET mode or an APT mode, and the working mode of the second power supply includes an ET mode or an APT mode, and the working modes of the first power supply and the second power supply are different.

[0035] In a second aspect, the disclosure provides a radio frequency front-end system, including the high-side switch circuit in any of the above embodiments.

[0036] The high-side switch circuit and the radio frequency front-end system provided by the embodiments of the present disclosure have the following beneficial effects: the first frequency modulation circuit is configured to generate a first oscillation clock signal under the control of the first initial adjustment signal, and the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit is greater than the oscillation frequency in other states; the first charge pump circuit is configured to adjust the voltage of the gate end of the first switch transistor according to the voltage feedback of the second end of the first switch transistor under the control of the first oscillation clock signal, so that the difference between the voltage of the gate end of the first switch transistor and the voltage of the second end of the first switch transistor is a preset difference, and the first switch transistor is turned on. In this way, since the first oscillation clock signal has a higher frequency in the initial state of charging of the charge pump circuit, the charging speed of the charge pump circuit can be accelerated, and the first switch transistor can be turned on quickly, so that the response speed of the first switch transistor is higher. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1Structure schematic of high-side switch circuit provided by the embodiment of the present disclosure Figure 1 ;

[0038] Figure 2 Waveform schematic of first voltage under ET mode and APT provided by the embodiment of the present disclosure

[0039] Figure 3 Structure schematic of load circuit provided by the embodiment of the present disclosure

[0040] Figure 4 Structure schematic of high-side switch circuit provided by the embodiment of the present disclosure Figure 2 ;

[0041] Figure 5 Timing schematic of first frequency modulation circuit provided by the embodiment of the present disclosure

[0042] Figure 6 Structure schematic of high-side switch circuit provided by the embodiment of the present disclosure Figure 3 ;

[0043] Figure 7 Structure schematic of logic control circuit and dead time control circuit provided by the embodiment of the present disclosure

[0044] Figure 8 Timing schematic of logic control circuit and dead time control circuit provided by the embodiment of the present disclosure

[0045] Figure 9 Structure schematic of radio frequency front-end system provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0047] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail in order to avoid obscuring aspects of the present disclosure.

[0048] In the drawings, the size of layers, regions, elements, and / or the like can be exaggerated for clarity. Like numbers refer to like elements throughout.

[0049] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] At present, MOS high-side switches are widely used in many fields such as automobiles, industries, mobile devices, etc. due to their low loss, easy driving, high reliability and ideal switching characteristics, and cover control and protection within tens of amperes of current.

[0052] Further, when the N-type MOS transistor (NMOS transistor) is used as a high-side switching device, it has the advantages of small size and stable switching resistance. When the NMOS transistor is used as a high-side switching device, the source of the NMOS transistor is connected to a load, which causes two problems: the source is floating, and the gate voltage is higher than the drain supply voltage. In the related art, in order to overcome these two problems, a voltage stabilizing circuit and a charge pump circuit are usually used to control the voltage at the gate terminal of the NMOS transistor. However, since the voltage stabilizing circuit needs a certain start-up time, and the capacitor in the charge pump circuit also needs a certain charging time, the switching transistor has a long start-up time, which reduces the response speed of the switching transistor.

[0053] Therefore, the high-side switching circuit and the radio frequency front-end system provided by the embodiments of the present disclosure have the following beneficial effects: the first oscillation clock signal has a high frequency at the initial state of the charging of the first charge pump circuit, so that the charging speed of the first charge pump circuit is increased, and the first switching transistor can be quickly turned on, so that the response speed of the first switching transistor is high.

[0054] The high-side switching circuit in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0055] Figure 1 A structural schematic diagram of a high-side switching circuit 100 provided by the embodiments of the present disclosure is shown in FIG. 1. Figure 1As shown, the high-side switch circuit 100 comprises a first frequency modulation circuit 110, a first charge pump circuit 120 and a first switch transistor 130; a first end of the first frequency modulation circuit 110 receives a first initial adjustment signal, a second end of the first frequency modulation circuit 110 is connected with a control end of the first charge pump circuit 120, a first end of the first charge pump circuit 120 is connected with a gate end of the first switch transistor 130, a second end of the first charge pump circuit 120 and a second end of the first switch transistor 130 are both connected with an input end of a load circuit 150, and a first end of the first switch transistor 130 is connected with a first power supply 140; wherein:

[0056] The first frequency modulation circuit 110 is configured to generate a first oscillation clock signal under the control of the first initial adjustment signal; the oscillation frequency of the first oscillation clock signal in a starting state of charging of the first charge pump circuit 120 is greater than the oscillation frequency in other states.

[0057] The first charge pump circuit 120 is configured to adjust the voltage of the gate end thereof according to the voltage feedback of the second end of the first switch transistor 130 under the control of the first oscillation clock signal, so that the difference between the voltage of the gate end of the first switch transistor 130 and the voltage of the second end of the first switch transistor 130 is a preset difference value, to turn on the first switch transistor 130.

[0058] Here, the first initial adjustment signal can be represented by EN Fre ctrl<0>, the first oscillation clock signal can be represented by CLK<0>, the first power supply 140 is configured to output a first voltage, the first voltage can be a voltage for powering the load circuit 150, and the first voltage can be represented by VCC_PS1(not shown in the figure). In other embodiments, the first voltage can also be other voltages, or can be provided by other power supply circuits.

[0059] Further, the first voltage can be a fixed voltage or a variable voltage. The first power supply 140 is configured to supply power and work in either of an envelope tracking mode (ET mode) and an average power tracking mode (APT mode); the voltage waveforms of the first voltage in the ET mode and the APT mode are shown in Figure 2 .

[0060] In addition, a structural schematic diagram of the load circuit 150 is shown in Figure 3As shown in FIG. 1, the load circuit 150 can include a power amplifier 151 (PA). A first end of the power amplifier 151 is connected to the second end of the first switch transistor 130 through the port 152; a second end of the power amplifier 151 is grounded; an input end of the power amplifier 151 is configured to receive the radio frequency input signal RF_in; and an output end of the power amplifier 151 is configured to output a radio frequency output signal RF_out. It should be noted that, Figure 3 The load circuit 150 in FIG. 1 is a simplified structure diagram, and in fact, the load circuit 150 can be any circuit structure that can be implemented.

[0061] In the embodiments of the present disclosure, the oscillation frequency of the first oscillation clock signal in the initial state of charging of the first charge pump circuit 120 is greater than the oscillation frequency in other states, which means that the frequency of the first oscillation clock signal is increased when the capacitor in the first charge pump circuit 120 starts to charge, and the first oscillation clock signal is restored to the original frequency when the capacitor in the first charge pump circuit 120 is about to be full or charging is completed. In this way, the charging speed of the capacitor in the first charge pump circuit 120 can be faster, so that the first switch transistor 130 can be turned on quickly.

[0062] In some embodiments, the first switch transistor 130 is an NMOS tube. The first switch transistor 130 can also be other N-type field effect tubes, which are not limited here.

[0063] In the embodiments of the present disclosure, the first charge pump circuit 120 also receives a voltage of a preset power supply (not shown), and the voltage output by the preset power supply is equal to a preset difference value; the first charge pump circuit 120 can be a QPUMP (gate drive charge pump), which is configured to input, to the gate end of the first switch transistor 130, the voltage of the preset power supply after lifting processing, so that the voltage difference between the second end of the first switch transistor 130 and the voltage of the gate end thereof is the preset difference value. For example, the preset difference value can be 5V, and in actual implementation, the preset difference value can also be other values that can enable the first switch transistor 130 to be turned on, such as 6V, 6.5V, 7V, etc.

[0064] It should be noted that, since a certain start-up time is required for the voltage stabilizing circuit (for example, a low-dropout linear voltage regulator), the voltage stabilizing circuit connected between the preset power supply and the first switch transistor 130 is removed in the embodiment of the present disclosure, so as to speed up the time for turning on the first switch transistor 130; accordingly, only the first charge pump circuit 120 is arranged between the preset power supply and the first switch transistor 130 for turning on the first switch transistor 130, that is, the first charge pump circuit 120 can achieve the voltage boosting requirement for turning on the first switch transistor 130. Further, in order to compensate for the voltage fluctuation caused by reducing the voltage stabilizing circuit, on one hand, the power (i.e., current) of the preset power supply can be increased to compensate, so that the first charge pump circuit 120 is filled with electricity faster to reach a stable state; on the other hand, the capacitance in the first charge pump circuit 120 can also be increased to stabilize the voltage in the first charge pump circuit 120.

[0065] In the embodiment of the present disclosure, since the voltage of the preset power supply is lifted by the first charge pump circuit 120, the voltage at the gate terminal of the first switch transistor is high, so the first switch transistor 130 in the high-side switch circuit 100 can use an NMOS tube with small volume and stable switching resistance as a high-side switch, so as to reduce the area of the high-side switch circuit 100.

[0066] In addition, since the first oscillation clock signal has a high frequency at the initial state of charging of the first charge pump circuit 120, the charging speed of the first charge pump circuit 120 is fast, so that the first switch transistor 130 can be turned on quickly, and the response speed of the first switch transistor 130 is high.

[0067] Next, please refer to Figure 4 to Figure 8 The high-side switch circuit 100 provided by the embodiment of the present disclosure is further described.

[0068] In some embodiments, please refer to Figure 4 and Figure 5The first frequency modulation circuit 110 comprises a first control circuit 111 and a first oscillator 112. The first end of the first control circuit 111 receives a first initial adjustment signal EN Fre ctrl<0>, the second end of the first control circuit 111 is connected with the first end of the first oscillator 112, and the second end of the first oscillator 112 is connected with the control end of the first charge pump circuit 120. The first control circuit 111 is configured to perform first preprocessing on the first initial adjustment signal EN Fre ctrl<0> to generate a first adjustment signal Fast<0>. The first preprocessing is to convert the first adjustment signal Fast<0> from a second level state to a first level state and maintain the first level state for a first preset time when the first initial adjustment signal EN Fre ctrl<0> is converted from the second level state to the first level state. The first oscillator 112 is configured to generate a first oscillation clock signal CLK<0> under the control of the first adjustment signal. The oscillation frequency of the first oscillation clock signal CLK<0> when the first adjustment signal Fast<0> is in the first level state is greater than the oscillation frequency when the first adjustment signal is in the second level state.

[0069] Here, the first adjustment signal can be denoted as Fast<0>. The first control circuit 111 can be an oscillator frequency control module Fre_Ctrl, and the first oscillator 112 can be an oscillator (OSC). The first preset time can be set according to actual needs, and the present disclosure is not limited thereto.

[0070] In the embodiments of the present disclosure, please continue to refer to Figure 4 and Figure 5 When the first initial adjustment signal EN Fre ctrl<0> received by the first control circuit 111 is converted from the second level state to the first level state, it indicates that the first switch transistor 130 is turned on, and the first control circuit 111 outputs the first adjustment signal Fast<0>. The first adjustment signal Fast<0> is input into the first oscillator 112 to control the frequency response of the first oscillator 112, so that the oscillation frequency of the first oscillation clock signal CLK<0> output by the first oscillator 112 is higher when the first adjustment signal Fast<0> is in the first level state, thereby driving the first charge pump circuit 120 to open faster. When the first adjustment signal Fast<0> is in the second level state, the oscillation frequency of the first oscillation clock signal CLK<0> output by the first oscillator 112 returns to a lower frequency, thereby reducing the noise and electromagnetic interference caused by the clock frequency.

[0071] It should be noted that Figure 5 Only one pulse signal in the first initial adjustment signal EN Fre ctrl<0> is taken as an example for description, and the timing of the first initial adjustment signal EN Fre ctrl<0> can be referred toFigure 8 .

[0072] It should be further noted that the first level state is 1 (logic high level) and the second level state is 0 (logic low level); the first initial adjustment signal EN Fre ctrl<0> is in the first level state, i.e. the first initial adjustment signal EN Fre ctrl<0> is in the enabled state, and the first initial adjustment signal EN Fre ctrl<0> is in the second level state, i.e. the first initial adjustment signal EN Fre ctrl<0> is in the disabled state. For the "first level state" and "second level state" appearing in the subsequent description, they can be understood according to the above explanation.

[0073] In some embodiments, please refer to Figure 4 , the high-side switch circuit 100 further comprises a first body terminal switch circuit 160, the first end and the second end of the first body terminal switch circuit 160 are connected with the gate end and the second end of the first switch transistor 130 respectively. To ensure that the first switch transistor 130 can be reliably turned on and turned off.

[0074] It should be further noted that, in Figure 4 , the first power supply supplies power to the first switch transistor 130 through the port 141, and the load circuit is connected with the first switch transistor 130 through the port 152. In addition, the high-side switch circuit 100 further comprises a port GND and a port VBAT, and some devices in the high-side switch circuit 100 are grounded through the port GND and connected with a preset power supply through the port VBAT.

[0075] In some embodiments, please refer to Figure 6The high-side switch circuit 100 further comprises a second frequency modulation circuit 170, a second charge pump circuit 180 and a second switch transistor 190; a first end of the second frequency modulation circuit 170 receives a second initial adjustment signal, a second end of the second frequency modulation circuit 170 is connected with a control end of the second charge pump circuit 180, a first end of the second charge pump circuit 180 is connected with a gate end of the second switch transistor 190, a second end of the second charge pump circuit 180 and a second end of the second switch transistor 190 are both connected with an input end of a load circuit (not shown) through a port 152, and a first end of the second switch transistor 190 is connected with a second power supply (not shown) through a port 200; wherein: the second frequency modulation circuit 170 is configured to generate a second oscillation clock signal under control of the second initial adjustment signal; an oscillation frequency of the second oscillation clock signal in a starting state of the second charge pump circuit is greater than oscillation frequencies in other states; and the second charge pump circuit 180 is configured to adjust a gate end voltage of the second switch transistor 190 according to a voltage feedback of a second end of the second switch transistor 190 under control of the second oscillation clock signal, so that a difference between the gate end voltage of the second switch transistor 190 and the voltage of the second end of the second switch transistor 190 is a preset difference, to turn on the second switch transistor 190.

[0076] Here, the second initial adjustment signal can be represented as EN Fre ctrl<1>, and the second oscillation clock signal can be represented as CLK<1>.

[0077] It should be noted that the load circuit, the first power supply, the second power supply, the first frequency modulation circuit, the second frequency modulation circuit and the high-side switch circuit can also be all arranged on an IC, or part of them can be arranged on the IC, in which case no external interface is required for connection, and direct connection is possible.

[0078] In some embodiments, the second switch transistor 190 is an NMOS transistor; since the NMOS transistor has a higher carrier mobility characteristic, the high-side switch circuit can have stronger driving current capability, and the current density and efficiency are improved. In addition, the working mode of the second power supply includes an ET mode or an APT mode; wherein the working modes of the first power supply 140 and the second power supply are different. In this way, the power supply mode of the load circuit can be switched by the first switch transistor 130 and the second switch transistor 190, thereby widening the application scenarios of the high-side switch circuit 100.

[0079] In some embodiments, the second switch transistor 190 is similar in structure and function to the first switch transistor 130, and the second charge pump circuit 180 is similar in structure and function to the first charge pump circuit 120, which will not be described here.

[0080] In some embodiments, the second frequency modulation circuit 170 comprises a second control circuit 171 and a second oscillator 172; a first end of the second control circuit 171 receives a second initial adjustment signal EN Fre ctrl<1>, and a second end of the second control circuit 171 is connected to a first end of the second oscillator 172; a second end of the second oscillator 172 is connected to a first end of the second charge pump circuit 180; wherein: the second control circuit 171 is configured to perform a second preprocessing on the second initial adjustment signal EN Fre ctrl<1> to generate a second adjustment signal Fast<1>; the second preprocessing is to convert the second adjustment signal Fast<1> from a second level state to a first level state and maintain the second adjustment signal Fast<1> in the first level state for a second preset time when the second initial adjustment signal EN Fre ctrl<1> is converted from the second level state to the first level state; and the second oscillator 172 is configured to generate a second oscillation clock signal CLK<1> under the control of the second adjustment signal Fast<1>; the oscillation frequency of the second oscillation clock signal CLK<1> when the second adjustment signal Fast<1> is in the first level state is greater than the oscillation frequency of the second oscillation clock signal CLK<1> when the second adjustment signal Fast<1> is in the second level state.

[0081] Here, the second adjustment signal can be represented by Fast<1>. The second preset time can be set according to actual needs, and the present disclosure does not limit this.

[0082] It should be noted that the structures and functions of the first control circuit 111 and the second control circuit 171 are similar, and the structures and functions of the second oscillator 172 and the first oscillator 112 are similar, which will not be described here.

[0083] In some embodiments, please refer to Figure 6 and Figure 8 The high-side switch circuit 100 further comprises a logic control circuit 210; a first output end of the logic control circuit 210 is connected to the first end of the first control circuit 111, and a second output end of the logic control circuit 210 is connected to the first end of the second control circuit 171; wherein: the logic control circuit 210 is configured to receive a first adjustment control signal and a second adjustment control signal, and perform a logic processing on the first adjustment control signal and the second adjustment control signal to generate a first initial adjustment signal EN Fre ctrl<0> and a second initial adjustment signal EN Fre ctrl<1>; wherein, if the first adjustment control signal and the second adjustment control signal are both in a first level state, the first initial adjustment signal EN Fre ctrl<0> and the second initial adjustment signal EN Fre ctrl<1> are both in a second level state; otherwise, the first initial adjustment signal EN Fre ctrl<0> is the same as the first adjustment control signal, and the second initial adjustment signal EN Fre ctrl<1> is the same as the second adjustment control signal.

[0084] Here, the input signals of the logic control circuit 210 can be represented by CTRL IN<1:0>, which includes the first adjustment control signal CTRL IN<0> and the second adjustment control signal CTRL IN<1>.

[0085] In some embodiments, referring to Figure 6 the first output end of the logic control circuit 210 is further coupled with the third end of the first charge pump circuit 120, and the second output end of the logic control circuit 210 is further coupled with the third end of the second charge pump circuit 180; wherein: the first initial adjustment signal EN Fre ctrl<0> is further used for controlling the opening or closing of the first charge pump circuit 120, so as to control the conduction or closing of the first switch transistor 130; the second initial adjustment signal EN Fre ctrl<1> is further used for controlling the opening or closing of the second charge pump circuit 180, so as to control the conduction or closing of the second switch transistor 190.

[0086] It should be noted that the coupling of the first output end of the logic control circuit 210 with the first charge pump circuit 120 means that the first output end of the logic control circuit 210 can be directly connected with the first charge pump circuit 120, or indirectly connected with the first charge pump circuit 120, that is, the "coupling" includes two ways of direct connection or indirect connection. For the "coupling" appearing in the subsequent description, it can be understood according to the above explanation.

[0087] Further, by performing logic processing on the first control signal CTRL IN<0> and the second control signal CTRL IN<1> through the logic control circuit 210, in the case of indicating the conduction of the first switch transistor 130, the first initial adjustment signal EN Fre ctrl<0> in the enabled state and the second initial adjustment signal EN Fre ctrl<1> in the non-enabled state are generated; in the case of indicating the conduction of the second switch transistor 190, the second initial adjustment signal EN Frectrl<1> in the enabled state and the first initial adjustment signal EN Fre ctrl<0> in the non-enabled state are generated. It should be noted that when the high-side switch circuit does not have the second switch transistor 190, the control signal related to the second switch transistor 190 is omitted.

[0088] In some embodiments, referring to Figure 7The logic control circuit 210 comprises a first NOT gate 10, a second NOT gate 12, a first AND gate 11 and a second AND gate 13. The first input end of the first AND gate 11 is configured to receive a first adjustment control signal CTRL_IN<0>, the second input end of the first AND gate 11 is connected with the output end of the first NOT gate 10, and the output end of the first AND gate 11 outputs a first initial adjustment signal EN Fre ctrl<0>. The input end of the first NOT gate 10 is configured to receive a second adjustment control signal CTRL_IN<1>. The first input end of the second AND gate 13 is connected with the output end of the second NOT gate 12, the second input end of the second AND gate 13 is configured to receive the second adjustment control signal CTRL_IN<1>, and the output end of the second AND gate 13 outputs a second initial adjustment signal EN Frectrl<1>. The input end of the second NOT gate 12 is configured to receive the first adjustment control signal CTRL_IN<0>.

[0089] In the embodiments of the present disclosure, in order to avoid the problem that the first switch transistor 130 and the second switch transistor 190 are simultaneously turned on in the working process of the high-side switch circuit 100, resulting in excessive transient current and burning the load circuit. In some embodiments, please continue to refer to Figure 6The high-side switch circuit 100 further comprises a dead-time control circuit 220, the dead-time control circuit 220 comprising a first delay processing circuit 221 and a second delay processing circuit 222; a first end of the first delay processing circuit 221 is connected with the first output end of the logic control circuit 210, a second end of the first delay processing circuit 221 is connected with the third end of the first charge pump circuit 120, a first end of the second delay processing circuit 222 is connected with the second output end of the logic control circuit 210, a second end of the second delay processing circuit is connected with the third end of the second charge pump circuit 180; wherein: the first delay processing circuit 221 is used for receiving the first initial adjustment signal EN Fre ctrl<0> and performing delay logic processing on the first initial adjustment signal EN Fre ctrl<0> to generate the first control signal CTRL_OUT<0>; the second delay processing circuit 222 is used for receiving the second initial adjustment signal EN Fre ctrl<1> and performing delay logic processing on the second initial adjustment signal EN Fre ctrl<1> to generate the second control signal CTRL_OUT<1>; wherein, in the case that the first control signal CTRL_OUT<0> is in the enabled state, the first charge pump circuit 120 is turned on, and the first switch transistor 130 is turned on; in the case that the second control signal CTRL_OUT<1> is in the enabled state, the second charge pump circuit 180 is turned on, and the second switch transistor 190 is turned on; in the case that one of the first initial adjustment signal EN Fre ctrl<0> and the second initial adjustment signal EN Fre ctrl<1> changes from the second level state to the first level state, after a dead-time (DT), one of the first control signal CTRL_OUT<0> and the second control signal CTRL_OUT<1> changes from the second level state to the first level state.

[0090] In some embodiments, please continue to refer to Figure 7The first delay processing circuit 221 comprises a first delay unit 14 and a third AND gate 15, and the second delay processing circuit 222 comprises a second delay unit 16 and a fourth AND gate 17. The input end of the first delay unit 14 is configured to receive the first initial adjustment signal EN Fre ctrl<0>, the output end of the first delay unit 14 is connected to the first input end of the third AND gate 15, the second input end of the third AND gate 15 is configured to receive the first initial adjustment signal EN Fre ctrl<0>, and the output end of the third AND gate 15 outputs the first control signal CTRL_OUT<0>. The input end of the second delay unit 16 is configured to receive the second initial adjustment signal EN Fre ctrl<1>, the output end of the second delay unit 16 is connected to the second input end of the fourth AND gate 17, the first input end of the fourth AND gate 17 is configured to receive the second initial adjustment signal EN Fre ctrl<1>, and the output end of the fourth AND gate 17 outputs the second control signal CTRL_OUT<1>.

[0091] In the high-side switch circuit 100, the first switch transistor 130 and the second switch transistor 190 are included. In the working process of the high-side switch circuit 100, the first switch transistor 130 and the second switch transistor 190 are simultaneously turned on, which causes the transient current of the input load circuit 150 to be too large and the chip to be burned out. Therefore, the dead-time control circuit 220 is arranged to delay the first initial adjustment signal EN Fre ctrl<0> and / or the second initial adjustment signal EN Fre ctrl<1> and then transmit the first initial adjustment signal EN Fre ctrl<0> and / or the second initial adjustment signal EN Fre ctrl<1> to the first charge pump circuit 120 and the second charge pump circuit 190, respectively. In this way, the first switch transistor 130 and the second switch transistor 190 are prevented from being simultaneously turned on, and the reliability of the high-side switch circuit 100 is high.

[0092] In some embodiments, please continue to refer to Figure 6 The high-side switch circuit 100 further comprises a second bulk terminal switch circuit 161, and the first end and the second end of the second bulk terminal switch circuit 161 are connected to the gate end and the second end of the second switch transistor 190, respectively. The second bulk terminal switch circuit 161 is configured to control the bulk terminal of the second switch transistor 190 and ensure that the second switch transistor 190 is reliably turned on and turned off.

[0093] It should be noted that the first switch transistor 130 in the embodiments of the present disclosure can be a depletion-mode NMOS transistor or an enhancement-mode NMOS transistor, and the second switch transistor 190 can be a depletion-mode NMOS transistor or an enhancement-mode NMOS transistor. The manufacturing process of the depletion-mode NMOS transistor is simple. The switching speed of the enhancement-mode NMOS transistor is fast, and the driving capability is stronger. In practice, the first switch transistor 130 and the second switch transistor 190 can be selected according to the needs.

[0094] The high-side switch circuit provided in the embodiments of the present disclosure has the advantages of Figure 6 The high-side switch circuit shown in the aboveFigure 4 The high-side switch circuit in the embodiment is similar, and for technical features not disclosed in detail in the embodiment of the present disclosure, please refer to the above embodiments for understanding, which will not be described here.

[0095] In addition, the present disclosure also provides a radio frequency front-end system 300, please refer to Figure 9 , the radio frequency front-end system 300 includes: a high-side switch circuit 100, a power amplifier 151, an output matching circuit 310, a first filter 320, an antenna switch module (ASM) 330, a receiving component (RX component) 350 and a second filter 360.

[0096] Please continue to refer to Figure 9 , the first end of the power amplifier 151 is connected with the high-side switch circuit 100, and the working mode of the power supply of the power amplifier 151 is controlled by the high-side switch circuit 100 to be the ET mode or the APT mode; the input end of the power amplifier 151 is used for receiving a radio frequency input signal RF_in; and the output end of the power amplifier 151 is connected with the input end of the output matching circuit 310.

[0097] The output end of the output matching circuit 310 is connected with the input end of the first filter 320, and the output end of the first filter 320 is connected with the first input end of the antenna switch module 330.

[0098] The input end of the receiving component 350 receives a signal LNA_OUT output by a low noise amplifier LAN, the output end of the receiving component 350 is connected with the second filter 360, the output end of the second filter 360 is connected with the second input end of the antenna switch module 330, and the output end of the antenna switch module 330 is output to an antenna (ANT) through a port 360.

[0099] It should be noted that, Figure 9 the radio frequency front-end system 300 in the above embodiment is a simplified structure diagram, and in fact, the radio frequency front-end system 300 can be any circuit structure that can be implemented.

[0100] In the embodiment of the present disclosure, since the radio frequency front-end system 300 includes the high-side switch circuit 100 in the above embodiment, the working mode of the power supply of the radio frequency front-end system 300 can be switched to the ET mode or the APT mode through the high-side switch circuit 100, and at the same time, since the switching or starting speed of the switch transistor (i.e. the first switch transistor 130 and / or the second switch transistor 190) is relatively fast, the response speed of the radio frequency front-end system 300 is relatively high.

[0101] In several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are merely illustrative, for example, the division of units is merely a logical functional division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the various components shown or discussed.

[0102] The disclosed features in several method or structure embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or structure embodiments.

[0103] The above is only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A high-side switch circuit, characterized by, The high-side switch circuit comprises a first frequency modulation circuit, a first charge pump circuit and a first switch transistor; a first end of the first frequency modulation circuit receives a first initial adjustment signal, a second end of the first frequency modulation circuit is connected with a control end of the first charge pump circuit, a first end of the first charge pump circuit is connected with a gate end of the first switch transistor, a second end of the first charge pump circuit and a second end of the first switch transistor are both connected with an input end of a load circuit, and a first end of the first switch transistor is connected with a first power supply; wherein: The first frequency modulation circuit comprises a first control circuit and a first oscillator; a first end of the first control circuit receives the first initial adjustment signal, a second end of the first control circuit is connected with a first end of the first oscillator, and a second end of the first oscillator is connected with the control end of the first charge pump circuit; wherein: the first control circuit is used for performing first preprocessing on the first initial adjustment signal to generate a first adjustment signal; the first preprocessing is to convert the first adjustment signal from a second level state to a first level state and maintain the first adjustment signal for a first preset time when the first initial adjustment signal is converted from the second level state to the first level state; the first oscillator is used for generating a first oscillation clock signal under the control of the first adjustment signal; an oscillation frequency of the first oscillation clock signal when the first adjustment signal is in the first level state is greater than an oscillation frequency of the first oscillation clock signal when the first adjustment signal is in the second level state; The first charge pump circuit is used for adjusting a gate end voltage of the first charge pump circuit according to a voltage feedback of the second end of the first switch transistor under the control of the first oscillation clock signal, so that a difference between the gate end voltage of the first switch transistor and the voltage of the second end of the first switch transistor is a preset difference value, to turn on the first switch transistor.

2. The circuit of claim 1, wherein, The high-side switch circuit further comprises a second frequency modulation circuit, a second charge pump circuit and a second switch transistor; a first end of the second frequency modulation circuit receives a second initial adjustment signal, a second end of the second frequency modulation circuit is connected with a control end of the second charge pump circuit, a first end of the second charge pump circuit is connected with a gate end of the second switch transistor, a second end of the second charge pump circuit and a second end of the second switch transistor are both connected with the input end of the load circuit, and a first end of the second switch transistor is connected with a second power supply; wherein: The second frequency modulation circuit is used for generating a second oscillation clock signal under the control of the second initial adjustment signal; an oscillation frequency of the second oscillation clock signal in a starting state of the second charge pump circuit charging is greater than oscillation frequencies in other states; The second charge pump circuit is used for adjusting a gate end voltage of the second charge pump circuit according to a voltage feedback of the second end of the second switch transistor under the control of the second oscillation clock signal, so that a difference between the gate end voltage of the second switch transistor and the voltage of the second end of the second switch transistor is a preset difference value, to turn on the second switch transistor.

3. The circuit of claim 2, wherein, The second frequency modulation circuit comprises a second control circuit and a second oscillator; a first end of the second control circuit receives the second initial adjustment signal, and a second end of the second control circuit is connected with a first end of the second oscillator; and a second end of the second oscillator is connected with a control end of the second charge pump circuit; and wherein: The second control circuit is configured to perform second preprocessing on the second initial adjustment signal to generate a second adjustment signal; and the second preprocessing comprises converting the second adjustment signal from the second level state to the first level state and maintaining the second adjustment signal in the first level state for a second preset time when the second initial adjustment signal is converted from the second level state to the first level state. The second oscillator is configured to generate the second oscillation clock signal under the control of the second adjustment signal; and the oscillation frequency of the second oscillation clock signal when the second adjustment signal is in the first level state is greater than the oscillation frequency of the second oscillation clock signal when the second adjustment signal is in the second level state.

4. The circuit of claim 3, wherein, The high-side switch circuit further comprises a logic control circuit; a first output end of the logic control circuit is connected with a first end of the first control circuit, and a second output end of the logic control circuit is connected with a first end of the second control circuit; and wherein: The logic control circuit is configured to receive a first adjustment control signal and a second adjustment control signal, and perform logic processing on the first adjustment control signal and the second adjustment control signal to generate the first initial adjustment signal and the second initial adjustment signal; and wherein, if the first adjustment control signal and the second adjustment control signal are both in the first level state, the first initial adjustment signal and the second initial adjustment signal are both in the second level state; otherwise, the first initial adjustment signal is the same as the first adjustment control signal, and the second initial adjustment signal is the same as the second adjustment control signal.

5. The circuit of claim 4, wherein, The first output end of the logic control circuit is further coupled with a third end of the first charge pump circuit, and the second output end of the logic control circuit is further coupled with a third end of the second charge pump circuit; and wherein: The first initial adjustment signal is further configured to control the opening and closing of the first charge pump circuit. The second initial adjustment signal is further configured to control the opening and closing of the second charge pump circuit.

6. The circuit of claim 5, wherein, The high-side switch circuit further comprises a dead time control circuit, and the dead time control circuit comprises a first delay processing circuit and a second delay processing circuit; a first end of the first delay processing circuit is connected with a first output end of the logic control circuit, a second end of the first delay processing circuit is connected with a third end of the first charge pump circuit, a first end of the second delay processing circuit is connected with a second output end of the logic control circuit, and a second end of the second delay processing circuit is connected with a third end of the second charge pump circuit; and wherein: The first delay processing circuit is configured to receive the first initial adjustment signal and perform delay logic processing on the first initial adjustment signal to generate a first control signal. The second delay processing circuit is configured to receive the second initial adjustment signal and perform delay logic processing on the second initial adjustment signal to generate a second control signal. The second delay processing circuit is configured to receive the second initial adjustment signal and perform delay logic processing on the second initial adjustment signal to generate a second control signal. In a case where the first control signal is in an enabled state, the first charge pump circuit is turned on and the first switch transistor is turned on; in a case where the second control signal is in an enabled state, the second charge pump circuit is turned on and the second switch transistor is turned on; and in a case where one of the first initial adjustment signal and the second initial adjustment signal changes from the second level state to the first level state, one of the first control signal and the second control signal changes from the second level state to the first level state after a dead time interval.

7. The circuit of claim 6, wherein, The logic control circuit comprises a first NOT gate, a second NOT gate, a first AND gate and a second AND gate. The first input end of the first AND gate is configured to receive a first adjustment control signal, the second input end of the first AND gate is connected with the output end of the first NOT gate, and the output end of the first AND gate outputs the first initial adjustment signal; and the input end of the first NOT gate is configured to receive a second adjustment control signal. The first input end of the second AND gate is connected with the output end of the second NOT gate, the second input end of the second AND gate is configured to receive the second adjustment control signal, and the output end of the second AND gate outputs the second initial adjustment signal; and the input end of the second NOT gate is configured to receive the first adjustment control signal.

8. The circuit of claim 7, wherein, The first delay processing circuit comprises a first delay unit and a third AND gate, and the second delay processing circuit comprises a second delay unit and a fourth AND gate. The input end of the first delay unit is configured to receive the first initial adjustment signal, the output end of the first delay unit is connected with the first input end of the third AND gate, the second input end of the third AND gate is configured to receive the first initial adjustment signal, and the output end of the third AND gate outputs the first control signal. The input end of the second delay unit is configured to receive the second initial adjustment signal, the output end of the second delay unit is connected with the second input end of the fourth AND gate, the first input end of the fourth AND gate is configured to receive the second initial adjustment signal, and the output end of the fourth AND gate outputs the second control signal.

9. The circuit of any one of claims 2 to 8, characterized in that, The first switch transistor and the second switch transistor are both NMOS transistors. The working mode of the first power supply comprises an ET mode or an APT mode, and the working mode of the second power supply comprises an ET mode or an APT mode; and the working modes of the first power supply and the second power supply are different.

10. A radio frequency front-end system, characterized by The high-side switch circuit comprises the high-side switch circuit according to any one of claims 1 to 9.

Images