Efficient cross-coupling charge pump circuit

Abstract

The invention discloses an efficient cross-coupling charge pump circuit which comprises a booster circuit, a pump capacitor circuit, a transmission circuit and a clock control circuit. Wherein the booster circuit comprises a first parallel branch and a second parallel branch, the output end of the first parallel branch is connected with the first input end of the transmission circuit, the output end of the second parallel branch is connected with the second input end of the transmission circuit, and the clock control circuit is connected with the output ends of the first parallel branch and the second parallel branch through the pump capacitor circuit. And the input module is used for inputting first to fourth clock signals so as to control the on-off of an MOS tube in the booster circuit and the voltage level of the output end of the booster circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a highly efficient cross-coupled charge pump circuit. Background Art

[0002] Cross-coupled charge pump circuits can generate a voltage higher than the power supply voltage and are widely used in circuits such as memories, power management modules, and driver chips.

[0003] The cross-coupled charge pump circuit has two branches that alternately provide current. However, during the charge conversion process, the charge in the main path is shared due to the presence of the conduction device and the parasitic capacitance of the layout. In particular, the gate-source capacitance Cgs of the MOS tube has a greater impact, resulting in reduced conversion efficiency and affecting the output voltage.

[0004] In addition, at the moment of clock jump, because all MOS tubes are turned on, current reflux occurs, which reduces the output efficiency of the charge pump and the open-loop output voltage.

[0005] Therefore, it is necessary to propose an efficient cross-coupled charge pump circuit to reduce current reflux and solve the problem of reduced output efficiency caused by charge sharing of the gate-source capacitance of the MOS tube. Summary of the invention

[0006] The present invention provides an efficient cross-coupled charge pump circuit, which can effectively reduce current reflux and solve the problem of reduced output efficiency caused by charge sharing of gate-source capacitance of MOS tubes.

[0007] The technical solution of the present invention is as follows: A highly efficient cross-coupled charge pump circuit, comprising: A boost circuit, a pump capacitor circuit, a transmission circuit and a clock control circuit; wherein the input end of the boost circuit is connected to the power supply voltage for boosting the power supply voltage, the output end of the boost circuit is connected to the input end of the transmission circuit, the output end of the transmission circuit outputs the boosted voltage, and the clock control circuit is connected to the output end of the boost circuit through the pump capacitor circuit; The boost circuit includes a first parallel branch and a second parallel branch, wherein the output end of the first parallel branch is connected to the first input end of the transmission circuit, and the output end of the second parallel branch is connected to the second input end of the transmission circuit. The clock control circuit is connected to the output ends of the first parallel branch and the second parallel branch respectively through the pump capacitor circuit, and is used to input the first to fourth clock signals, thereby controlling the on and off of the MOS tube in the boost circuit and the voltage level of the output end of the boost circuit.

[0008] The pump capacitor circuit includes a first pump capacitor pair and a second pump capacitor pair, The output end of the first parallel branch is connected to the second end of the first pump capacitor pair, and the output end of the second parallel branch is also connected to the second end of the second pump capacitor pair. The first end of the first pump capacitor pair and the first end of the second pump capacitor pair are respectively connected to the clock control circuit, the clock control circuit inputs the first clock signal and the second clock signal through the first pump capacitor pair, and the clock control circuit inputs the third clock signal and the fourth clock signal through the second pump capacitor pair.

[0009] The first parallel branch includes a first NMOS transistor N0 and a second NMOS transistor N1. The sources of N0 and N1 are connected to the power supply voltage VIN, the drain of N0 and the gate of N1 are connected at a first node Netx, the drain of N1 and the gate of N0 are connected at a second node Nety, and the nodes Netx and Nety form the output end of the first parallel branch.

[0010] The first pump capacitor pair includes a first capacitor C1 and a second capacitor C2, The first node Netx is connected to the second end of the second capacitor C2, and the second node Nety is connected to the second end of the first capacitor C1. A first end of the first capacitor C1 is connected to the first clock signal CLKP_A, and a first end of the second capacitor C2 is connected to the second clock signal CLKPB_A.

[0011] The second parallel branch includes a third NMOS transistor N0A and a fourth NMOS transistor N1A. The sources of N0A and N1A are connected to the power supply voltage VIN, the drain of N0A and the gate of N1A are connected at a third node Netxa, the drain of N1A and the gate of NOA are connected at a fourth node Netya, and the nodes Netxa and Netya form the output end of the second parallel branch.

[0012] The second pump capacitor pair includes a third capacitor C3 and a fourth capacitor C4, The third node Netxa is connected to the second end of the fourth capacitor C4, and the fourth node Netya is connected to the second end of the third capacitor C3. A first end of the third capacitor C3 is connected to the third clock signal CLKP_AB, and a first end of the fourth capacitor C4 is connected to the fourth clock signal CLKPB_AB.

[0013] The transmission circuit includes a first PMOS tube P2 and a second PMOS tube P3. The source of P2 is connected to the first node Netx, and the source of P3 is connected to the second node Nety. The gate of P2 is connected to the fourth node Netya, and the gate of P3 is connected to the third node Netxa. The drain of P2 is connected to the drain of P3 and serves as the output end of the transmission circuit.

[0014] The clock control circuit includes a non-overlapping clock circuit and four inverters. The clock source Clock is input into the non-overlapping clock circuit to generate two clock signals CLKP and CLKPB with opposite phases. The clock signals CLKP and CLKPB pass through two inverters respectively to generate a third clock signal CLKP_AB, a first clock signal CLKP_A, a fourth clock signal CLKPB_AB and a second clock signal CLKPB_A in sequence.

[0015] The non-overlapping clock circuit includes a first inverter, a first NAND gate, a second NAND gate, a first delay device, a second delay device, a second inverter and a third inverter. The clock source Clock is input to the input end of the first inverter and the first input end of the first NAND gate, the output end of the first inverter is connected to the first input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the second delay device, the output end of the first NAND gate is connected to the input end of the first delay device, the output end of the first delay device is connected to the second input end of the second NAND gate and the input end of the second inverter, and the output end of the second delay device is connected to the second input end of the first NAND gate and the input end of the third inverter.

[0016] The output end of the second inverter is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the third inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the input end of the seventh inverter. The output end of the fourth inverter outputs the third clock signal CLKP_AB, the output end of the fifth inverter outputs the first clock signal CLKP_A, the output end of the sixth inverter outputs the fourth clock signal CLKPB_AB, and the output end of the seventh inverter outputs the second clock signal CLKPB_A.

[0017] The present invention can solve the problem of reducing output efficiency due to charge sharing of the main path by the gate-source capacitance Cgs of the MOS tube by adding a parallel driving circuit. The non-overlapping clock circuit of the present invention can effectively reduce the current reflux problem from output to input. The implementation circuit of the present invention is simple and easy to implement, and is convenient for low-cost integration.

[0018] The features and advantages of the present invention will become clear through reference to the following drawings and detailed description of specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A circuit diagram of a conventional cross-coupled charge pump circuit is shown.

[0020] Figure 2 A circuit diagram of a cross-coupled charge pump circuit of the present invention is shown.

[0021] Figure 3 The output waveform timing diagram of the non-overlapping clock circuit of the present invention is shown. DETAILED DESCRIPTION

[0022] In order to make the technical solution of the present invention clearer and more understandable, it will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Figure 1 A circuit diagram of a conventional cross-coupled charge pump circuit is shown.

[0023] In the traditional cross-coupled charge pump circuit, MOS tubes N0 and P2 and N1 and P3 respectively form two inverters, and their inputs and outputs are coupled. It is necessary to consider the parasitic capacitance Cpar on nodes Netx and Nety. For example, Cpar on Nety is mainly affected by the gate-source capacitance Cgs of N0 and P2. Since the output on-resistance is small, Cgs of P2 is the main factor. Since the charge of the main path is shared by Cgs of P2, the voltage of nodes Netx and Nety swings between VIN and VIN+VIN×C1 / (C1+Cpar) under the action of the first capacitor C1 and the second capacitor C2 and the clocks CLK1N and CLK1P, so the output voltage is low, resulting in reduced conversion efficiency. On the other hand, at the moment of clock signal jump, MOS tubes N0 and P2 and N1 and P3 will be turned on briefly, and current will flow back from VOUT to VIN, increasing the power consumption of the clock circuit, resulting in reduced charge pump efficiency and increased output voltage ripple.

[0024] Figure 2 A circuit diagram of a cross-coupled charge pump circuit of the present invention is shown.

[0025] The cross-coupled charge pump circuit of the present invention comprises a boost circuit, a pump capacitor circuit, a transmission circuit and a clock control circuit. The input end of the boost circuit is connected to the power supply voltage for boosting the power supply voltage, the output end of the boost circuit is connected to the input end of the transmission circuit, and the output end of the transmission circuit outputs the boosted voltage. The clock control circuit is connected to the output end of the boost circuit through the pump capacitor circuit, and is used to provide a clock signal to control the on and off of the MOS tube in the boost circuit and the voltage level of the output end of the boost circuit.

[0026] The boost circuit includes a first parallel branch and a second parallel branch. The output end of the first parallel branch is connected to the first input end of the transmission circuit, and the output end of the second parallel branch is connected to the second input end of the transmission circuit. The clock control circuit is connected to the output ends of the first parallel branch and the second parallel branch respectively through the pump capacitor circuit, and is used to input the first to fourth clock signals, thereby controlling the on and off of the MOS tube in the boost circuit and the voltage level of the output end of the boost circuit. Specifically, the pump capacitor circuit includes a first pump capacitor pair and a second pump capacitor pair, the output end of the first parallel branch is also connected to the second end of the first pump capacitor pair, and the output end of the second parallel branch is also connected to the second end of the second pump capacitor pair. The first end of the first pump capacitor pair and the first end of the second pump capacitor pair are respectively connected to the clock control circuit, the clock control circuit inputs the first clock signal and the second clock signal through the first pump capacitor pair, and the clock control circuit inputs the third clock signal and the fourth clock signal through the second pump capacitor.

[0027] The first parallel branch includes a first NMOS tube N0 and a second NMOS tube N1. The sources of N0 and N1 are connected to the power supply voltage VIN, the drain of N0 and the gate of N1 are connected to the first node Netx, the drain of N1 and the gate of N0 are connected to the second node Nety, and the nodes Netx and Nety form the output end of the first parallel branch. The first pump capacitor pair includes a first capacitor C1 and a second capacitor C2. The first node Netx is connected to the second end of the second capacitor C2, and the second node Nety is connected to the second end of the first capacitor C1. The first end of the first capacitor C1 is connected to the first clock signal CLKP_A, and the first end of the second capacitor C2 is connected to the second clock signal CLKPB_A.

[0028] The second parallel branch includes a third NMOS tube N0A and a fourth NMOS tube N1A. The sources of N0A and N1A are connected to the power supply voltage VIN, the drain of N0A and the gate of N1A are connected at the third node Netxa, the drain of N1A and the gate of N0A are connected at the fourth node Netya, and the nodes Netxa and Netya form the output end of the second parallel branch. The second pump capacitor pair includes a third capacitor C3 and a fourth capacitor C4. The third node Netxa is connected to the second end of the fourth capacitor C4, and the fourth node Netya is connected to the second end of the third capacitor C3. The first end of the third capacitor C3 is connected to the third clock signal CLKP_AB, and the first end of the fourth capacitor C4 is connected to the fourth clock signal CLKPB_AB.

[0029] The transmission circuit includes a first PMOS tube P2 and a second PMOS tube P3. The source of P2 is connected to the first node Netx, and the source of P3 is connected to the second node Nety. The gate of P2 is connected to the fourth node Netya, and the gate of P3 is connected to the third node Netxa. The drain of P2 is connected to the drain of P3, serving as the output terminal VOUT of the transmission circuit.

[0030] The clock control circuit includes a non-overlapping clock circuit and four inverters. The clock source Clock is input into the non-overlapping clock circuit to generate two clock signals CLKP and CLKPB with opposite phases. The clock signals CLKP and CLKPB pass through two inverters respectively to generate the third clock signal CLKP_AB, the first clock signal CLKP_A, the fourth clock signal CLKPB_AB and the second clock signal CLKPB_A in sequence.

[0031] The non-overlapping clock circuit includes a first inverter, a first NAND gate, a second NAND gate, a first delay, a second delay, a second inverter and a third inverter. The clock source Clock is input to the input end of the first inverter and the first input end of the first NAND gate, the output end of the first inverter is connected to the first input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the second delay, the output end of the first NAND gate is connected to the input end of the first delay, the output end of the first delay is connected to the second input end of the second NAND gate and the input end of the second inverter, and the output end of the second delay is connected to the second input end of the first NAND gate and the input end of the third inverter. The output end of the second inverter outputs a clock signal CLKP, and the output end of the third inverter outputs a clock signal CLKPB.

[0032] The output end of the second inverter is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the third inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the input end of the seventh inverter. The output end of the fourth inverter outputs the third clock signal CLKP_AB, the output end of the fifth inverter outputs the first clock signal CLKP_A, the output end of the sixth inverter outputs the fourth clock signal CLKPB_AB, and the output end of the seventh inverter outputs the second clock signal CLKPB_A.

[0033] The output waveform of the non-overlapping clock circuit of the present invention is as follows: Figure 3 shown.

[0034] When Clock is high, CLKP_A is high, and the node Nety is charged to the voltage VIN+VIN×C1 / (C1+Cpar) through the first capacitor C1. The first capacitor C1 is integrated inside the chip and is limited by the working clock and cannot be too large. At this time, the parasitic capacitor Cpar lacks the largest parasitic capacitor, namely the gate-source capacitor Cgs of P2, compared with the traditional circuit. Therefore, the voltage of the node Nety can be approximately 2×VIN, which greatly improves the charging efficiency. Similarly, when Clock is low, the other node Netx can also be charged to a voltage of approximately 2×VIN.

[0035] When Clock is at a low level, CLKPB_AB is at a low level, the voltage of the node Netxa is VIN, and the voltage of the node Netx is about 2×VIN. P2 is turned on, and outputs voltage to the output terminal VOUT through charge transfer. In the actual implementation sequence, since the dead time relationship can be realized, when P2 starts to turn on and output voltage to the output terminal VOUT, N0 has been closed in advance, thereby preventing the current from the output terminal VOUT to the input terminal VIN from flowing back. Similarly, when the other MOS tube P3 is turned on, the dead time relationship can also be realized, and the current from the output terminal VOUT to the input terminal VIN can also be prevented from flowing back.

[0036] Compared with the prior art, in the cross-coupled charge pump circuit of the present invention, MOS tubes N0A and N1A and the third capacitor C3 and the fourth capacitor C4 are added as corresponding parallel circuits, which can effectively solve the influence of the gate-source capacitance Cgs of the MOS tubes P2 and P3, so that the voltage of the nodes Netx and Nety swings between VIN and 2×VIN under the action of the first capacitor C1 and the second capacitor C2 and the clock signals CLKP_A and CLKPB_A. At the same time, the timing generated by the non-overlapping clock circuit can avoid the current backflow from VOUT to VIN, reduce the power consumption of the clock circuit, improve the efficiency of the charge pump, and reduce the output voltage ripple.

[0037] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. An efficient cross-coupled charge pump circuit, comprising: A boost circuit, a pump capacitor circuit, a transmission circuit and a clock control circuit; wherein the input end of the boost circuit is connected to the power supply voltage for boosting the power supply voltage, the output end of the boost circuit is connected to the input end of the transmission circuit, the output end of the transmission circuit outputs the boosted voltage, and the clock control circuit is connected to the output end of the boost circuit via the pump capacitor circuit; characterized in that: The boost circuit includes a first parallel branch and a second parallel branch, wherein the output end of the first parallel branch is connected to the first input end of the transmission circuit, and the output end of the second parallel branch is connected to the second input end of the transmission circuit. The clock control circuit is connected to the output ends of the first parallel branch and the second parallel branch respectively through the pump capacitor circuit, and is used to input the first to fourth clock signals, thereby controlling the on and off of the MOS tube in the boost circuit and the voltage level of the output end of the boost circuit.

2. The cross-coupled charge pump circuit according to claim 1, wherein: The clock control circuit is connected to the output ends of the first parallel branch and the second parallel branch respectively through a pump capacitor circuit, and includes: The pump capacitor circuit includes a first pump capacitor pair and a second pump capacitor pair, The output end of the first parallel branch is connected to the second end of the first pump capacitor pair, and the output end of the second parallel branch is also connected to the second end of the second pump capacitor pair. The first end of the first pump capacitor pair and the first end of the second pump capacitor pair are respectively connected to the clock control circuit, the clock control circuit inputs the first clock signal and the second clock signal through the first pump capacitor pair, and the clock control circuit inputs the third clock signal and the fourth clock signal through the second pump capacitor pair.

3. The cross-coupled charge pump circuit according to claim 2, wherein: The first parallel branch includes a first NMOS transistor N0 and a second NMOS transistor N1. The sources of N0 and N1 are connected to the power supply voltage VIN, the drain of N0 and the gate of N1 are connected at a first node Netx, the drain of N1 and the gate of N0 are connected at a second node Nety, and the nodes Netx and Nety form the output end of the first parallel branch.

4. The cross-coupled charge pump circuit according to claim 3, characterized in that: The first pump capacitor pair includes a first capacitor C1 and a second capacitor C2, The first node Netx is connected to the second end of the second capacitor C2, and the second node Nety is connected to the second end of the first capacitor C1. A first end of the first capacitor C1 is connected to the first clock signal CLKP_A, and a first end of the second capacitor C2 is connected to the second clock signal CLKPB_A.

5. The cross-coupled charge pump circuit according to claim 4, characterized in that: The second parallel branch includes a third NMOS transistor N0A and a fourth NMOS transistor N1A. The sources of N0A and N1A are connected to the power supply voltage VIN, the drain of N0A and the gate of N1A are connected at a third node Netxa, the drain of N1A and the gate of NOA are connected at a fourth node Netya, and the nodes Netxa and Netya form the output end of the second parallel branch.

6. The cross-coupled charge pump circuit according to claim 5, characterized in that: The second pump capacitor pair includes a third capacitor C3 and a fourth capacitor C4, The third node Netxa is connected to the second end of the fourth capacitor C4, and the fourth node Netya is connected to the second end of the third capacitor C3. A first end of the third capacitor C3 is connected to the third clock signal CLKP_AB, and a first end of the fourth capacitor C4 is connected to the fourth clock signal CLKPB_AB.

7. The cross-coupled charge pump circuit according to claim 6, wherein: The transmission circuit includes a first PMOS transistor P2 and a second PMOS transistor P3. The source of P2 is connected to the first node Netx, and the source of P3 is connected to the second node Nety. The gate of P2 is connected to the fourth node Netya, and the gate of P3 is connected to the third node Netxa. The drain of P2 is connected to the drain of P3 and serves as the output end of the transmission circuit.

8. The cross-coupled charge pump circuit according to claim 7, wherein: The clock control circuit includes a non-overlapping clock circuit and four inverters. The clock source Clock is input into the non-overlapping clock circuit to generate two clock signals CLKP and CLKPB with opposite phases. The clock signals CLKP and CLKPB pass through two inverters respectively to generate a third clock signal CLKP_AB, a first clock signal CLKP_A, a fourth clock signal CLKPB_AB and a second clock signal CLKPB_A in sequence.

9. The cross-coupled charge pump circuit according to claim 8, characterized in that: The non-overlapping clock circuit includes a first inverter, a first NAND gate, a second NAND gate, a first delay device, a second delay device, a second inverter and a third inverter. The clock source Clock is input to the input end of the first inverter and the first input end of the first NAND gate, the output end of the first inverter is connected to the first input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the second delay device, the output end of the first NAND gate is connected to the input end of the first delay device, the output end of the first delay device is connected to the second input end of the second NAND gate and the input end of the second inverter, and the output end of the second delay device is connected to the second input end of the first NAND gate and the input end of the third inverter.

10. The cross-coupled charge pump circuit according to claim 9, wherein: The output end of the second inverter is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the third inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the input end of the seventh inverter. The output end of the fourth inverter outputs the third clock signal CLKP_AB, the output end of the fifth inverter outputs the first clock signal CLKP_A, the output end of the sixth inverter outputs the fourth clock signal CLKPB_AB, and the output end of the seventh inverter outputs the second clock signal CLKPB_A.

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