Digital load current estimation method applied to buck power supply

Abstract

The invention discloses a digital load current estimation method applied to a buck power supply. A power level module, an ADC voltage sampling module, a switch node voltage comparator, a switch period counting module and a digital filter module are included. The ADC voltage sampling module quantizes analog quantity of input voltage and output voltage of the power level module into input voltage digital quantity and output voltage digital quantity which serve as input parameters of the digital filter module. The switch node voltage comparator compares the switch node voltage of the power level module with a constant direct current voltage to obtain a switch pulse signal, and duty ratio information of a switch pulse is obtained through the switch period counting module and serves as an input parameter of the digital filter module; the digital filter module pre-estimates inductive current according to the input voltage digital quantity, the output voltage digital quantity and duty ratio information, pre-estimates capacitive current according to the output voltage digital quantity, obtains an expression of load current in a z domain, and discretizes the expression through bilinear transformation.

Description

Technical Field

[0001] The invention belongs to the field of switching power supplies, and in particular relates to a digital load current estimation method applied to a buck power supply. Background Art

[0002] In recent years, in order to further reduce the power consumption of microprocessors and enhance their computing power, the power supply requirements of microprocessors have developed towards low voltage and high current. Therefore, low-voltage and high-current Buck converters have gradually become one of the research hotspots. As the power supply of microprocessors, when a large current step change occurs, low-voltage and high-current Buck converters must maintain low output voltage and good dynamic performance within a strict voltage window tolerance. In addition, as the output voltage continues to decrease, how to reduce the output voltage window tolerance has also become an important challenge for low-voltage and high-current Buck converters.

[0003] However, the transient current of the Buck converter can often reach tens or even hundreds of amperes when switching loads. At such a low operating voltage, the window tolerance of voltage changes will become smaller, making the chip more prone to failure during load current transients. When the load is switched from light load to heavy load, since the inductor current cannot increase immediately, the voltage on the output capacitor needs to provide some energy for the load, which will cause the output voltage to decrease; at the same time, when the heavy load is switched to the light load, the inductor current cannot be reduced immediately, so it must use some energy to charge the output capacitor, thereby increasing the output voltage. The traditional output voltage operating point is fixed. When the light load is switched to the heavy load, it takes a while to restore the dropped output voltage to the set reference voltage value, and when the heavy load is switched to the light load, it takes a while to restore the overshoot voltage to the set fixed voltage value. In this way, the system can only use half of the range of the output voltage variable window. When meeting the output voltage regulation performance, a large output capacitor is required, and the response time is still very slow, and the dynamic performance becomes very poor. Therefore, improving the dynamic performance of the Buck converter is of great significance to the research of the Buck converter power supply system.

[0004] AVP control technology can make full use of the voltage window tolerance specified in the standard, improve the dynamic characteristics of the system, reduce the requirements for output filter capacitors, and reduce the size and cost of the converter. The principle is to control the output voltage level based on the load current being higher than the minimum value when heavily loaded and lower than the maximum value when lightly loaded, and then build a voltage tolerance window. AVP control technology enables the voltage tolerance window to be fully utilized, and is more suitable for research on reducing the output voltage window tolerance and improving the dynamic performance of the Buck converter. However, AVP control technology requires sampling of the output voltage and output current, and for traditional Rdroop resistor sampling, this method brings additional power loss and affects efficiency; or requires a wideband amplifier, which is very demanding for CMOS production. In addition, the current information required for AVP control of existing methods mostly uses inductor current, and the inductor current cannot change immediately in transient state, so there are certain efficiency issues in using inductor current to achieve AVP control. Summary of the invention

[0005] The purpose of the present invention is to provide a digital load current estimation method applied to a buck power supply, in order to improve the regulation capability of AVP and provide load current information for AVP control, so as to solve the technical problems mentioned in the background technology.

[0006] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0007] A digital load current estimation method applied to a buck power supply, characterized by comprising a power stage module, an ADC voltage sampling module, a switch node voltage comparator, a switch cycle counting module, and a digital filter module;

[0008] The power stage module includes two switch tubes MOS1 and MOS2, an ideal filter inductor L and its equivalent series resistance R L , ideal filter capacitor C and its equivalent series resistance R C and equivalent series inductance L C MOS1 source connected to input voltage V in MOS1 drain is connected to MOS2 source, the connection point between MOS1 drain and MOS2 source is the switch node of the power stage module, MOS2 drain is grounded, ideal filter inductor L and equivalent series resistance R L connected in series between the switch node and the output voltage V out The two ends of the ideal filter capacitor C and the equivalent series resistance R C , equivalent series inductance L C In series with the output voltage V out and between the earth;

[0009] The ADC voltage sampling module quantizes the analog quantities of the input voltage and output voltage of the power stage module into digital quantities of input voltage and output voltage as input parameters of the digital filter module;

[0010] The switch node voltage comparator is an analog input and digital output comparator that compares the switch node voltage of the power stage module with the constant DC voltage to obtain the actual switch pulse signal, and obtains the duty cycle information of the switch pulse through the switch cycle counting module as the input parameter of the digital filter module;

[0011] The digital filter module estimates the inductor current according to the input voltage digital quantity, the output voltage digital quantity and the duty cycle information, and estimates the capacitor current according to the output voltage digital quantity. On this basis, the expression of the load current in the z domain is obtained and discretized through bilinear transformation.

[0012] Furthermore, the switching cycle counting module counts a fixed period T through a high frequency counter. s The number of times the internal switch signal SW is 1, and the duty cycle d is output once in each cycle. The switching cycle counting module calculates more accurate duty cycle d information through a delay line-based structure, thereby obtaining more accurate inductor current information, including average value and peak-to-peak value.

[0013] Furthermore, the load current is expressed as the difference between the inductor current and the capacitor current. The load current estimation consists of the inductor current estimation and the capacitor current estimation. Both estimations are implemented by the digital controller. In a multi-phase system, i L It is represented as the sum of the inductor currents of each phase, SW represents the staggered switch node signal; the staggered switch node signal SW is obtained by performing a logical OR operation on the switch node signals SW1 to SWN of each phase, so as to estimate the sum of the inductor currents when multiple phases are staggered; the estimated inductor current is shown in formula (1), where V L The switch node V SW With output voltage V out The voltage difference between the two, k represents the kth estimated cycle, and r is the on-resistance of the switch tube and the equivalent series resistance R L The sum of: I L_est (k) = -D 3 i L_est (k-1)+N 2 [V L (k)+V L (k-1)] (1).

[0014] Furthermore, the digital filter module is designed based on bilinear transformation. By designing the z-domain expression of the inductor current and capacitor current transfer function, the digital controller is realized. First, the current is converted from the time domain to the s-domain expression through Laplace transformation, and then converted to the z-domain expression through bilinear transformation to achieve continuous time discretization. The expression of the load current in the z-domain is shown in formula (2), where r is the on-resistance of the switch tube and R L The sum of:

[0015]

[0016] A digital load current estimation method applied to a buck power supply of the present invention has the following advantages:

[0017] 1. The method of the present invention is pure digital control, which only samples the voltage signal and does not require a complex current sampling circuit, thus greatly reducing the cost of current sampling.

[0018] 2. During loop control, the current inner loop is not required, and the entire loop bandwidth only depends on the voltage loop, which can achieve high-bandwidth control.

[0019] 3. The digital prediction method of the present invention is insensitive to sampling noise, and the loop control is more stable.

[0020] 4. The present invention directly uses the load current as current information instead of inductor current feedback, thereby improving the transient speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a system structure block diagram of the buck power supply digital load current estimation method of the present invention;

[0022] Figure 2 The present invention samples the switch node voltage through the analog input and digital output comparator;

[0023] Figure 3 It is a circuit structure diagram of the load current estimation concept of the present invention;

[0024] Figure 4 It is a waveform diagram of the load current estimation concept of the present invention;

[0025] Figure 5 is a functional block diagram of a high-resolution duty cycle sampling method based on a delay line of the present invention;

[0026] Figure 6 is a block diagram of a digital filter of the present invention;

[0027] FIG7( a ) is a test diagram of the output voltage and the actual current and the estimated current when switching from light load to heavy load;

[0028] FIG7( b ) is a test diagram of the output voltage and the actual current and the estimated current when the heavy load is switched to the light load. DETAILED DESCRIPTION

[0029] In order to better understand the purpose, structure and function of the present invention, a digital load current estimation method applied to a buck power supply of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0030] Figure 1 The system structure block diagram of the digital load current estimation method of the present invention applied in the Buck converter includes a power stage module, an ADC voltage sampling module, a switch node voltage comparator, a switch cycle counting module, and a digital filter module. Among them, the input voltage V in and output voltage V out After being processed by the ADC voltage sampling module, it is output to the digital filter module, and the switch node voltage V sw After a constant reference voltage of 1.25V is input to the switch node voltage comparator, it is output to the switch cycle calculation module, and then passed to the digital filter module for unified processing and calculation. The synchronous rectification Buck converter controls the duty cycle signal V of the switch node by controlling the on and off time of the upper switch MOS1 and the lower switch MOS2. sw , thereby controlling the output voltage. L is the filter inductance of the Buck converter, R L is the equivalent series resistance of the filter inductor, C is the ideal filter capacitor, R C is the series equivalent resistance of the filter capacitor. In order to predict more accurate information, the equivalent series inductance (ESL) of the capacitor is considered when designing the digital filter. C .L C is the equivalent series inductance of the filter capacitor. The input voltage V of the ADC voltage sampling module input buck power supply in and output voltage V out , converts the analog voltage into a digital quantity and transmits it to the digital filter. The switch node voltage V sw The actual switch signal SW is output by comparing the comparator with the reference voltage 1.25V. When the upper switch tube MOS1 is turned on and the lower switch tube MOS2 is turned off, the switch node voltage is approximately equal to V in , greater than the reference voltage 1.25V, the comparator outputs the switch signal SW as a high level. When the upper switch tube MOS1 is turned off and the lower switch tube MOS2 is turned on, the switch node voltage is approximately equal to 0V, less than the reference voltage 1.25V, and the comparator outputs the switch signal SW as a low level. The switching cycle counting module counts a fixed period T through a high-frequency counters The number of times the internal switch signal SW is 1, and the duty cycle d is output once in each cycle. The digital filter calculates and estimates the inductor current based on the digital information of the input voltage, output voltage and duty cycle, and estimates the capacitor current based on the output voltage. On this basis, the expression of the load current in the z domain is obtained and discretized through bilinear transformation.

[0031] Figure 2 The switch node voltage V is sampled by the analog input and digital output comparator. sw The analog input and digital output comparators are used to convert V sw The output signal SW is compared with a constant DC reference voltage of 1.25V, so that the output signal SW is a digital signal that is not affected by noise.

[0032] Figure 3 This is the circuit diagram of the load current estimation concept. Figure 4 The two figures clearly show the principle of load current estimation. The load current can be expressed as the difference between the inductor current and the capacitor current, which can be expressed as formula (1):

[0033] i out =i L -i C (1)

[0034] Among them, i out is the load current, i L is the inductor current, i C is the capacitor current. Therefore, the load current estimation consists of the inductor current estimation and the capacitor current estimation, both of which are realized by the digital controller. L It should be expressed as the sum of the inductor currents of each phase, and SW should represent the interleaved switch node signal. Therefore, the interleaved switch node signal SW is obtained by performing the OR logic on the switch node signals SW1 to SWN of each phase. This operation is performed in the digital controller, so that the sum of the inductor currents when multi-phase interleaving can be estimated. In the steady state, the average value of the inductor current is equal to the load current, and the average value of the capacitor current is 0, and the ripples of the two are offset. During the load transient process, the inductor current cannot change immediately, so the instant of the load step is presented by the capacitor current.

[0035] Figure 5 The functional block diagram of the high-resolution switching cycle counting module based on the delay line is shown in FIG. The switching cycle counting module counts a fixed period T through a high-frequency counter. sThe number of times the internal switch signal SW is 1, and the duty cycle d is output once in each cycle. It obtains more accurate information about the duty cycle d through calculation based on the delay line structure, thereby obtaining more accurate information about the inductor current, including the average value and peak-to-peak value. The digital filter is based on the input voltage V in , output voltage V out The inductor current is estimated by calculating the digital information of the duty cycle d, as shown in formula (2), where V L The switch node V SW With output voltage V out The voltage difference between the switch and R L The sum of:

[0036] I L_est (k) = -D 3 i L_est (k-1)+N 2 [V L (k)+V L (k-1)] (2).

[0037] Figure 6 The transfer function expression of capacitor current in s domain is C (s) is shown in equation (3). When estimating the inductor current and capacitor current, they are first discretized by bilinear transformation so that the digital filter design can be performed using the s-domain frequency response method. Based on equations (2) and (3), the expression of the load current in the z-domain is shown in equation (4).

[0038]

[0039]

[0040]

[0041] In equation (4), the first polynomial is the inductor current estimate, and the second polynomial is the capacitor current estimate. The expression of the load current in the z domain can be implemented in the digital controller.

[0042] Figure 7(a) and Figure 7(b) show the test diagrams of the actual load current and the estimated load current when a load transient occurs. Figure 7(a) shows the transient situation of light load switching to heavy load, and Figure 7(b) shows the transient situation of heavy load switching to light load. The blue waveform is the output voltage, the green waveform is the actual current, and the red waveform is the estimated current. It can be seen that the actual load current value can be restored through load current estimation.

[0043] The present invention can accurately estimate the real-time inductor current and capacitor current information and obtain the load current information by sampling only the input voltage and the output voltage. The present invention does not need to add additional analog sampling circuits such as resistors, capacitors, operational amplifiers, and high-speed ADC sampling far higher than the switching frequency, which greatly reduces the cost.

[0044] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A digital load current estimation method applied to a buck power supply, characterized in that: It includes a power stage module, an ADC voltage sampling module, a switch node voltage comparator, a switch cycle counting module, and a digital filter module; The power stage module includes two switch tubes MOS1 and MOS2, an ideal filter inductor L and its equivalent series resistance R L , ideal filter capacitor C and its equivalent series resistance R C and equivalent series inductance L C MOS1 source connected to input voltage V in MOS1 drain is connected to MOS2 source, the connection point between MOS1 drain and MOS2 source is the switch node of the power stage module, MOS2 drain is grounded, ideal filter inductor L and equivalent series resistance R L connected in series between the switch node and the output voltage V out The two ends of the ideal filter capacitor C and the equivalent series resistance R C , equivalent series inductance L C In series with the output voltage V out and between the earth; The ADC voltage sampling module quantizes the analog quantities of the input voltage and output voltage of the power stage module into digital quantities of input voltage and output voltage as input parameters of the digital filter module; The switch node voltage comparator is an analog input and digital output comparator that compares the switch node voltage of the power stage module with the constant DC voltage to obtain the actual switch pulse signal, and obtains the duty cycle information of the switch pulse through the switch cycle counting module as the input parameter of the digital filter module; The digital filter module estimates the inductor current according to the input voltage digital quantity, the output voltage digital quantity and the duty cycle information, and estimates the capacitor current according to the output voltage digital quantity. On this basis, the expression of the load current in the z domain is obtained and discretized through bilinear transformation.

2. The digital load current estimation method applied to a buck power supply according to claim 1, characterized in that: The switching cycle counting module counts a fixed period T through a high-frequency counter. s The number of times the internal switch signal SW is 1, and the duty cycle d is output once in each cycle.

3. The digital load current estimation method applied to a buck power supply according to claim 2, characterized in that: The load current is expressed as the difference between the inductor current and the capacitor current. The load current estimation consists of the inductor current estimation and the capacitor current estimation. Both estimations are implemented by the digital controller. In a multi-phase system, i L It is represented as the sum of the inductor currents of each phase, and SW represents the interleaved switch node signal; the interleaved switch node signal SW is obtained by performing a logical OR operation on the switch node signals SW1 to SWN of each phase, so as to estimate the sum of the inductor currents when multiple phases are interleaved; The estimated inductor current is shown in equation (1), where V L The switch node V SW With the output voltage V out The voltage difference between the two, k represents the kth estimated cycle, and r is the on-resistance of the switch tube and the equivalent series resistance R L The sum of: <h2 style=";text-align:left;direction:ltr">I<h2 style=";text-align:left;direction:ltr"> L_est <h2 style=";text-align:left;direction:ltr"> (k)=-D3i<h2 style=";text-align:left;direction:ltr"> L_est <h2 style=";text-align:left;direction:ltr"> (k-1)+N2[V<h2 style=";text-align:left;direction:ltr"> L <h2 style=";text-align:left;direction:ltr"> (k)+V<h2 style=";text-align:left;direction:ltr"> L <h2 style=";text-align:left;direction:ltr"> (k-1)] (1)。 4. The digital load current estimation method applied to a buck power supply according to claim 3, characterized in that: The digital filter module is designed based on bilinear transformation. The digital controller is realized by designing the z-domain expression of the transfer function of the inductor current and the capacitor current. First, the current is converted from the time domain to the s-domain expression through Laplace transformation, and then converted to the z-domain expression through bilinear transformation to achieve continuous time discretization. The expression of the load current in the z-domain is shown in formula (2), where

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