Power supply system circuit

Abstract

The invention provides a power supply system circuit which is provided with a power supply input end, a power supply output end, an LDO voltage transformation module and a DC-DC voltage transformation module, the DC-DC voltage transformation module comprises a shared capacitor circuit, and the LDO voltage transformation module is used for converting electric energy of the power supply input end into first voltage stabilization electric energy and outputting the first voltage stabilization electric energy to the power supply output end; the shared capacitor circuit is used for converting electric energy of the power supply input end into second voltage-stabilized electric energy and outputting the second voltage-stabilized electric energy to the power supply output end or filtering the first voltage-stabilized electric energy, and the power of the second voltage-stabilized electric energy is lower than that of the first voltage-stabilized electric energy; wherein the power supply input end is connected with the LDO voltage transformation module and the shared capacitance circuit, the power supply output end is connected with the LDO voltage transformation module and the shared capacitance circuit, the shared capacitance circuit is connected with the LDO voltage transformation module, and then the DC-DC voltage transformation module and the LDO voltage transformation module are integrated in a chip together based on the design mode of the built-in shared capacitance circuit. And therefore, high-efficiency power supply can be realized in a low-power-consumption light-load scene, and the hardware cost is saved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a power system circuit. Background Art

[0002] The power supply of integrated circuits usually requires a DC-DC transformer module or an LDO transformer module. Among them, the DC-DC transformer module has a higher efficiency, but since the inductors, capacitors and other components required by the DC-DC transformer module, if integrated into the chip, will occupy a huge area, generally the chip will not integrate a large inductor, so the application of DC-DC in integrated circuits is often in the form of external dedicated DC-DC chips and discrete inductors and capacitors in the PCB peripheral circuit, which increases the cost of peripheral hardware.

[0003] In addition, the power supply ripple of the LDO transformer module is small, and the application of on-chip LDO transformer modules without external capacitors in integrated circuits is already very common. However, the significant disadvantage of the LDO transformer module is its low efficiency. Especially in application scenarios where some devices switch to battery power after power failure and enter an ultra-low power standby mode, the power conversion efficiency becomes particularly important.

[0004] In existing integrated circuits, the operating voltage of low-voltage logic devices in 40nm process is generally 1.1V. If an LDO voltage conversion module is used to convert the 3.3V voltage into 1.1V to power the low-voltage logic, plus the static power consumption of the LDO itself, its efficiency value is less than 33%; if an external dedicated DC-DC chip is used for power supply, not only is the peripheral hardware cost high, but also when the standby power consumption is very low, the power consumption of the DC-DC chip itself may be even greater, and the purpose of high-efficiency energy saving cannot be achieved. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to propose a power supply system circuit that can achieve high-efficiency power supply in low-power and light-load application scenarios, and save the circuit layout area within the chip and the hardware cost of peripheral application circuits.

[0006] To achieve the above objectives, a first aspect of an embodiment of the present application provides a power system circuit, including: Power supply input terminal; Power supply output terminal; An LDO voltage conversion module, the LDO voltage conversion module is used to convert the electric energy at the power supply input end into the first voltage-stabilized electric energy and output it to the power supply output end; A DC-DC transformer module, the DC-DC transformer module includes a shared capacitor circuit, the shared capacitor circuit is used to convert the electric energy at the power supply input end into a second stabilized electric energy and output it to the power supply output end or filter the first stabilized electric energy, the power of the second stabilized electric energy is lower than the power of the first stabilized electric energy; Among them, the power supply input end is connected to the LDO transformer module and the shared capacitor circuit respectively, the power supply output end is connected to the LDO transformer module and the shared capacitor circuit respectively, and the shared capacitor circuit is connected to the LDO transformer module.

[0007] Furthermore, in some embodiments, the power system circuit further includes: A digital logic load module, wherein the input end of the digital logic load module is connected to the power supply output end, and the output end of the digital logic load module is grounded; An output capacitor, wherein an upper plate of the output capacitor is connected to the power supply output terminal, and a lower plate of the output capacitor is grounded; The output capacitor and the digital logic load module are connected in parallel, and the output capacitor is used to stabilize the voltage of the digital logic load module.

[0008] Further, in some embodiments, the shared capacitor circuit includes a first shared capacitor, a second shared capacitor, a third shared capacitor, a first MOS transistor, a second MOS transistor, and a third MOS transistor; Among them, the first pole of the first MOS tube is connected to the power supply input end, the second pole of the first MOS tube is connected to the upper plate of the first shared capacitor, the lower plate of the first shared capacitor is connected to the first pole of the second MOS tube, the second pole of the second MOS tube is connected to the upper plate of the second shared capacitor, the lower plate of the second shared capacitor is connected to the first pole of the third MOS tube, the first pole of the third MOS tube is connected to the upper plate of the third shared capacitor, and the lower plate of the third shared capacitor is grounded.

[0009] Furthermore, in some embodiments, the shared capacitor circuit further includes a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor; Among them, the first electrode of the fourth MOS tube, the first electrode of the fifth MOS tube, and the first electrode of the sixth MOS tube at the power supply output end are connected, the second electrode of the fourth MOS tube is connected to the upper plate of the first shared capacitor, the drain of the fifth MOS tube is connected to the upper plate of the second shared capacitor, the drain of the sixth MOS tube is connected to the upper plate of the third shared capacitor, the source of the seventh MOS tube is connected to the lower plate of the first shared capacitor, the source of the eighth MOS tube is connected to the lower plate of the second shared capacitor, the drain of the seventh MOS tube is grounded, and the drain of the eighth MOS tube is grounded.

[0010] Furthermore, in some embodiments, the DC-DC transformer module further includes: A NAND gate controller, wherein the input end of the NAND gate controller is respectively connected to the clock signal line and the DC-DC enable signal line, and the output end of the NAND gate controller is respectively connected to the third electrode of the first MOS tube, the third electrode of the second MOS tube, the third electrode of the third MOS tube, the third electrode of the fourth MOS tube, the third electrode of the fifth MOS tube, the third electrode of the sixth MOS tube, the third electrode of the seventh MOS tube and the third electrode of the eighth MOS tube.

[0011] Furthermore, in some embodiments, the DC-DC transformer module further includes: The inverter is used to invert the electrical signal output by the NAND gate controller, and the inverter is connected in series between the third electrode of the third MOS tube and the output end of the NAND gate controller.

[0012] Furthermore, in some embodiments, the first MOS tube and the second MOS tube are both P-type MOS tubes, and the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, and the eighth MOS tube are all N-type MOS tubes.

[0013] Furthermore, in some embodiments, the first electrode of the first MOS tube and the first electrode of the second MOS tube are both drain electrodes; The second electrode of the first MOS tube and the second electrode of the second MOS tube are both source electrodes; The first electrode of the third MOS tube, the first electrode of the fourth MOS tube, the first electrode of the fifth MOS tube, the first electrode of the sixth MOS tube, the first electrode of the seventh MOS tube, and the first electrode of the eighth MOS tube are all source electrodes; The second electrode of the third MOS tube, the second electrode of the fourth MOS tube, the second electrode of the fifth MOS tube, the second electrode of the sixth MOS tube, the second electrode of the seventh MOS tube, and the second electrode of the eighth MOS tube are all drain electrodes; The third pole of the first MOS tube, the third pole of the second MOS tube, the third pole of the third MOS tube, the third pole of the fourth MOS tube, the third pole of the fifth MOS tube, the third pole of the sixth MOS tube, the third pole of the seventh MOS tube, and the third pole of the eighth MOS tube are all gates.

[0014] Further, in some embodiments, the LDO voltage conversion module includes: Operational amplifier, ninth MOS tube, Miller compensation resistor and Miller compensation capacitor; Among them, the first electrode of the ninth MOS tube is connected to the power supply input end, the second electrode of the ninth MOS tube is connected to the power supply output end, the power supply output end is connected to the positive input end of the operational amplifier, the reverse input end of the operational amplifier is connected to the reference voltage line, the enable input end of the operational amplifier is connected to the LDO enable signal line, the output end of the operational amplifier is respectively connected to the third electrode of the ninth MOS tube and the upper plate of the Miller compensation capacitor, the lower plate of the Miller compensation capacitor is connected to the power supply output end, and the Miller compensation resistor is connected in series between the output end of the operational amplifier and the lower plate of the Miller compensation capacitor.

[0015] Furthermore, in some embodiments, the ninth MOS tube is a P-type MOS tube, the first electrode of the ninth MOS tube is a drain, the second electrode of the ninth MOS tube is a source, and the third electrode of the ninth MOS tube is a gate.

[0016] The embodiments of the present application have the following beneficial effects: the present application is provided with a power supply input terminal, a power supply output terminal, an LDO transformer module and a DC-DC transformer module, the DC-DC transformer module includes a shared capacitor circuit, the LDO transformer module is used to convert the electric energy of the power supply input terminal into a first stabilized electric energy and output it to the power supply output terminal; the shared capacitor circuit is used to convert the electric energy of the power supply input terminal into a second stabilized electric energy and output it to the power supply output terminal or filter the first stabilized electric energy, the power of the second stabilized electric energy is lower than the power of the first stabilized electric energy; wherein the power supply input terminal is respectively connected to the LDO The transformer module and the shared capacitor circuit are connected, the power supply output end is respectively connected to the LDO transformer module and the shared capacitor circuit, and the shared capacitor circuit is connected to the LDO transformer module. Based on the design of the built-in shared capacitor circuit, the DC-DC transformer module is integrated into the chip together with the LDO transformer module without the need for an external dedicated DC-DC chip and discrete inductors and capacitors, thereby achieving high-efficiency power supply in low-power and light-load application scenarios, achieving the purpose of high efficiency and energy saving, and saving the circuit layout area in the chip and the hardware cost of the peripheral application circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is an overall structural diagram of a power system circuit provided by some embodiments of the present application; Figure 2 is a DC-DC charging equivalent circuit diagram in a power system circuit provided in some embodiments of the present application; Figure 3 is a DC-DC discharge equivalent circuit diagram in a power system circuit provided in some embodiments of the present application; Reference numerals: LDO voltage conversion module 100, DC-DC voltage conversion module 200, shared capacitor circuit 210, digital logic load module 300; Power supply input terminal VCC, power supply output terminal VOUT, Miller compensation capacitor C0, first shared capacitor C1, second shared capacitor C2, third shared capacitor C3, output capacitor C4, first MOS tube M1, second MOS tube M2, third MOS tube M3, fourth MOS tube M4, fifth MOS tube M5, sixth MOS tube M6, seventh MOS tube M7, eighth MOS tube M8, ninth MOS tube M9, NAND gate controller Nand, inverter Inv, operational amplifier Amp, Miller compensation resistor R0. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] It should also be noted that in the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0022] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0023] In existing integrated circuits, the operating voltage of low-voltage logic devices in 40nm process is generally 1.1V. If an LDO voltage conversion module is used to convert the 3.3V voltage into 1.1V to power the low-voltage logic, plus the static power consumption of the LDO itself, its efficiency value is less than 33%; if an external dedicated DC-DC chip is used for power supply, not only is the peripheral hardware cost high, but also when the standby power consumption is very low, the power consumption of the DC-DC chip itself may be even greater, and the purpose of high-efficiency energy saving cannot be achieved.

[0024] Moreover, even if an integrated DC-DC module without external capacitors is used for power supply, its power supply capacity is very limited and it is difficult to meet the heavy-load application scenarios. Therefore, a high-efficiency and low-cost power supply system has become an urgent need for special application scenarios in integrated circuits.

[0025] Based on this, the present application is provided with a power supply input end, a power supply output end, an LDO transformer module and a DC-DC transformer module, the DC-DC transformer module includes a shared capacitor circuit, the LDO transformer module is used to convert the electric energy of the power supply input end into a first stabilized electric energy and output it to the power supply output end; the shared capacitor circuit is used to convert the electric energy of the power supply input end into a second stabilized electric energy and output it to the power supply output end or filter the first stabilized electric energy, and the power of the second stabilized electric energy is lower than the power of the first stabilized electric energy; wherein the power supply input end is respectively connected to the LDO transformer module and the shared capacitor circuit, the power supply output end is respectively connected to the LDO transformer module and the shared capacitor circuit, and the shared capacitor circuit is connected to the LDO transformer module, and then based on the design method of the built-in shared capacitor circuit, the DC-DC transformer module is integrated into the chip together with the LDO transformer module without the need for an external dedicated DC-DC chip and a discrete inductor and capacitor, so that high-efficiency power supply can be achieved in the application scenario of low power consumption and light load, so as to achieve the purpose of high efficiency and energy saving, and save the circuit layout area in the chip and the hardware cost of the peripheral application circuit.

[0026] A power system circuit provided in an embodiment of the present application is specifically described through the following embodiments.

[0027] Reference Figure 1 As shown, Figure 1 It is an overall structural diagram of a power system circuit provided in some embodiments of the present application. The power system circuit includes a power supply input terminal VCC, a power supply output terminal VOUT, an LDO transformer module 100 and a DC-DC transformer module 200. The DC-DC transformer module 200 includes a shared capacitor circuit 210. The power supply input terminal VCC is respectively connected to the LDO transformer module 100 and the shared capacitor circuit 210. The power supply output terminal VOUT is respectively connected to the LDO transformer module 100 and the shared capacitor circuit 210. The shared capacitor circuit 210 is connected to the LDO transformer module 100.

[0028] Among them, the LDO transformer module 100 is used to convert the electric energy of the power supply input terminal VCC into the first stabilized electric energy and output it to the power supply output terminal VOUT; the shared capacitor circuit 210 is used to convert the electric energy of the power supply input terminal VCC into the second stabilized electric energy and output it to the power supply output terminal VOUT or filter the first stabilized electric energy, and the power of the second stabilized electric energy is lower than the power of the first stabilized electric energy. In a possible embodiment, the power system circuit also includes a digital logic load module 300, the input end of the digital logic load module 300 is connected to the power supply output end VOUT, the output end of the digital logic load module 300 is grounded, and the signal receiving end of the digital logic load module 300 is connected to the low power mode control signal line.

[0029] Among them, when the digital logic load module 300 receives a high-level electrical signal lp_mode from the low-power mode control signal line, it is determined that the digital logic load module 300 at the current moment enters the low-power working mode, that is, the digital logic load module 300 enters the standby state, and the required power becomes smaller; and when the digital logic load module 300 receives a low-level electrical signal lp_mode from the low-power mode control signal line, it is determined that the digital logic load module 300 at the current moment enters the normal working mode, and the required power becomes larger.

[0030] In a possible embodiment, the power system circuit further includes an output capacitor C4, an upper plate of the output capacitor C4 is connected to the power output terminal VOUT, and a lower plate of the output capacitor C4 is grounded.

[0031] The output capacitor C4 and the digital logic load module 300 are connected in parallel, and the output capacitor C4 is used to stabilize the voltage of the digital logic load module 300 , that is, the output capacitor C4 serves as a filter capacitor of the digital logic load module 300 .

[0032] Furthermore, the shared capacitor circuit 210 includes a first shared capacitor C1, a second shared capacitor C2, a third shared capacitor C3, a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3.

[0033] It should be noted that the first shared capacitor C1 , the second shared capacitor C2 , and the third shared capacitor C3 have the same capacitance.

[0034] Among them, the first electrode of the first MOS tube M1 is connected to the power supply input terminal VCC, the second electrode of the first MOS tube M1 is connected to the upper electrode plate of the first shared capacitor C1, the lower electrode plate of the first shared capacitor C1 is connected to the first electrode of the second MOS tube M2, the second electrode of the second MOS tube M2 is connected to the upper electrode plate of the second shared capacitor C2, the lower electrode plate of the second shared capacitor C2 is connected to the first electrode of the third MOS tube M3, the first electrode of the third MOS tube M3 is connected to the upper electrode plate of the third shared capacitor C3, and the lower electrode plate of the third shared capacitor C3 is grounded.

[0035] Furthermore, the shared capacitor circuit 210 further includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7 and an eighth MOS transistor M8.

[0036] Among them, the first electrode of the fourth MOS tube M4, the first electrode of the fifth MOS tube M5, and the first electrode of the sixth MOS tube M6 are connected to the power supply output terminal VOUT, the second electrode of the fourth MOS tube M4 is connected to the upper plate of the first shared capacitor C1, the drain of the fifth MOS tube M5 is connected to the upper plate of the second shared capacitor C2, the drain of the sixth MOS tube M6 is connected to the upper plate of the third shared capacitor C3, the source of the seventh MOS tube M7 is connected to the lower plate of the first shared capacitor C1, the source of the eighth MOS tube M8 is connected to the lower plate of the second shared capacitor C2, the drain of the seventh MOS tube M7 is grounded, and the drain of the eighth MOS tube M8 is grounded.

[0037] It should be noted that, refer to Figure 2 As shown, Figure 2 It is a DC-DC charging equivalent circuit diagram in the power system circuit provided by some embodiments of the present application. When the DC-DC transformer module 200 is in working state, a charging equivalent circuit is formed between the first shared capacitor C1, the second shared capacitor C2, the third shared capacitor C3, the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3. The formation conditions of the charging equivalent circuit are as follows: the first MOS tube M1 and the second MOS tube M2 receive a high level voltage and are in a conducting state, the third MOS tube M3 receives a low level voltage and is in a conducting state, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 receive a high level voltage and are in a cut-off state, then Figure 2As shown, the power supply input terminal VCC, the first MOS tube M1, the first shared capacitor C1, the second MOS tube M2, the second shared capacitor C2, the third MOS tube M3 and the third shared capacitor C3 are mutually conductive, that is, a charging equivalent circuit is formed. At this time, the first shared capacitor C1, the second shared capacitor C2 and the third shared capacitor C3 are connected in series between the power supply input terminal VCC of the power supply and the ground. Finally, the power supply charges the first shared capacitor C1, the second shared capacitor C2 and the third shared capacitor C3 respectively through the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 in the power supply input terminal VCC.

[0038] It should be noted that, refer to Figure 3 As shown, Figure 3 : is a DC-DC discharge equivalent circuit diagram in a power system circuit provided by some embodiments of the present application. When the DC-DC transformer module 200 is in a working state, a discharge equivalent circuit is formed between the first shared capacitor C1, the second shared capacitor C2, the third shared capacitor C3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8. The formation conditions of the discharge equivalent circuit are as follows: the first MOS tube M1 and the second MOS tube M2 receive a low-level voltage and are in a cut-off state, the third MOS tube M3 receives a high-level voltage and is in a cut-off state, and the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 receive a low-level voltage and are in a conducting state. If Figure 3 As shown, the power supply output terminal VOUT, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the first shared capacitor C1, the second shared capacitor C2, the third shared capacitor C3, the seventh MOS tube M7 and the eighth MOS tube M8 are mutually connected, that is, a discharge equivalent circuit is formed. At this time, the first shared capacitor C1, the second shared capacitor C2 and the third shared capacitor C3 are connected in parallel between the power supply output terminal VOUT and the ground. Finally, the first shared capacitor C1, the second shared capacitor C2 and the third shared capacitor C3 are discharged to the power supply output terminal VOUT through the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 respectively.

[0039] In a possible embodiment, the DC-DC conversion module 200 also includes a NAND gate controller Nand, an input end of the NAND gate controller Nand is respectively connected to the clock signal line and the DC-DC enable signal line, and an output end of the NAND gate controller Nand is respectively connected to the third pole of the first MOS tube M1, the third pole of the second MOS tube M2, the third pole of the third MOS tube M3, the third pole of the fourth MOS tube M4, the third pole of the fifth MOS tube M5, the third pole of the sixth MOS tube M6, the third pole of the seventh MOS tube M7 and the third pole of the eighth MOS tube M8.

[0040] It should be noted that when the NAND gate controller Nand receives a high-level electrical signal en_dcdc from the DC-DC enable signal line and a high-level electrical signal clk from the clock signal line, it is determined that the output end of the NAND gate controller Nand outputs a high-level electrical signal sb at this time; and when the NAND gate controller Nand receives a high-level electrical signal en_dcdc from the DC-DC enable signal line and a low-level electrical signal clk from the clock signal line, it is determined that the output end of the NAND gate controller Nand outputs a low-level electrical signal sb at this time.

[0041] In a possible embodiment, the DC-DC conversion module 200 further includes an inverter Inv, which is used to invert the electrical signal output by the NAND gate controller Nand, and the inverter Inv is connected in series between the third pole of the third MOS tube M3 and the output end of the NAND gate controller Nand.

[0042] It should be noted that when the output end of the NAND gate controller Nand outputs a low-level electrical signal sb to the inverter Inv, the inverter Inv outputs a high-level electrical signal s to the third pole of the third MOS tube M3; and when the output end of the NAND gate controller Nand outputs a high-level electrical signal sb to the inverter Inv, the inverter Inv outputs a low-level electrical signal s to the third pole of the third MOS tube M3.

[0043] In a possible embodiment, when the DC-DC conversion module 200 further includes an inverter Inv, and the inverter Inv is connected in series between the third electrode of the third MOS tube M3 and the output end of the NAND gate controller Nand, the first MOS tube M1 and the second MOS tube M2 are both P-type MOS tubes, and the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, and the eighth MOS tube M8 are all N-type MOS tubes. The first electrode of the first MOS tube M1 and the first electrode of the second MOS tube M2 are both drains; the second electrode of the first MOS tube M1 and the second electrode of the second MOS tube M2 are both sources; the first electrode of the third MOS tube M3, the first electrode of the fourth MOS tube M4, the first electrode of the fifth MOS tube M5, the first electrode of the sixth MOS tube M6, the first electrode of the seventh MOS tube M7, and the first electrode of the eighth MOS tube M8 are all sources; the second electrode of the third MOS tube M3, the second electrode of the fourth MOS tube M4, the second electrode of the fifth MOS tube M5, the second electrode of the sixth MOS tube M6, the second electrode of the seventh MOS tube M7, and the second electrode of the eighth MOS tube M8 are all drains; the third electrode of the first MOS tube M1, the third electrode of the second MOS tube M2, the third electrode of the third MOS tube M3, the third electrode of the fourth MOS tube M4, the third electrode of the fifth MOS tube M5, the third electrode of the sixth MOS tube M6, the third electrode of the seventh MOS tube M7, and the third electrode of the eighth MOS tube M8 are all gates.

[0044] In a possible embodiment, when the DC-DC conversion module 200 is not provided with an inverter Inv, the first MOS tube M1, the second MOS tube M2, and the third MOS tube M3 are all P-type MOS tubes, and the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, and the eighth MOS tube M8 are all N-type MOS tubes. The first electrode of the first MOS tube M1, the first electrode of the second MOS tube M2, and the first electrode of the third MOS tube M3 are all drains; the second electrode of the first MOS tube M1, the second electrode of the second MOS tube M2, and the second electrode of the third MOS tube M3 are all sources; the first electrode of the fourth MOS tube M4, the first electrode of the fifth MOS tube M5, the first electrode of the sixth MOS tube M6, the first electrode of the seventh MOS tube M7, and the first electrode of the eighth MOS tube M8 are all sources; the second electrode of the fourth MOS tube M4, the second electrode of the fifth MOS tube M5, the second electrode of the sixth MOS tube M6, the second electrode of the seventh MOS tube M7, and the second electrode of the eighth MOS tube M8 are all drains; the third electrode of the first MOS tube M1, the third electrode of the second MOS tube M2, the third electrode of the third MOS tube M3, the third electrode of the fourth MOS tube M4, the third electrode of the fifth MOS tube M5, the third electrode of the sixth MOS tube M6, the third electrode of the seventh MOS tube M7, and the third electrode of the eighth MOS tube M8 are all gates.

[0045] Furthermore, the LDO voltage conversion module includes an operational amplifier Amp, a ninth MOS tube M9 and a Miller compensation capacitor C0.

[0046] Among them, the first electrode of the ninth MOS tube M9 is connected to the power supply input terminal VCC, the second electrode of the ninth MOS tube M9 is connected to the power supply output terminal VOUT, the power supply output terminal VOUT is connected to the positive input terminal of the operational amplifier Amp, the reverse input terminal of the operational amplifier Amp is connected to the reference voltage line, the enable input terminal of the operational amplifier Amp is connected to the LDO enable signal line, the output terminal of the operational amplifier Amp is respectively connected to the third electrode of the ninth MOS tube M9 and the upper plate of the Miller compensation capacitor C0, and the lower plate of the Miller compensation capacitor C0 is connected to the power supply output terminal VOUT.

[0047] Furthermore, the LDO voltage conversion module further includes a Miller compensation resistor R0, which is connected in series between the output end of the operational amplifier Amp and the lower plate of the Miller compensation capacitor C0.

[0048] Further, the ninth MOS tube M9 is a P-type MOS tube, the first electrode of the ninth MOS tube M9 is a drain, the second electrode of the ninth MOS tube M9 is a source, and the third electrode of the ninth MOS tube M9 is a gate.

[0049] It should be noted that the circuit conduction principle of the above power system circuit in the low power consumption mode is as follows.

[0050] When the digital logic load module 300 receives a high-level electrical signal lp_mode from the low power mode control signal line, it is determined that the digital logic load module 300 enters the low power working mode at the current moment. At this time, the power supply system circuit adopts the DC-DC power supply mode, that is, the electrical signal en_dcdc on the DC-DC enable signal line is set to a high level, and the electrical signal en_ldo on the LDO enable signal line is set to a low level. Further, when the NAND gate controller Nand receives a high-level electrical signal en_dcdc from the DC-DC enable signal line and receives a high-level electrical signal clk from the clock signal line, the NAND gate controller Nand outputs corresponding level signals (sb, s) to the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8, respectively, so that the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 are respectively in the on state, and the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are respectively in the off state. At this time, as Figure 2As shown, the first shared capacitor C1, the second shared capacitor C2, and the third shared capacitor C3 are connected in series between the power supply input terminal VCC and the ground. Finally, the power supply charges the first shared capacitor C1, the second shared capacitor C2, and the third shared capacitor C3 in the power supply input terminal VCC through the first MOS tube M1, the second MOS tube M2, and the third MOS tube M3, respectively. Since the first shared capacitor C1, the second shared capacitor C2, and the third shared capacitor C3 have the same capacitance, the voltage difference between the two ends of the first shared capacitor C1, the second shared capacitor C2, and the third shared capacitor C3 after being fully charged is one-third of the power supply voltage.

[0051] When the electrical signal clk in the clock signal line jumps from a high level to a low level of the next phase, the NAND gate controller Nand outputs corresponding level signals (sb, s) to the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8, respectively, so that the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 are respectively in the cut-off state, and the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are respectively in the on state. At this time, as Figure 3 As shown, the lower plates of the first shared capacitor C1, the second shared capacitor C2, and the third shared capacitor C3 are connected to the ground, and the upper plates of the first shared capacitor C1, the second shared capacitor C2, and the third shared capacitor C3 are connected to the upper plate of the output capacitor C4 through the fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6 and transfer the charge to the output capacitor C4. Finally, after multiple clock cycles, the DC-DC transformer module 200 finally outputs the voltage of the digital logic load module 300 and stabilizes at about one-third of the power supply voltage.

[0052] Due to the working mode of DC-DC, in the process of periodic charging and discharging, the voltage drop output to the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 is very small, the power loss is very small, and the efficiency can be very high. Moreover, since the DC-DC only needs to be used under ultra-low power consumption and light load conditions, the first shared capacitor C1, the second shared capacitor C2, the third shared capacitor C3 and the output capacitor C4 can all be micro capacitors and can be integrated inside the chip, saving the circuit wiring area inside the chip and the hardware cost of the peripheral application circuit.

[0053] Furthermore, the circuit conduction principle of the above power system circuit in normal mode is as follows.

[0054] When the digital logic load module 300 receives a low-level electrical signal lp_mode from the low-power mode control signal line, it is determined that the digital logic load module 300 at the current moment enters the normal working mode. At this time, the power system circuit adopts the LDO power supply mode, that is, the electrical signal en_dcdc on the DC-DC enable signal line is set to a low level, and the electrical signal en_ldo on the LDO enable signal line is set to high. Further, when the operational amplifier Amp receives a high-level electrical signal en_ldo from the LDO enable signal line, the operational amplifier Amp works normally, so that the ninth MOS tube M9 is in a conducting state. At this time, the LDO transformer module 100 transmits the voltage of the power supply input terminal VCC to the power supply output terminal VOUT through the ninth MOS tube M9. Finally, the power supply output terminal VOUT transmits the voltage to the digital logic load module 300.

[0055] In addition, since the electrical signal en_dcdc on the DC-DC enable signal line is set to a low level, at this time, the output end of the NAND gate controller Nand in the DC-DC conversion module 200 always outputs a low level, so that the first MOS tube M1, the second MOS tube M2, and the third MOS tube M3 are respectively in the cut-off state, and the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are respectively in the on state. At this time, the first shared capacitor C1, the second shared capacitor C2, the third shared capacitor C3 and the output capacitor C4 jointly act as a filter capacitor of the LDO conversion module 100.

[0056] To summarize, in the power system circuit of the present application, the LDO transformer module 100 and the DC-DC transformer module 200 share the capacitors that occupy the main area, without significantly increasing the area cost, and when the power system circuit has a heavy load requirement, the LDO transformer module 100 can be used for power supply, and when the power system circuit has a low power consumption and light load requirement, the DC-DC transformer module 200 can be used for power supply, that is, the LDO transformer module 100 can be used to obtain a stable power supply capability under heavy load conditions, and the DC-DC transformer module 200 can be used to obtain a high-efficiency power supply capability under low power consumption and light load conditions, thereby achieving the purpose of high efficiency and energy saving. As above, it also meets the diverse and special application scenario requirements in integrated circuits.

[0057] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0058] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0059] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0061] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0063] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0064] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0065] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0066] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present application.

[0067] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A power system circuit, characterized in that: include: Power supply input terminal; Power supply output terminal; An LDO voltage conversion module, the LDO voltage conversion module is used to convert the electric energy of the power supply input end into a first voltage-stabilized electric energy and output it to the power supply output end; A DC-DC transformer module, the DC-DC transformer module comprising a shared capacitor circuit, the shared capacitor circuit is used to convert the electric energy of the power supply input end into a second stabilized electric energy and output it to the power supply output end or filter the first stabilized electric energy, the power of the second stabilized electric energy is lower than the power of the first stabilized electric energy; Among them, the power supply input end is connected to the LDO transformer module and the shared capacitor circuit respectively, the power supply output end is connected to the LDO transformer module and the shared capacitor circuit respectively, and the shared capacitor circuit is connected to the LDO transformer module.

2. The power system circuit according to claim 1, characterized in that: Also includes: A digital logic load module, wherein the input end of the digital logic load module is connected to the power supply output end, and the output end of the digital logic load module is grounded; An output capacitor, wherein an upper plate of the output capacitor is connected to the power supply output terminal, and a lower plate of the output capacitor is grounded; The output capacitor and the digital logic load module are connected in parallel, and the output capacitor is used to stabilize the voltage of the digital logic load module.

3. The power system circuit according to claim 1, characterized in that: The shared capacitor circuit includes a first shared capacitor, a second shared capacitor, a third shared capacitor, a first MOS transistor, a second MOS transistor and a third MOS transistor; Among them, the first electrode of the first MOS tube is connected to the power supply input end, the second electrode of the first MOS tube is connected to the upper electrode plate of the first shared capacitor, the lower electrode plate of the first shared capacitor is connected to the first electrode of the second MOS tube, the second electrode of the second MOS tube is connected to the upper electrode plate of the second shared capacitor, the lower electrode plate of the second shared capacitor is connected to the first electrode of the third MOS tube, the first electrode of the third MOS tube is connected to the upper electrode plate of the third shared capacitor, and the lower electrode plate of the third shared capacitor is grounded.

4. The power system circuit according to claim 3, characterized in that: The shared capacitor circuit further includes a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube; Among them, the first electrode of the fourth MOS tube, the first electrode of the fifth MOS tube, and the first electrode of the sixth MOS tube at the power supply output end are connected, the second electrode of the fourth MOS tube is connected to the upper plate of the first shared capacitor, the drain of the fifth MOS tube is connected to the upper plate of the second shared capacitor, the drain of the sixth MOS tube is connected to the upper plate of the third shared capacitor, the source of the seventh MOS tube is connected to the lower plate of the first shared capacitor, the source of the eighth MOS tube is connected to the lower plate of the second shared capacitor, the drain of the seventh MOS tube is grounded, and the drain of the eighth MOS tube is grounded.

5. The power system circuit according to claim 4, characterized in that: The DC-DC transformer module further includes: A NAND gate controller, wherein the input end of the NAND gate controller is respectively connected to the clock signal line and the DC-DC enable signal line, and the output end of the NAND gate controller is respectively connected to the third electrode of the first MOS tube, the third electrode of the second MOS tube, the third electrode of the third MOS tube, the third electrode of the fourth MOS tube, the third electrode of the fifth MOS tube, the third electrode of the sixth MOS tube, the third electrode of the seventh MOS tube and the third electrode of the eighth MOS tube.

6. The power system circuit according to claim 5, characterized in that: The DC-DC transformer module further includes: An inverter is used to invert the electrical signal output by the NAND gate controller, and the inverter is connected in series between the third electrode of the third MOS tube and the output end of the NAND gate controller.

7. The power system circuit according to claim 6, characterized in that: The first MOS tube and the second MOS tube are both P-type MOS tubes, and the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, and the eighth MOS tube are all N-type MOS tubes.

8. The power system circuit according to claim 7, characterized in that: The first electrode of the first MOS tube and the first electrode of the second MOS tube are both drain electrodes; The second electrode of the first MOS tube and the second electrode of the second MOS tube are both source electrodes; The first electrode of the third MOS tube, the first electrode of the fourth MOS tube, the first electrode of the fifth MOS tube, the first electrode of the sixth MOS tube, the first electrode of the seventh MOS tube, and the first electrode of the eighth MOS tube are all source electrodes; The second electrode of the third MOS tube, the second electrode of the fourth MOS tube, the second electrode of the fifth MOS tube, the second electrode of the sixth MOS tube, the second electrode of the seventh MOS tube, and the second electrode of the eighth MOS tube are all drain electrodes; The third pole of the first MOS tube, the third pole of the second MOS tube, the third pole of the third MOS tube, the third pole of the fourth MOS tube, the third pole of the fifth MOS tube, the third pole of the sixth MOS tube, the third pole of the seventh MOS tube, and the third pole of the eighth MOS tube are all gates.

9. The power system circuit according to claim 1, characterized in that: The LDO voltage conversion module comprises: Operational amplifier, ninth MOS tube, Miller compensation resistor and Miller compensation capacitor; Among them, the first electrode of the ninth MOS tube is connected to the power supply input end, the second electrode of the ninth MOS tube is connected to the power supply output end, the power supply output end is connected to the positive input end of the operational amplifier, the reverse input end of the operational amplifier is connected to the reference voltage line, the enable input end of the operational amplifier is connected to the LDO enable signal line, the output end of the operational amplifier is respectively connected to the third electrode of the ninth MOS tube and the upper plate of the Miller compensation capacitor, the lower plate of the Miller compensation capacitor is connected to the power supply output end, and the Miller compensation resistor is connected in series between the output end of the operational amplifier and the lower plate of the Miller compensation capacitor.

10. The power system circuit according to claim 9, characterized in that: The ninth MOS tube is a P-type MOS tube, the first electrode of the ninth MOS tube is a drain, the second electrode of the ninth MOS tube is a source, and the third electrode of the ninth MOS tube is a gate.

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