A DC-DC converter with dual duty cycles and control method thereof

Abstract

The present invention belongs to the field of microgrid technology and discloses a DC-DC converter with dual duty cycles and a control method. The converter includes: a power supply, a first inductor, a second inductor, a first switching transistor, a second switching transistor S2, a third switching transistor, a first inductor, a second inductor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor. The DC-DC converter of the present invention has high voltage gain capability without relying on a transformer or coupled inductors. The present invention is achieved by effectively integrating an active switched inductor network and a switched capacitor, and high voltage gain can be achieved by using a low duty cycle value.

Description

Technical Field

[0001] The present invention belongs to the technical field of microgrids, and in particular relates to a DC-DC converter with dual duty cycles and a control method thereof. Background Art

[0002] Traditional DC-DC converters, such as boost, secondary boost, and flyback converters, are capable of achieving high voltage conversion ratios at increasing duty cycles. However, in practice, several factors limit VG, or the boost factor, including increased stress on the power switches, diode reverse recovery issues, and inductor conduction losses. Consequently, modifications to the traditional boost converter configuration are necessary to improve key performance metrics. For example, one approach involves implementing soft-switching operation through auxiliary circuitry. Another example is achieving zero voltage switching (ZVS) of the main switch through the application of an active snubber. A transformer or coupled inductor (CI) enhances the converter through its turns ratio, allowing VG to be adjusted through this ratio. However, this integration introduces several disadvantages, including increased size and cost, high switching voltage spikes due to the transformer's leakage inductance, and core saturation. In pursuit of achieving higher VG, many boost DC-DC converters have incorporated a variety of unique boost technologies. However, achieving higher VG requires additional SC cells, resulting in increased losses and reduced efficiency. Furthermore, these converters face significant current spikes or inrushes during switching, impacting switch current stress and overall efficiency. Another approach for increasing VG is SL technology, which produces very effective results, especially when combined with SC technology. However, this requires the use of many components to achieve high VG.

[0003] China Patent Publication No. CN113890356A, titled "A New High-Gain Dual-Input DC-DC Converter," includes an input unit, first and second boost units, and a load unit. The input unit comprises three inductors L1, L3, and L4, four capacitors C3, C5, C7, and C8, three power switches S1, S2, and S3, and four diodes D1, D2, D3, and D4. The first boost unit comprises an inductor L2, a capacitor C4, and a diode D5, while the second boost unit comprises an inductor L5, a capacitor C6, and a diode D6. This patent reduces the number of energy conversions between a micropower source, a battery, and a load, improving energy conversion efficiency. However, the DC-DC converter described in this patent application cannot integrate an energy storage unit, charge and discharge the battery, or achieve high-gain output. Summary of the Invention

[0004] To overcome the aforementioned problems in the prior art, the present invention aims to provide a dual-duty-cycle DC-DC converter and control method. By improving the converter structure, this system integrates an energy storage unit. Comprising only three switching transistors, it can meet battery charging and discharging requirements and achieve high-gain output. This integration reduces the number of energy conversions between the micropower source, battery, and load, improving energy utilization.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] In a first aspect, the present invention provides a DC-DC converter with dual duty cycles, comprising: a power supply Vin, an output terminal Vo, a first inductor L1, a second inductor L2, a first switch tube S1, a second switch tube S2, a third switch tube S3, a first inductor L1, a second inductor L2, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5;

[0007] The positive electrode of the power supply Vin is connected to the first end of the first inductor L1 and the drain of the first switch tube S1, and the other end is connected to the source of the second switch tube S2 and the first end of the second inductor L2; the second end of the first inductor L1 is connected to the drain of the second switch tube S2, the positive electrode of the first diode D1, the first end of the first capacitor C1 and the positive electrode of the third diode D3; the source of the first switch tube S1 is connected to the first end of the second capacitor C2, the first end of the third capacitor C3, the second end of the second inductor L2, the source of the third switch tube S3 and the cathode of the second diode D2; the drain of the third switch tube S3 is connected to the cathode of the first diode D1; the first end of the output terminal Vo is connected to the negative electrode of the first diode D1; One end is connected to the second end of the second capacitor C2 and the positive electrode of the fourth diode D4; the negative electrode of the fourth diode D4 is connected to the second end of the first capacitor C1 and the positive electrode of the second diode D2; the second end of the output end Vo is connected to the first end of the fifth capacitor C5 and the negative electrode of the sixth diode D6; the negative electrode of the third diode D3 is connected to the second end of the third capacitor C3, the first end of the fourth capacitor C4 and the positive electrode of the fifth diode D5; the primary side of the common mode choke N1Ls is connected to the second end of the fourth capacitor C4 and the negative electrode of the fifth diode D5; the secondary side of the common mode choke N1Ls is connected to the second end of the fifth capacitor C5 and the positive electrode of the sixth diode D6.

[0008] Optionally, the first switch tube S1 , the second switch tube S2 and the third switch tube S3 are all IRFZ44NMOSFET switch tubes.

[0009] Optionally, the first diode D1 and the third diode D3 are Schottky diodes.

[0010] Optionally, the second diode D2 and the fourth diode D4 are fast recovery diodes.

[0011] Optionally, the fifth diode D5 and the sixth diode D6 are Zener diodes.

[0012] Optionally, the first inductor L1 and the second inductor L2 are WE-PD2 type inductors.

[0013] Optionally, the first capacitor C1 and the second capacitor C2 are electrolytic capacitors.

[0014] Optionally, the fourth capacitor C4 and the fifth capacitor C5 are ceramic capacitors.

[0015] Optionally, the common-mode choke coil N1Ls is a PCN-type common-mode choke coil.

[0016] In a second aspect, the present invention provides a control method for a DC-DC converter with dual duty cycles, comprising the following steps:

[0017] The first switch S1 and the second switch S2 are activated simultaneously; the third switch S3, the first diode D1, the second diode D2, and the third diode D3 are all disconnected, and the fourth diode D4 is turned on; the third capacitor C3 is charged, and the first capacitor C1 and the second capacitor C2 are discharged;

[0018] Cut off the gate signals of the first switch tube S1 and the second switch tube S2, and apply a control signal to the third switch tube S3; the first capacitor C1 maintains a charged level, and the second capacitor C2 and the third capacitor C3 discharge and provide an output load;

[0019] Turn off the third switch tube S3, the fourth diode D4 and the first diode D1, and turn on the diode D2 and the diode D3;

[0020] When the currents of the first inductor L1 and the second inductor L2 are zero, the first switch tube S1 and the second switch tube S2 are turned off.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] This invention discloses a dual-duty-cycle DC-DC converter featuring high voltage gain (VG) capability without relying on transformers or coupled inductors. This is achieved by efficiently integrating an active switched inductor network and switched capacitors, providing dual duty cycles. High voltage gain is achieved by utilizing low duty cycle values. Furthermore, the DC-DC converter of the invention achieves low turn-off switching losses for both the output and input switches under ZVS (Zero Voltage Switching) conditions.

[0023] The invented dual-duty-cycle DC-DC converter eliminates the need for a transformer or coupled inductor, reducing the size and weight of the converter, eliminating the challenge of leakage inductance, and simplifying analysis, design, and manufacturing. At a power of 300W and a gain of 20V, the measured efficiency is 95%. Therefore, the proposed DC-DC converter is suitable for applications requiring high-voltage step-up conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present invention in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only schematic and are used to help understand the present invention, and are not intended to specifically limit the shapes and proportional dimensions of the components of the present invention. In the drawings:

[0025] Figure 1 This is a circuit topology diagram of a DC-DC converter with dual duty cycles according to the present invention.

[0026] Figure 2 Schematic diagrams of the circuit on-off conditions of the converter in various operating modes: mode 1 (a), mode 2 (b), mode 3 (c), and mode 4 (d).

[0027] Figure 3 This is the transfer function system of embodiment 2 of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0029] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0030] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.

[0031] When an element is referred to as being "disposed on" another element, it may be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may also be an intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only embodiments. If the term "horizontal" appears, it does not mean that the component is required to be absolutely horizontal, but it can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and it does not mean that the structure must be completely horizontal, but it can be slightly tilted.

[0032] It should be noted that similar reference numerals and letters denote similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures. In the description of the present invention, it should be understood that the terms "comprise" and "include" indicate the presence of the described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their combinations.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0034] The present invention will be described in detail below with reference to the accompanying drawings.

[0035] A DC-DC converter with dual duty cycles according to the present invention includes: a power supply Vin, an output terminal Vo, a first inductor L1, a second inductor L2, a first switching tube S1, a second switching tube S2, a third switching tube S3, a first inductor L1, a second inductor L2, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5.

[0036] The first switch tube S1 , the second switch tube S2 , and the third switch tube S3 are connected in parallel, and each switch tube is connected to an inductor for controlling the on and off of the current.

[0037] The control strategy of the first switch tube S1, the second switch tube S2, and the third switch tube S3 adopts a dual duty cycle, which allows maintaining a stable output voltage by adjusting the on-time of the switch under different input voltage conditions.

[0038] The first diode D1, the second diode D2, the third diode D3 and the fourth diode D4 are connected to the first switch tube S1, the second switch tube S2 and the third switch tube S3 to provide a current path when the switch is turned off to prevent the inductor from generating excessive reverse voltage.

[0039] The first capacitor C1 , the second capacitor C2 , and the third capacitor C3 are connected to the first diode D1 , the second diode D2 , and the third diode D3 for filtering and reducing the ripple of the output voltage.

[0040] Common-mode choke N1Ls, consisting of winding N1 and inductor Ls, is used for voltage conversion and isolation. The turns ratio N1:Ls of common-mode choke N1Ls determines the voltage conversion ratio. Fifth diode D5 and sixth diode D6, located on the secondary side of common-mode choke N1Ls, convert the AC voltage on the secondary side of common-mode choke N1Ls to a DC voltage.

[0041] The fourth capacitor C4 and the fifth capacitor C5 are connected to the secondary side of the common mode choke N1Ls to further smooth the voltage. The output voltage Vo is filtered by the inductor Ls and the capacitor C5 before being supplied to the load.

[0042] The present invention discloses a DC-DC converter with dual duty cycles. The circuit utilizes a three-phase design, improving power density and efficiency. The dual rectifier design on the secondary side of the common-mode choke (N1Ls) allows current to flow to the load during every cycle, improving energy conversion efficiency. The common-mode choke (N1Ls) provides electrical isolation, enhancing circuit safety. This allows for maintaining a stable output voltage under varying input voltage conditions by adjusting the switch on-time. Multi-stage filter capacitors and inductors reduce voltage and current ripple, improving output quality.

[0043] Optionally, the first switch tube S1 , the second switch tube S2 and the third switch tube S3 are all IRFZ44N MOSFET type switch tubes, which are N-channel enhancement MOSFETs suitable for high voltage gain applications.

[0044] Optionally, the first diode D1 and the third diode D3 are Schottky diodes. Further, the Schottky diodes are STPS2L60UF Schottky diodes from STMicroelectronics for fast recovery.

[0045] Optionally, the second diode D2 and the fourth diode D4 are fast recovery diodes, and the fifth diode D5 and the sixth diode D6 are Zener diodes.

[0046] Optionally, the first inductor L1 and the second inductor L2 are Wurth Elektronik WE-PD2 inductors, which have high current capacity and low DC resistance and are suitable for use in high-efficiency DC-DC converters.

[0047] Optionally, the first capacitor C1 and the second capacitor C2 are electrolytic capacitors. Further, the first capacitor C1 and the second capacitor C2 are Panasonic EPCOS B series electrolytic capacitors suitable for output filtering.

[0048] Optionally, the third capacitor C3 adopts a TDK C3225X7R1C106K250AC type diode, which is used as a parallel capacitor of the freewheeling diode.

[0049] Optionally, the fourth capacitor C4 and the fifth capacitor C5 are ceramic capacitors. Further, the fourth capacitor C4 and the fifth capacitor C5 are Murata GRM series ceramic capacitors for high-frequency applications.

[0050] Optionally, the common-mode choke N1Ls is a TDK PCN series common-mode choke. A common-mode choke can be selected to reduce electromagnetic interference.

[0051] Example 1

[0052] A control method for a DC-DC converter with dual duty cycles in this embodiment includes the following operating modes:

[0053] DCM (Discontinuous Conduction Mode) Operation: In DCM operation, the voltage across the first inductor L1 and the second inductor L2 drops to zero before the switching cycle is completed. Therefore, the operation is divided into four different operating modes.

[0054] Mode 1 [t0-t1]: At t = t0, when receiving the same control signal, the first switch S1 and the second switch S2 are activated simultaneously; this causes the first inductor L1 and the second inductor L2 to be connected in parallel with the power supply Vin, and the power supply charges the inductor and linearly increases its current (i L1 and i L2 ). The current flow path associated with this state is as follows Figure 2 As shown in (a).

[0055] The third switch tube S3, the first diode D1, the second diode D2 and the third diode D3 are all disconnected, and the fourth diode D4 is turned on.

[0056] Therefore, the third capacitor C3 is charged, while the first and second capacitors C1 and C2 are discharged. Furthermore, the second capacitor C2 provides energy to the output load. Using KVL and KCL in the equivalent circuit for this state, the following equation is derived.

[0057] Formula 1

[0058] Formula 2

[0059] Formula 3

[0060] Formula 4

[0061] Formula 5

[0062] Formula 6

[0063] in, v L is the voltage across the inductor L, v in is the input voltage, v C1 is the voltage across capacitor C1, v C1 is the voltage across capacitor C1, v C2 is the voltage across capacitor C2, v C3 is the voltage across capacitor C3, v o is the output voltage, i C1 is the current flowing through capacitor C1, i C2 is the current flowing through capacitor C2, i C3 is the current flowing through capacitor C3, i Lis the current flowing through the inductor L, i o is the load current.

[0064] Mode 2 [t1-t2]: At t = t1, the gate signals of the first switch S1 and the second switch S2 are cut off, and the control signal V is applied to the third switch S3. GS3 Therefore, S1 and S2 are turned off and S3 is activated. Considering that the turn-off voltages of the first and second switches S1 and S2 are quite low in this mode, equivalent to half of the input voltage, the losses associated with their turn-off switching are reduced.

[0065] In addition, if Figure 2 As shown in Figure (a), activating the third switch S3 under ZVS (Zero Voltage Switching) conditions significantly reduces switching losses. The first diode D1 is conductive, but the second, third, and fourth diodes D2, D3, and D4 are reverse-biased. Consequently, the inductor and power supply are connected in series, with half the input voltage applied to each inductor. Consequently, the inductor continues to charge, but its current increases at half the rate of the previous mode. The first capacitor C1 remains at the same charge level. However, the second and third capacitors C2 and C3 discharge and supply the output load.

[0066] Applying KVL (Kirchhoff's Voltage Law) and KCL (Kirchhoff's Current Law) in this mode yields the following equation:

[0067] Formula 7

[0068] Formula 8

[0069] Formula 9

[0070] Formula 10

[0071] in, v L is the voltage across the inductor L, v in is the input voltage, i C1 The current flowing through capacitor C1 is i C2 The current flowing through capacitor C2 is i C3 The current flowing through capacitor C3 is i L The current flowing through the inductor L is,i o is the load current.

[0072] DCM operation: In DCM operation, the voltage across the first inductor L1 and the second inductor L2 drops to zero before the switching cycle is completed.

[0073] Mode 3 [t2-t3]: At 2z, the gate signal Ves is turned off, the third switch S3 and the diode D1 are turned off. The fourth diode D4 is still in the off state, but the diodes D2 and D3 begin to conduct.

[0074] Therefore, the power supply energy and the stored energy of inductors L1 and L2 are transferred and charge capacitor C1 and second capacitor C2. i in 、 i L1 and i L2 in, i in Input current, i L1 The current flowing through the inductor L1 is i L2 The current flowing through inductor L2 decreases linearly. In addition, the third capacitor C3 provides energy and discharges. Using this equivalent circuit model, the subsequent equations are derived as follows:

[0075] Formula 11

[0076] Formula 12

[0077] Formula 13

[0078] Formula 14

[0079] in, v L is the voltage across the inductor L, v in is the input voltage, v C1 The voltage across capacitor C1, v C2 The voltage across capacitor C2, i C1 The current flowing through capacitor C1 is i C2 The current flowing through capacitor C2 is i C3 The current flowing through capacitor C3 is i L The current flowing through the inductor L is io is the load current.

[0080] The first three DCM operating modes follow similar behaviors; mode four is as follows Figure 2 (d) is shown. The waveform of the basic component is as follows Figure 2 (b) shown.

[0081] Mode 4 [t3-t4]: This mode starts when the current in inductors L1 and L2 is zero; therefore, the voltage between them is zero. All semiconductor devices are inactive. At the same time, the second capacitor C2 and the third capacitor C3 are discharged due to the energy provided by the load. Therefore, in this mode, their current is equal to -i o .

[0082] By applying the volt-second balance law to the inductor L

[0083] Formula 15

[0084] in, v in is the input voltage, v C1 The voltage across capacitor C1.

[0085] The formula for the change of the voltage across the first capacitor C1, the second capacitor C2 and the third capacitor C3 with the output voltage is as follows:

[0086] Formula 16

[0087] Formula 17

[0088] Formula 18

[0089] in, D 1 is the duty cycle associated with switch S1, which is the ratio of the S1 on-time to the total cycle time. D 2 is the duty cycle associated with switch S2, which is the ratio of the S2 on-time to the total cycle time. G CCM is the gain in continuous conduction mode.

[0090] To select the appropriate components necessary to manufacture the proposed converter, it is necessary to calculate the voltage and current values that each component must be able to withstand. The voltage stress in the semiconductor can be calculated by analyzing the intervals of the equivalent circuit in the inactive state. By writing out the KVL for each operating mode, the voltage cross section of the semiconductor can be obtained.

[0091] Applying the ampere-second principle to the second capacitor C2 and the third capacitor C3, we obtain:

[0092] Formula 19

[0093] Formula 20

[0094] in, D 1 is the duty cycle associated with switch S1, which is the ratio of the S1 on-time to the total cycle time. D 2 is the duty cycle associated with switch S2, which is the ratio of the S2 on-time to the total cycle time. T S is a switching cycle, I O is the output current.

[0095] From these equations, calculate the currents of the second capacitor C2 and the third capacitor C3 in mode 2 and mode 1 respectively,

[0096] Formula 21

[0097] Furthermore, considering the ideal performance of the converter, the input current is:

[0098] Formula 22

[0099] The average current of the inductor is obtained as follows:

[0100] Formula 23

[0101] By using the volt-second balance principle on the input inductor, the voltages of the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 as well as the output voltage can be determined.

[0102] Using Equations 21 and 23, and the capacitor current relationship derived from KCL, the current stress of the semiconductor is determined using the following formula.

[0103] Formula 24

[0104] Formula 25

[0105] Formula 26

[0106] Formula 27

[0107] The voltages of the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 as well as the output voltage are determined by using the volt-second balance principle on the input inductor.

[0108] Formula 28

[0109] Formula 29

[0110] Formula 30

[0111] in, D x is the duty cycle of the third switch tube S3.

[0112] By applying the charge balance principle to the capacitor, the current flowing through the inductor is calculated.

[0113] Formula 31

[0114] Hypothesis I L = L L(peak) / 2, then we get I L(peak) (peak current of inductor L), as shown below:

[0115] Formula 32

[0116] in, is the load resistance.

[0117] Furthermore, the following equation is established for the inductor:

[0118] Formula 33

[0119] in, is the change in the inductor L, is the time variation, is the switching frequency.

[0120] Combining Equations 32 and 33, we can obtain the time duration of mode three.

[0121] Formula 34

[0122] Where, is a dimensionless variable, defined as follows:

[0123] Formula 35

[0124] in, is the equivalent inductance, is the switching frequency, L eq For R load for.

[0125] Use Equations 30 and 34 to implement the DCM voltage gain of the PC.

[0126] Formula 36

[0127] In order to determine the boundary conditions that distinguish CCM and DCM operation, G CCM = GDCM .therefore, The critical value of is obtained by Equation 37.

[0128] Formula 37

[0129] This prototype is designed to demonstrate the high-voltage gain capabilities of a PC with a 20V input voltage and a 400V output voltage. Furthermore, efficiency will be evaluated with output power ranging from 100W to 300W. Therefore, the output power range must be considered when conducting these evaluations. The duty cycles Di and Dz are determined; various combinations of these duty cycles can be adjusted to achieve a 400V output voltage regulation.

[0130] The required inductor relationship is expressed as:

[0131] Formula 38

[0132] In the given equation, D represents the duty cycle, f S represents the switching frequency, represents the ripple in the inductor current.

[0133] The magnetic induction value of the first diode D1 is expressed as follows:

[0134] Formula 39

[0135] The worst-case inductor condition occurs at 100W output power within the operating range. The minimum inductor value that ensures CCM operation is shown in the prototype at different switching frequencies and duty cycles. The inductor current ripple ratio is calculated.

[0136] Formula 40

[0137] Formula 41

[0138] in, is the critical time constant, is the load factor, is the inductor current ripple ratio.

[0139] The design of all capacitors will be based on the overall relationship defined as follows:

[0140] Formula 42

[0141] Where D represents the duty cycle, f s represents the switching frequency, VC represents the capacitor voltage ripple percentage.

[0142] Substituting the capacitor voltage and current into Equation 42, we get the minimum value of all capacitors as follows,

[0143] Formula 43

[0144] Formula 44

[0145] Formula 45

[0146] Formula 46

[0147] It is crucial to accurately determine the capacitance of the capacitor to constrain the voltage oscillation on the capacitor. Load = 5332), the capacitor encounters the most critical condition. Consider the specified = 1% ( The allowable voltage ripple of the circuit can be determined by applying the following equation. The minimum value of the capacitor for different combinations of duty cycle and switching frequency.

[0148] Formula 47

[0149] Formula 48

[0150] Formula 49

[0151] Selecting capacitors with higher capacitance values reduces voltage ripple. Additionally, these capacitors typically exhibit lower power losses due to lower equivalent series resistance (ESR).

[0152] To determine the efficiency of the proposed converter, a careful calculation of the power losses in each component, including the input inductor, semiconductors, and capacitors, is essential. The power losses are calculated using Equation 50, and the efficiency is then determined using Equation 51.

[0153] Formula 50

[0154] Formula 51

[0155] in, is the total power consumption, is the inductor loss, is the switching loss, is the diode loss, is the capacitance loss, is the output power, It's efficiency.

[0156] Additionally, the derivation of the non-ideal voltage gain can be accomplished by applying Equation 45.

[0157] Formula 52

[0158] It is assumed that all power semiconductors, inductors and capacitors are in ideal conditions. However, in order to accurately separate the state variables in each operating state, the inductor is marked with r L The parasitic series resistance of the capacitor is considered, and the capacitor with parasitic series resistance characteristics is marked as r C The derivation of average and small-signal models is facilitated by employing a state-space averaging technique. This approach involves obtaining the system equations for all operating modes and then averaging them over a single commutation cycle while taking into account the time duration of each mode.

[0159] Example 2

[0160] like Figure 3 The transfer function of the DC-DC converter with dual duty cycle of the present invention is shown as follows: the input current reference signal I Lref and voltage reference signals V Cref electricity Stream Reference Signal I Lref With feedback signal d 1 is added at the first summing node, V Cref With feedback signal d 2 is added at the second summing node. The added signal enters the controller q , after passing through the controller q through the gain K q , then enters the integrator for integration operation. The integrated signal is then passed through the gain K d , then split into two paths, one path through the gain K x1 , the other way through the gain K x2 .go through K x1 The signal and A Multiply, pass K x2 The signal and B Add, A and B The output of d 1 and d 2 are added to form feedback. At the same time, the state of the system is determined by x(t) and y(t) Indicates that they are respectively gained E The output is the actual current IL and voltage V C The entire system uses this feedback mechanism to ensure that the actual output current and voltage are as close to the reference signal as possible, and uses controllers, integrators, and multiple gain links to achieve precise control.

[0161] To verify the theoretical analysis and feasibility of the proposed design, an experimental model was assembled and tested in the laboratory. It is designed to boost a 20V input voltage to a 400V output load voltage with a power range of 100-300W. The output voltage can be adjusted to 400V by setting different duty cycles; duty cycles D1 = 50% and D2 = 35% are used as an example. A TMS320F28379D microcontroller was used to generate control pulses at a frequency of 25kHz, which were applied to the MOSFETs in an open-loop control mechanism using a gate driver to obtain steady-state experimental waveforms. Clearly, at 400V, the output voltage remains constant, with VG approximately 20V, emphasizing that the converter is capable of achieving significant VG. Furthermore, it can be observed that the voltage across each capacitor is approximately half the output voltage. Clearly, in mode 1, they are active and conductive, while in mode 2, low voltage is applied to them, ultimately minimizing turn-off switching losses.

[0162] Unless otherwise specified, the device components involved in the above embodiments are all conventional device components, and the structural settings, working modes or control modes involved are all conventional settings, working modes or control modes in the art unless otherwise specified.

[0163] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and are not limiting. Other modifications or equivalent substitutions made to the technical solution of the present invention by ordinary technicians in this field should be included in the scope of the claims of the present invention as long as they do not depart from the spirit and scope of the technical solution of the present invention.

Claims

1. A DC-DC converter with dual duty cycles, characterized in that: include: Power supply Vin, output terminal Vo, first inductor L1, second inductor L2, first switch S1, second switch S2, third switch S3, first diode D1, second diode D2, third diode D3, fourth diode D4, fifth diode D5, sixth diode D6, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5; The positive electrode of the power supply Vin is connected to the first end of the first inductor L1 and the drain of the first switch tube S1, and the other end is connected to the source of the second switch tube S2 and the first end of the second inductor L2; the second end of the first inductor L1 is connected to the drain of the second switch tube S2, the positive electrode of the first diode D1, the first end of the first capacitor C1 and the positive electrode of the third diode D3; the source of the first switch tube S1 is connected to the first end of the second capacitor C2, the first end of the third capacitor C3, the second end of the second inductor L2, the source of the third switch tube S3 and the cathode of the second diode D2; the drain of the third switch tube S3 is connected to the cathode of the first diode D1; the output terminal Vo is connected to the positive electrode of the first inductor L1. The first end is connected to the second end of the second capacitor C2 and the positive electrode of the fourth diode D4; the negative electrode of the fourth diode D4 is connected to the second end of the first capacitor C1 and the positive electrode of the second diode D2; the second end of the output end Vo is connected to the first end of the fifth capacitor C5 and the negative electrode of the sixth diode D6; the negative electrode of the third diode D3 is connected to the second end of the third capacitor C3, the first end of the fourth capacitor C4 and the positive electrode of the fifth diode D5; the primary side of the common mode choke N1Ls is connected to the second end of the fourth capacitor C4 and the negative electrode of the fifth diode D5; the secondary side of the common mode choke N1Ls is connected to the second end of the fifth capacitor C5 and the positive electrode of the sixth diode D6.

2. The DC-DC converter with dual duty cycles according to claim 1, wherein: The first switch tube S1, the second switch tube S2 and the third switch tube S3 are all IRFZ44N MOSFET switch tubes.

3. The DC-DC converter with dual duty cycles according to claim 1, wherein: The first diode D1 and the third diode D3 are Schottky diodes.

4. The DC-DC converter with dual duty cycles according to claim 1, wherein: The second diode D2 and the fourth diode D4 are fast recovery diodes.

5. The DC-DC converter with dual duty cycles according to claim 1, wherein: The fifth diode D5 and the sixth diode D6 are Zener diodes.

6. The DC-DC converter with dual duty cycles according to claim 1, wherein: The first inductor L1 and the second inductor L2 are WE-PD2 type inductors.

7. The DC-DC converter with dual duty cycles according to claim 1, wherein: The first capacitor C1 and the second capacitor C2 are electrolytic capacitors.

8. The DC-DC converter with dual duty cycles according to claim 1, wherein: The fourth capacitor C4 and the fifth capacitor C5 are ceramic capacitors.

9. The DC-DC converter with dual duty cycles according to claim 1, wherein: The common mode choke coil N1Ls is a PCN type common mode choke coil.

10. The control method of a DC-DC converter with dual duty cycles according to any one of claims 1 to 9, characterized in that: The following steps are involved: The first switch S1 and the second switch S2 are activated simultaneously; the third switch S3, the first diode D1, the second diode D2, and the third diode D3 are all disconnected, and the fourth diode D4 is turned on; the third capacitor C3 is charged, and the first capacitor C1 and the second capacitor C2 are discharged; Cut off the gate signals of the first switch tube S1 and the second switch tube S2, and apply a control signal to the third switch tube S3; the first capacitor C1 maintains a charged level, and the second capacitor C2 and the third capacitor C3 discharge and provide an output load; Turn off the third switch tube S3, the fourth diode D4 and the first diode D1, and turn on the diode D2 and the diode D3; When the currents of the first inductor L1 and the second inductor L2 are zero, the first switch tube S1 and the second switch tube S2 are turned off.

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